qla3xxx.h

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	FM93C56A_WEN = 0x0,
	FM93C56A_WRITE = 0x1,
	FM93C56A_WRITE_ALL = 0x0,
	FM93C56A_WDS = 0x0,
	FM93C56A_ERASE = 0x3,
	FM93C56A_ERASE_ALL = 0x0,
/* Command Extentions */
	FM93C56A_WEN_EXT = 0x3,
	FM93C56A_WRITE_ALL_EXT = 0x1,
	FM93C56A_WDS_EXT = 0x0,
	FM93C56A_ERASE_ALL_EXT = 0x2,
/* Special Bits */
	FM93C56A_READ_DUMMY_BITS = 1,
	FM93C56A_READY = 0,
	FM93C56A_BUSY = 1,
	FM93C56A_CMD_BITS = 2,
/* AM29LV Flash definitions	*/
	FM93C56A_SIZE_8 = 0x100,
	FM93C56A_SIZE_16 = 0x80,
	FM93C66A_SIZE_8 = 0x200,
	FM93C66A_SIZE_16 = 0x100,
	FM93C86A_SIZE_16 = 0x400,
/* Address Bits */
	FM93C56A_NO_ADDR_BITS_16 = 8,
	FM93C56A_NO_ADDR_BITS_8 = 9,
	FM93C86A_NO_ADDR_BITS_16 = 10,
/* Data Bits */
	FM93C56A_DATA_BITS_16 = 16,
	FM93C56A_DATA_BITS_8 = 8,
};
enum {
/* Auburn Bits */
	    AUBURN_EEPROM_DI = 0x8,
	AUBURN_EEPROM_DI_0 = 0x0,
	AUBURN_EEPROM_DI_1 = 0x8,
	AUBURN_EEPROM_DO = 0x4,
	AUBURN_EEPROM_DO_0 = 0x0,
	AUBURN_EEPROM_DO_1 = 0x4,
	AUBURN_EEPROM_CS = 0x2,
	AUBURN_EEPROM_CS_0 = 0x0,
	AUBURN_EEPROM_CS_1 = 0x2,
	AUBURN_EEPROM_CLK_RISE = 0x1,
	AUBURN_EEPROM_CLK_FALL = 0x0,
};
enum {EEPROM_SIZE = FM93C86A_SIZE_16,
	EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16,
	EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16,
};

/*
 *  MAC Config data structure
 */
    struct eeprom_port_cfg {
	u16 etherMtu_mac;
	u16 pauseThreshold_mac;
	u16 resumeThreshold_mac;
	u16 portConfiguration;
#define PORT_CONFIG_DEFAULT                 0xf700
#define PORT_CONFIG_AUTO_NEG_ENABLED        0x8000
#define PORT_CONFIG_SYM_PAUSE_ENABLED       0x4000
#define PORT_CONFIG_FULL_DUPLEX_ENABLED     0x2000
#define PORT_CONFIG_HALF_DUPLEX_ENABLED     0x1000
#define PORT_CONFIG_1000MB_SPEED            0x0400
#define PORT_CONFIG_100MB_SPEED             0x0200
#define PORT_CONFIG_10MB_SPEED              0x0100
#define PORT_CONFIG_LINK_SPEED_MASK         0x0F00
	u16 reserved[12];

};

/*
 * BIOS data structure
 */
struct eeprom_bios_cfg {
	u16 SpinDlyEn:1, disBios:1, EnMemMap:1, EnSelectBoot:1, Reserved:12;

	u8 bootID0:7, boodID0Valid:1;
	u8 bootLun0[8];

	u8 bootID1:7, boodID1Valid:1;
	u8 bootLun1[8];

	u16 MaxLunsTrgt;
	u8 reserved[10];
};

/*
 *  Function Specific Data structure
 */
struct eeprom_function_cfg {
	u8 reserved[30];
	u8 macAddress[6];
	u8 macAddressSecondary[6];

	u16 subsysVendorId;
	u16 subsysDeviceId;
};

/*
 *  EEPROM format
 */
struct eeprom_data {
	u8 asicId[4];
	u8 version;
	u8 numPorts;
	u16 boardId;

#define EEPROM_BOARDID_STR_SIZE   16
#define EEPROM_SERIAL_NUM_SIZE    16

	u8 boardIdStr[16];
	u8 serialNumber[16];
	u16 extHwConfig;
	struct eeprom_port_cfg macCfg_port0;
	struct eeprom_port_cfg macCfg_port1;
	u16 bufletSize;
	u16 bufletCount;
	u16 tcpWindowThreshold50;
	u16 tcpWindowThreshold25;
	u16 tcpWindowThreshold0;
	u16 ipHashTableBaseHi;
	u16 ipHashTableBaseLo;
	u16 ipHashTableSize;
	u16 tcpHashTableBaseHi;
	u16 tcpHashTableBaseLo;
	u16 tcpHashTableSize;
	u16 ncbTableBaseHi;
	u16 ncbTableBaseLo;
	u16 ncbTableSize;
	u16 drbTableBaseHi;
	u16 drbTableBaseLo;
	u16 drbTableSize;
	u16 reserved_142[4];
	u16 ipReassemblyTimeout;
	u16 tcpMaxWindowSize;
	u16 ipSecurity;
#define IPSEC_CONFIG_PRESENT 0x0001
	u8 reserved_156[294];
	u16 qDebug[8];
	struct eeprom_function_cfg funcCfg_fn0;
	u16 reserved_510;
	u8 oemSpace[432];
	struct eeprom_bios_cfg biosCfg_fn1;
	struct eeprom_function_cfg funcCfg_fn1;
	u16 reserved_1022;
	u8 reserved_1024[464];
	struct eeprom_function_cfg funcCfg_fn2;
	u16 reserved_1534;
	u8 reserved_1536[432];
	struct eeprom_bios_cfg biosCfg_fn3;
	struct eeprom_function_cfg funcCfg_fn3;
	u16 checksum;
};

/*
 * General definitions...
 */

/*
 * Below are a number compiler switches for controlling driver behavior.
 * Some are not supported under certain conditions and are notated as such.
 */

#define QL3XXX_VENDOR_ID    0x1077
#define QL3022_DEVICE_ID    0x3022
#define QL3032_DEVICE_ID    0x3032

/* MTU & Frame Size stuff */
#define NORMAL_MTU_SIZE 		ETH_DATA_LEN
#define JUMBO_MTU_SIZE 			9000
#define VLAN_ID_LEN			    2

/* Request Queue Related Definitions */
#define NUM_REQ_Q_ENTRIES   256	/* so that 64 * 64  = 4096 (1 page) */

/* Response Queue Related Definitions */
#define NUM_RSP_Q_ENTRIES   256	/* so that 256 * 16  = 4096 (1 page) */

/* Transmit and Receive Buffers */
#define NUM_LBUFQ_ENTRIES   	128
#define JUMBO_NUM_LBUFQ_ENTRIES 32
#define NUM_SBUFQ_ENTRIES   	64
#define QL_SMALL_BUFFER_SIZE    32
#define QL_ADDR_ELE_PER_BUFQ_ENTRY \
(sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
    /* Each send has at least control block.  This is how many we keep. */
#define NUM_SMALL_BUFFERS     	NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY

#define QL_HEADER_SPACE 32	/* make header space at top of skb. */
/*
 * Large & Small Buffers for Receives
 */
struct lrg_buf_q_entry {

	u32 addr0_lower;
#define IAL_LAST_ENTRY 0x00000001
#define IAL_CONT_ENTRY 0x00000002
#define IAL_FLAG_MASK  0x00000003
	u32 addr0_upper;
	u32 addr1_lower;
	u32 addr1_upper;
	u32 addr2_lower;
	u32 addr2_upper;
	u32 addr3_lower;
	u32 addr3_upper;
	u32 addr4_lower;
	u32 addr4_upper;
	u32 addr5_lower;
	u32 addr5_upper;
	u32 addr6_lower;
	u32 addr6_upper;
	u32 addr7_lower;
	u32 addr7_upper;

};

struct bufq_addr_element {
	u32 addr_low;
	u32 addr_high;
};

#define QL_NO_RESET			0
#define QL_DO_RESET			1

enum link_state_t {
	LS_UNKNOWN = 0,
	LS_DOWN,
	LS_DEGRADE,
	LS_RECOVER,
	LS_UP,
};

struct ql_rcv_buf_cb {
	struct ql_rcv_buf_cb *next;
	struct sk_buff *skb;
	 DECLARE_PCI_UNMAP_ADDR(mapaddr);
	 DECLARE_PCI_UNMAP_LEN(maplen);
	__le32 buf_phy_addr_low;
	__le32 buf_phy_addr_high;
	int index;
};

/*
 * Original IOCB has 3 sg entries:
 * first points to skb-data area
 * second points to first frag
 * third points to next oal.
 * OAL has 5 entries:
 * 1 thru 4 point to frags
 * fifth points to next oal.
 */
#define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1)

struct oal_entry {
	u32 dma_lo;
	u32 dma_hi;
	u32 len;
#define OAL_LAST_ENTRY   0x80000000	/* Last valid buffer in list. */
#define OAL_CONT_ENTRY   0x40000000	/* points to an OAL. (continuation) */
};

struct oal {
	struct oal_entry oal_entry[5];
};

struct map_list {
	 DECLARE_PCI_UNMAP_ADDR(mapaddr);
	 DECLARE_PCI_UNMAP_LEN(maplen);
};

struct ql_tx_buf_cb {
	struct sk_buff *skb;
	struct ob_mac_iocb_req *queue_entry ;
	int seg_count;
	struct oal *oal;
	struct map_list map[MAX_SKB_FRAGS+1];
};

/* definitions for type field */
#define QL_BUF_TYPE_MACIOCB 0x01
#define QL_BUF_TYPE_IPIOCB  0x02
#define QL_BUF_TYPE_TCPIOCB 0x03

/* qdev->flags definitions. */
enum { QL_RESET_DONE = 1,	/* Reset finished. */
	QL_RESET_ACTIVE = 2,	/* Waiting for reset to finish. */
	QL_RESET_START = 3,	/* Please reset the chip. */
	QL_RESET_PER_SCSI = 4,	/* SCSI driver requests reset. */
	QL_TX_TIMEOUT = 5,	/* Timeout in progress. */
	QL_LINK_MASTER = 6,	/* This driver controls the link. */
	QL_ADAPTER_UP = 7,	/* Adapter has been brought up. */
	QL_THREAD_UP = 8,	/* This flag is available. */
	QL_LINK_UP = 9,	/* Link Status. */
	QL_ALLOC_REQ_RSP_Q_DONE = 10,
	QL_ALLOC_BUFQS_DONE = 11,
	QL_ALLOC_SMALL_BUF_DONE = 12,
	QL_LINK_OPTICAL = 13,
	QL_MSI_ENABLED = 14,
};

/*
 * ql3_adapter - The main Adapter structure definition.
 * This structure has all fields relevant to the hardware.
 */

struct ql3_adapter {
	u32 reserved_00;
	unsigned long flags;

	/* PCI Configuration information for this device */
	struct pci_dev *pdev;
	struct net_device *ndev;	/* Parent NET device */

	struct napi_struct napi;

	/* Hardware information */
	u8 chip_rev_id;
	u8 pci_slot;
	u8 pci_width;
	u8 pci_x;
	u32 msi;
	int index;
	struct timer_list adapter_timer;	/* timer used for various functions */

	spinlock_t adapter_lock;
	spinlock_t hw_lock;

	/* PCI Bus Relative Register Addresses */
	u8 __iomem *mmap_virt_base;	/* stores return value from ioremap() */
	struct ql3xxx_port_registers __iomem *mem_map_registers;
	u32 current_page;	/* tracks current register page */

	u32 msg_enable;
	u8 reserved_01[2];
	u8 reserved_02[2];

	/* Page for Shadow Registers */
	void *shadow_reg_virt_addr;
	dma_addr_t shadow_reg_phy_addr;

	/* Net Request Queue */
	u32 req_q_size;
	u32 reserved_03;
	struct ob_mac_iocb_req *req_q_virt_addr;
	dma_addr_t req_q_phy_addr;
	u16 req_producer_index;
	u16 reserved_04;
	u16 *preq_consumer_index;
	u32 req_consumer_index_phy_addr_high;
	u32 req_consumer_index_phy_addr_low;
	atomic_t tx_count;
	struct ql_tx_buf_cb tx_buf[NUM_REQ_Q_ENTRIES];

	/* Net Response Queue */
	u32 rsp_q_size;
	u32 eeprom_cmd_data;
	struct net_rsp_iocb *rsp_q_virt_addr;
	dma_addr_t rsp_q_phy_addr;
	struct net_rsp_iocb *rsp_current;
	u16 rsp_consumer_index;
	u16 reserved_06;
	volatile u32 *prsp_producer_index;
	u32 rsp_producer_index_phy_addr_high;
	u32 rsp_producer_index_phy_addr_low;

	/* Large Buffer Queue */
	u32 lrg_buf_q_alloc_size;
	u32 lrg_buf_q_size;
	void *lrg_buf_q_alloc_virt_addr;
	void *lrg_buf_q_virt_addr;
	dma_addr_t lrg_buf_q_alloc_phy_addr;
	dma_addr_t lrg_buf_q_phy_addr;
	u32 lrg_buf_q_producer_index;
	u32 lrg_buf_release_cnt;
	struct bufq_addr_element *lrg_buf_next_free;
	u32 num_large_buffers;
	u32 num_lbufq_entries;

	/* Large (Receive) Buffers */
	struct ql_rcv_buf_cb *lrg_buf;
	struct ql_rcv_buf_cb *lrg_buf_free_head;
	struct ql_rcv_buf_cb *lrg_buf_free_tail;
	u32 lrg_buf_free_count;
	u32 lrg_buffer_len;
	u32 lrg_buf_index;
	u32 lrg_buf_skb_check;

	/* Small Buffer Queue */
	u32 small_buf_q_alloc_size;
	u32 small_buf_q_size;
	u32 small_buf_q_producer_index;
	void *small_buf_q_alloc_virt_addr;
	void *small_buf_q_virt_addr;
	dma_addr_t small_buf_q_alloc_phy_addr;
	dma_addr_t small_buf_q_phy_addr;
	u32 small_buf_index;

	/* Small (Receive) Buffers */
	void *small_buf_virt_addr;
	dma_addr_t small_buf_phy_addr;
	u32 small_buf_phy_addr_low;
	u32 small_buf_phy_addr_high;
	u32 small_buf_release_cnt;
	u32 small_buf_total_size;

	/* ISR related, saves status for DPC. */
	u32 control_status;

	struct eeprom_data nvram_data;
	struct timer_list ioctl_timer;
	u32 port_link_state;
	u32 last_rsp_offset;

	/* 4022 specific */
	u32 mac_index;		/* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */
	u32 PHYAddr;		/* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */
	u32 mac_ob_opcode;	/* Opcode to use on mac transmission */
	u32 tcp_ob_opcode;	/* Opcode to use on tcp transmission */
	u32 update_ob_opcode;	/* Opcode to use for updating NCB */
	u32 mb_bit_mask;	/* MA Bits mask to use on transmission */
	u32 numPorts;
	struct workqueue_struct *workqueue;
	struct delayed_work reset_work;
	struct delayed_work tx_timeout_work;
	struct delayed_work link_state_work;
	u32 max_frame_size;
	u32 device_id;
	u16 phyType;
};

#endif				/* _QLA3XXX_H_ */