qla3xxx.h

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	INTERNAL_CHIP_RAP_RR = 0x0000,
	INTERNAL_CHIP_RAP_NRM = 0x0004,
	INTERNAL_CHIP_RAP_ERM = 0x0008,
	INTERNAL_CHIP_RAP_ERMx = 0x000C,
	INTERNAL_CHIP_WE = 0x0010,
	INTERNAL_CHIP_EF = 0x0020,
	INTERNAL_CHIP_FR = 0x0040,
	INTERNAL_CHIP_FW = 0x0080,
	INTERNAL_CHIP_FI = 0x0100,
	INTERNAL_CHIP_FT = 0x0200,
};

/* portControl */
enum {
	PORT_CONTROL_DS = 0x0001,
	PORT_CONTROL_HH = 0x0002,
	PORT_CONTROL_EI = 0x0004,
	PORT_CONTROL_ET = 0x0008,
	PORT_CONTROL_EF = 0x0010,
	PORT_CONTROL_DRM = 0x0020,
	PORT_CONTROL_RLB = 0x0040,
	PORT_CONTROL_RCB = 0x0080,
	PORT_CONTROL_MAC = 0x0100,
	PORT_CONTROL_IPV = 0x0200,
	PORT_CONTROL_IFP = 0x0400,
	PORT_CONTROL_ITP = 0x0800,
	PORT_CONTROL_FI = 0x1000,
	PORT_CONTROL_DFP = 0x2000,
	PORT_CONTROL_OI = 0x4000,
	PORT_CONTROL_CC = 0x8000,
};

/* portStatus */
enum {
	PORT_STATUS_SM0 = 0x0001,
	PORT_STATUS_SM1 = 0x0002,
	PORT_STATUS_X = 0x0008,
	PORT_STATUS_DL = 0x0080,
	PORT_STATUS_IC = 0x0200,
	PORT_STATUS_MRC = 0x0400,
	PORT_STATUS_NL = 0x0800,
	PORT_STATUS_REV_ID_MASK = 0x7000,
	PORT_STATUS_REV_ID_1 = 0x1000,
	PORT_STATUS_REV_ID_2 = 0x2000,
	PORT_STATUS_REV_ID_3 = 0x3000,
	PORT_STATUS_64 = 0x8000,
	PORT_STATUS_UP0 = 0x10000,
	PORT_STATUS_AC0 = 0x20000,
	PORT_STATUS_AE0 = 0x40000,
	PORT_STATUS_UP1 = 0x100000,
	PORT_STATUS_AC1 = 0x200000,
	PORT_STATUS_AE1 = 0x400000,
	PORT_STATUS_F0_ENABLED = 0x1000000,
	PORT_STATUS_F1_ENABLED = 0x2000000,
	PORT_STATUS_F2_ENABLED = 0x4000000,
	PORT_STATUS_F3_ENABLED = 0x8000000,
};

/* macMIIMgmtControlReg */
enum {
	MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,
	MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,
	MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,
	MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
	MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,
	MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,
	MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,
	MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
	MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,
	MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080,
};

/* macMIIMgmtControlReg */
enum {
	MAC_MII_CONTROL_RC = 0x0001,
	MAC_MII_CONTROL_SC = 0x0002,
	MAC_MII_CONTROL_AS = 0x0004,
	MAC_MII_CONTROL_NP = 0x0008,
	MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,
	MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,
	MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,
	MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
	MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,
	MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,
	MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,
	MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
	MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,
	MAC_MII_CONTROL_RM = 0x8000,
};

/* macMIIStatusReg */
enum {
	MAC_MII_STATUS_BSY = 0x0001,
	MAC_MII_STATUS_SC = 0x0002,
	MAC_MII_STATUS_NV = 0x0004,
};

enum {
	MAC_CONFIG_REG_PE = 0x0001,
	MAC_CONFIG_REG_TF = 0x0002,
	MAC_CONFIG_REG_RF = 0x0004,
	MAC_CONFIG_REG_FD = 0x0008,
	MAC_CONFIG_REG_GM = 0x0010,
	MAC_CONFIG_REG_LB = 0x0020,
	MAC_CONFIG_REG_SR = 0x8000,
};

enum {
	MAC_HALF_DUPLEX_REG_ED = 0x10000,
	MAC_HALF_DUPLEX_REG_NB = 0x20000,
	MAC_HALF_DUPLEX_REG_BNB = 0x40000,
	MAC_HALF_DUPLEX_REG_ALT = 0x80000,
};

enum {
	IP_ADDR_INDEX_REG_MASK = 0x000f,
	IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,
	IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,
	IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
	IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,
	IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,
	IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
	IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
	IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
	IP_ADDR_INDEX_REG_6 = 0x0008,
	IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
	IP_ADDR_INDEX_REG_E = 0x0040,
};
enum {
	QL3032_PORT_CONTROL_DS = 0x0001,
	QL3032_PORT_CONTROL_HH = 0x0002,
	QL3032_PORT_CONTROL_EIv6 = 0x0004,
	QL3032_PORT_CONTROL_EIv4 = 0x0008,
	QL3032_PORT_CONTROL_ET = 0x0010,
	QL3032_PORT_CONTROL_EF = 0x0020,
	QL3032_PORT_CONTROL_DRM = 0x0040,
	QL3032_PORT_CONTROL_RLB = 0x0080,
	QL3032_PORT_CONTROL_RCB = 0x0100,
	QL3032_PORT_CONTROL_KIE = 0x0200,
};

enum {
	PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,
	PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,
	PROBE_MUX_ADDR_REG_PCICLK = 0x0040,
	PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
	PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,
	PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,
	PROBE_MUX_ADDR_REG_UP = 0x4000,
	PROBE_MUX_ADDR_REG_RE = 0x8000,
};

enum {
	STATISTICS_INDEX_REG_MASK = 0x01ff,
	STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,
	STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,
	STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
	STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,
	STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,
	STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,
	STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
	STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,
	STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,
	STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,
	STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
	STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,
	STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,
	STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,
	STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
	STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,
	STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,
	STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,
	STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
	STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,
	STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,
	STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,
	STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
	STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,
	STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,
	STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,
	STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
	STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,
	STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,
	STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,
	STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
	STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,
	STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,
	STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,
	STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
	STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,
	STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,
	STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,
	STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
	STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,
	STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,
	STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,
	STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
	STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,
	STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,
	STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,
	STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
	STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,
	STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,
	STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,
	STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
	STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f,
};

enum {
	PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,
	PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,
	PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,
	PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
	PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,
	PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,
	PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,
	PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
	PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,
	PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,
	PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,
	PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
	PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,
	PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,
	PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,
	PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
	PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,
	PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,
	PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,
	PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
	PORT_FATAL_ERROR_STATUS_MA = 0x00100000,
	PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,
	PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,
	PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
	PORT_FATAL_ERROR_STATUS_OCE = 0x01000000,
};

/*
 *  port control and status page - page 0
 */

struct ql3xxx_port_registers {
	struct ql3xxx_common_registers CommonRegs;

	u32 ExternalHWConfig;
	u32 InternalChipConfig;
	u32 portControl;
	u32 portStatus;
	u32 macAddrIndirectPtrReg;
	u32 macAddrDataReg;
	u32 macMIIMgmtControlReg;
	u32 macMIIMgmtAddrReg;
	u32 macMIIMgmtDataReg;
	u32 macMIIStatusReg;
	u32 mac0ConfigReg;
	u32 mac0IpgIfgReg;
	u32 mac0HalfDuplexReg;
	u32 mac0MaxFrameLengthReg;
	u32 mac0PauseThresholdReg;
	u32 mac1ConfigReg;
	u32 mac1IpgIfgReg;
	u32 mac1HalfDuplexReg;
	u32 mac1MaxFrameLengthReg;
	u32 mac1PauseThresholdReg;
	u32 ipAddrIndexReg;
	u32 ipAddrDataReg;
	u32 ipReassemblyTimeout;
	u32 tcpMaxWindow;
	u32 currentTcpTimestamp[2];
	u32 internalRamRWAddrReg;
	u32 internalRamWDataReg;
	u32 reclaimedBufferAddrRegLow;
	u32 reclaimedBufferAddrRegHigh;
	u32 tcpConfiguration;
	u32 functionControl;
	u32 fpgaRevID;
	u32 localRamAddr;
	u32 localRamDataAutoIncr;
	u32 localRamDataNonIncr;
	u32 gpOutput;
	u32 gpInput;
	u32 probeMuxAddr;
	u32 probeMuxData;
	u32 statisticsIndexReg;
	u32 statisticsReadDataRegAutoIncr;
	u32 statisticsReadDataRegNoIncr;
	u32 PortFatalErrStatus;
};

/*
 * port host memory config page - page 1
 */
struct ql3xxx_host_memory_registers {
	struct ql3xxx_common_registers CommonRegs;

	u32 reserved[12];

	/* Network Request Queue */
	u32 reqConsumerIndex;
	u32 reqConsumerIndexAddrLow;
	u32 reqConsumerIndexAddrHigh;
	u32 reqBaseAddrLow;
	u32 reqBaseAddrHigh;
	u32 reqLength;

	/* Network Completion Queue */
	u32 rspProducerIndex;
	u32 rspProducerIndexAddrLow;
	u32 rspProducerIndexAddrHigh;
	u32 rspBaseAddrLow;
	u32 rspBaseAddrHigh;
	u32 rspLength;

	/* RX Large Buffer Queue */
	u32 rxLargeQConsumerIndex;
	u32 rxLargeQBaseAddrLow;
	u32 rxLargeQBaseAddrHigh;
	u32 rxLargeQLength;
	u32 rxLargeBufferLength;

	/* RX Small Buffer Queue */
	u32 rxSmallQConsumerIndex;
	u32 rxSmallQBaseAddrLow;
	u32 rxSmallQBaseAddrHigh;
	u32 rxSmallQLength;
	u32 rxSmallBufferLength;

};

/*
 *  port local RAM page - page 2
 */
struct ql3xxx_local_ram_registers {
	struct ql3xxx_common_registers CommonRegs;
	u32 bufletSize;
	u32 maxBufletCount;
	u32 currentBufletCount;
	u32 reserved;
	u32 freeBufletThresholdLow;
	u32 freeBufletThresholdHigh;
	u32 ipHashTableBase;
	u32 ipHashTableCount;
	u32 tcpHashTableBase;
	u32 tcpHashTableCount;
	u32 ncbBase;
	u32 maxNcbCount;
	u32 currentNcbCount;
	u32 drbBase;
	u32 maxDrbCount;
	u32 currentDrbCount;
};

/*
 * definitions for Semaphore bits in Semaphore/Serial NVRAM interface register
 */

#define LS_64BITS(x)    (u32)(0xffffffff & ((u64)x))
#define MS_64BITS(x)    (u32)(0xffffffff & (((u64)x)>>16>>16) )

/*
 * I/O register
 */

enum {
	CONTROL_REG = 0,
	STATUS_REG = 1,
	PHY_STAT_LINK_UP = 0x0004,
	PHY_CTRL_LOOPBACK = 0x4000,

	PETBI_CONTROL_REG = 0x00,
	PETBI_CTRL_ALL_PARAMS = 0x7140,
	PETBI_CTRL_SOFT_RESET = 0x8000,
	PETBI_CTRL_AUTO_NEG = 0x1000,
	PETBI_CTRL_RESTART_NEG = 0x0200,
	PETBI_CTRL_FULL_DUPLEX = 0x0100,
	PETBI_CTRL_SPEED_1000 = 0x0040,

	PETBI_STATUS_REG = 0x01,
	PETBI_STAT_NEG_DONE = 0x0020,
	PETBI_STAT_LINK_UP = 0x0004,

	PETBI_NEG_ADVER = 0x04,
	PETBI_NEG_PAUSE = 0x0080,
	PETBI_NEG_PAUSE_MASK = 0x0180,
	PETBI_NEG_DUPLEX = 0x0020,
	PETBI_NEG_DUPLEX_MASK = 0x0060,

	PETBI_NEG_PARTNER = 0x05,
	PETBI_NEG_ERROR_MASK = 0x3000,

	PETBI_EXPANSION_REG = 0x06,
	PETBI_EXP_PAGE_RX = 0x0002,

	PHY_GIG_CONTROL = 9,
	PHY_GIG_ENABLE_MAN = 0x1000,  /* Enable Master/Slave Manual Config*/
	PHY_GIG_SET_MASTER = 0x0800,  /* Set Master (slave if clear)*/
	PHY_GIG_ALL_PARAMS = 0x0300,
	PHY_GIG_ADV_1000F = 0x0200,
	PHY_GIG_ADV_1000H = 0x0100,

	PHY_NEG_ADVER = 4,
	PHY_NEG_ALL_PARAMS = 0x0fe0,
	PHY_NEG_ASY_PAUSE =  0x0800,
	PHY_NEG_SYM_PAUSE =  0x0400,
	PHY_NEG_ADV_SPEED =  0x01e0,
	PHY_NEG_ADV_100F =   0x0100,
	PHY_NEG_ADV_100H =   0x0080,
	PHY_NEG_ADV_10F =    0x0040,
	PHY_NEG_ADV_10H =    0x0020,

	PETBI_TBI_CTRL = 0x11,
	PETBI_TBI_RESET = 0x8000,
	PETBI_TBI_AUTO_SENSE = 0x0100,
	PETBI_TBI_SERDES_MODE = 0x0010,
	PETBI_TBI_SERDES_WRAP = 0x0002,

	AUX_CONTROL_STATUS = 0x1c,
	PHY_AUX_NEG_DONE = 0x8000,
	PHY_NEG_PARTNER = 5,
	PHY_AUX_DUPLEX_STAT = 0x0020,
	PHY_AUX_SPEED_STAT = 0x0018,
	PHY_AUX_NO_HW_STRAP = 0x0004,
	PHY_AUX_RESET_STICK = 0x0002,
	PHY_NEG_PAUSE = 0x0400,
	PHY_CTRL_SOFT_RESET = 0x8000,
	PHY_CTRL_AUTO_NEG = 0x1000,
	PHY_CTRL_RESTART_NEG = 0x0200,
};
enum {
/* AM29LV Flash definitions	*/
	FM93C56A_START = 0x1,
/* Commands */
	FM93C56A_READ = 0x2,