qla3xxx.h

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/*
 * QLogic QLA3xxx NIC HBA Driver
 * Copyright (c)  2003-2006 QLogic Corporation
 *
 * See LICENSE.qla3xxx for copyright and licensing details.
 */
#ifndef _QLA3XXX_H_
#define _QLA3XXX_H_

/*
 * IOCB Definitions...
 */
#pragma pack(1)

#define OPCODE_OB_MAC_IOCB_FN0          0x01
#define OPCODE_OB_MAC_IOCB_FN2          0x21
#define OPCODE_OB_TCP_IOCB_FN0          0x03
#define OPCODE_OB_TCP_IOCB_FN2          0x23
#define OPCODE_UPDATE_NCB_IOCB_FN0      0x00
#define OPCODE_UPDATE_NCB_IOCB_FN2      0x20

#define OPCODE_UPDATE_NCB_IOCB      0xF0
#define OPCODE_IB_MAC_IOCB          0xF9
#define OPCODE_IB_3032_MAC_IOCB     0x09
#define OPCODE_IB_IP_IOCB           0xFA
#define OPCODE_IB_3032_IP_IOCB      0x0A
#define OPCODE_IB_TCP_IOCB          0xFB
#define OPCODE_DUMP_PROTO_IOCB      0xFE
#define OPCODE_BUFFER_ALERT_IOCB    0xFB

#define OPCODE_FUNC_ID_MASK                 0x30
#define OUTBOUND_MAC_IOCB                   0x01	/* plus function bits */
#define OUTBOUND_TCP_IOCB                   0x03	/* plus function bits */
#define UPDATE_NCB_IOCB                     0x00	/* plus function bits */

#define FN0_MA_BITS_MASK    0x00
#define FN1_MA_BITS_MASK    0x80

struct ob_mac_iocb_req {
	u8 opcode;
	u8 flags;
#define OB_MAC_IOCB_REQ_MA  0xe0
#define OB_MAC_IOCB_REQ_F   0x10
#define OB_MAC_IOCB_REQ_X   0x08
#define OB_MAC_IOCB_REQ_D   0x02
#define OB_MAC_IOCB_REQ_I   0x01
	u8 flags1;
#define OB_3032MAC_IOCB_REQ_IC	0x04
#define OB_3032MAC_IOCB_REQ_TC	0x02
#define OB_3032MAC_IOCB_REQ_UC	0x01
	u8 reserved0;

	__le32 transaction_id;
	__le16 data_len;
	u8 ip_hdr_off;
	u8 ip_hdr_len;
	__le32 reserved1;
	__le32 reserved2;
	__le32 buf_addr0_low;
	__le32 buf_addr0_high;
	__le32 buf_0_len;
	__le32 buf_addr1_low;
	__le32 buf_addr1_high;
	__le32 buf_1_len;
	__le32 buf_addr2_low;
	__le32 buf_addr2_high;
	__le32 buf_2_len;
	__le32 reserved3;
	__le32 reserved4;
};
/*
 * The following constants define control bits for buffer
 * length fields for all IOCB's.
 */
#define OB_MAC_IOCB_REQ_E   0x80000000	/* Last valid buffer in list. */
#define OB_MAC_IOCB_REQ_C   0x40000000	/* points to an OAL. (continuation) */
#define OB_MAC_IOCB_REQ_L   0x20000000	/* Auburn local address pointer. */
#define OB_MAC_IOCB_REQ_R   0x10000000	/* 32-bit address pointer. */

struct ob_mac_iocb_rsp {
	u8 opcode;
	u8 flags;
#define OB_MAC_IOCB_RSP_P   0x08
#define OB_MAC_IOCB_RSP_L   0x04
#define OB_MAC_IOCB_RSP_S   0x02
#define OB_MAC_IOCB_RSP_I   0x01

	__le16 reserved0;
	__le32 transaction_id;
	__le32 reserved1;
	__le32 reserved2;
};

struct ib_mac_iocb_rsp {
	u8 opcode;
#define IB_MAC_IOCB_RSP_V   0x80
	u8 flags;
#define IB_MAC_IOCB_RSP_S   0x80
#define IB_MAC_IOCB_RSP_H1  0x40
#define IB_MAC_IOCB_RSP_H0  0x20
#define IB_MAC_IOCB_RSP_B   0x10
#define IB_MAC_IOCB_RSP_M   0x08
#define IB_MAC_IOCB_RSP_MA  0x07

	__le16 length;
	__le32 reserved;
	__le32 ial_low;
	__le32 ial_high;

};

struct ob_ip_iocb_req {
	u8 opcode;
	__le16 flags;
#define OB_IP_IOCB_REQ_O        0x100
#define OB_IP_IOCB_REQ_H        0x008
#define OB_IP_IOCB_REQ_U        0x004
#define OB_IP_IOCB_REQ_D        0x002
#define OB_IP_IOCB_REQ_I        0x001

	u8 reserved0;

	__le32 transaction_id;
	__le16 data_len;
	__le16 reserved1;
	__le32 hncb_ptr_low;
	__le32 hncb_ptr_high;
	__le32 buf_addr0_low;
	__le32 buf_addr0_high;
	__le32 buf_0_len;
	__le32 buf_addr1_low;
	__le32 buf_addr1_high;
	__le32 buf_1_len;
	__le32 buf_addr2_low;
	__le32 buf_addr2_high;
	__le32 buf_2_len;
	__le32 reserved2;
	__le32 reserved3;
};

/* defines for BufferLength fields above */
#define OB_IP_IOCB_REQ_E    0x80000000
#define OB_IP_IOCB_REQ_C    0x40000000
#define OB_IP_IOCB_REQ_L    0x20000000
#define OB_IP_IOCB_REQ_R    0x10000000

struct ob_ip_iocb_rsp {
	u8 opcode;
	u8 flags;
#define OB_MAC_IOCB_RSP_H       0x10
#define OB_MAC_IOCB_RSP_E       0x08
#define OB_MAC_IOCB_RSP_L       0x04
#define OB_MAC_IOCB_RSP_S       0x02
#define OB_MAC_IOCB_RSP_I       0x01

	__le16 reserved0;
	__le32 transaction_id;
	__le32 reserved1;
	__le32 reserved2;
};

struct ob_tcp_iocb_req {
	u8 opcode;

	u8 flags0;
#define OB_TCP_IOCB_REQ_P       0x80
#define OB_TCP_IOCB_REQ_CI      0x20
#define OB_TCP_IOCB_REQ_H       0x10
#define OB_TCP_IOCB_REQ_LN      0x08
#define OB_TCP_IOCB_REQ_K       0x04
#define OB_TCP_IOCB_REQ_D       0x02
#define OB_TCP_IOCB_REQ_I       0x01

	u8 flags1;
#define OB_TCP_IOCB_REQ_OSM     0x40
#define OB_TCP_IOCB_REQ_URG     0x20
#define OB_TCP_IOCB_REQ_ACK     0x10
#define OB_TCP_IOCB_REQ_PSH     0x08
#define OB_TCP_IOCB_REQ_RST     0x04
#define OB_TCP_IOCB_REQ_SYN     0x02
#define OB_TCP_IOCB_REQ_FIN     0x01

	u8 options_len;
#define OB_TCP_IOCB_REQ_OMASK   0xF0
#define OB_TCP_IOCB_REQ_SHIFT   4

	__le32 transaction_id;
	__le32 data_len;
	__le32 hncb_ptr_low;
	__le32 hncb_ptr_high;
	__le32 buf_addr0_low;
	__le32 buf_addr0_high;
	__le32 buf_0_len;
	__le32 buf_addr1_low;
	__le32 buf_addr1_high;
	__le32 buf_1_len;
	__le32 buf_addr2_low;
	__le32 buf_addr2_high;
	__le32 buf_2_len;
	__le32 time_stamp;
	__le32 reserved1;
};

struct ob_tcp_iocb_rsp {
	u8 opcode;

	u8 flags0;
#define OB_TCP_IOCB_RSP_C       0x20
#define OB_TCP_IOCB_RSP_H       0x10
#define OB_TCP_IOCB_RSP_LN      0x08
#define OB_TCP_IOCB_RSP_K       0x04
#define OB_TCP_IOCB_RSP_D       0x02
#define OB_TCP_IOCB_RSP_I       0x01

	u8 flags1;
#define OB_TCP_IOCB_RSP_E       0x10
#define OB_TCP_IOCB_RSP_W       0x08
#define OB_TCP_IOCB_RSP_P       0x04
#define OB_TCP_IOCB_RSP_T       0x02
#define OB_TCP_IOCB_RSP_F       0x01

	u8 state;
#define OB_TCP_IOCB_RSP_SMASK   0xF0
#define OB_TCP_IOCB_RSP_SHIFT   4

	__le32 transaction_id;
	__le32 local_ncb_ptr;
	__le32 reserved0;
};

struct ib_ip_iocb_rsp {
	u8 opcode;
#define IB_IP_IOCB_RSP_3032_V   0x80
#define IB_IP_IOCB_RSP_3032_O   0x40
#define IB_IP_IOCB_RSP_3032_I   0x20
#define IB_IP_IOCB_RSP_3032_R   0x10
	u8 flags;
#define IB_IP_IOCB_RSP_S        0x80
#define IB_IP_IOCB_RSP_H1       0x40
#define IB_IP_IOCB_RSP_H0       0x20
#define IB_IP_IOCB_RSP_B        0x10
#define IB_IP_IOCB_RSP_M        0x08
#define IB_IP_IOCB_RSP_MA       0x07

	__le16 length;
	__le16 checksum;
#define IB_IP_IOCB_RSP_3032_ICE		0x01
#define IB_IP_IOCB_RSP_3032_CE		0x02
#define IB_IP_IOCB_RSP_3032_NUC		0x04
#define IB_IP_IOCB_RSP_3032_UDP		0x08
#define IB_IP_IOCB_RSP_3032_TCP		0x10
#define IB_IP_IOCB_RSP_3032_IPE		0x20
	__le16 reserved;
#define IB_IP_IOCB_RSP_R        0x01
	__le32 ial_low;
	__le32 ial_high;
};

struct ib_tcp_iocb_rsp {
	u8 opcode;
	u8 flags;
#define IB_TCP_IOCB_RSP_P       0x80
#define IB_TCP_IOCB_RSP_T       0x40
#define IB_TCP_IOCB_RSP_D       0x20
#define IB_TCP_IOCB_RSP_N       0x10
#define IB_TCP_IOCB_RSP_IP      0x03
#define IB_TCP_FLAG_MASK        0xf0
#define IB_TCP_FLAG_IOCB_SYN    0x00

#define TCP_IB_RSP_FLAGS(x) (x->flags & ~IB_TCP_FLAG_MASK)

	__le16 length;
	__le32 hncb_ref_num;
	__le32 ial_low;
	__le32 ial_high;
};

struct net_rsp_iocb {
	u8 opcode;
	u8 flags;
	__le16 reserved0;
	__le32 reserved[3];
};
#pragma pack()

/*
 * Register Definitions...
 */
#define PORT0_PHY_ADDRESS   0x1e00
#define PORT1_PHY_ADDRESS   0x1f00

#define ETHERNET_CRC_SIZE   4

#define MII_SCAN_REGISTER 0x00000001

#define PHY_ID_0_REG    2
#define PHY_ID_1_REG    3

#define PHY_OUI_1_MASK       0xfc00
#define PHY_MODEL_MASK       0x03f0

/*  Address for the Agere Phy */
#define MII_AGERE_ADDR_1  0x00001000
#define MII_AGERE_ADDR_2  0x00001100

/* 32-bit ispControlStatus */
enum {
	ISP_CONTROL_NP_MASK = 0x0003,
	ISP_CONTROL_NP_PCSR = 0x0000,
	ISP_CONTROL_NP_HMCR = 0x0001,
	ISP_CONTROL_NP_LRAMCR = 0x0002,
	ISP_CONTROL_NP_PSR = 0x0003,
	ISP_CONTROL_RI = 0x0008,
	ISP_CONTROL_CI = 0x0010,
	ISP_CONTROL_PI = 0x0020,
	ISP_CONTROL_IN = 0x0040,
	ISP_CONTROL_BE = 0x0080,
	ISP_CONTROL_FN_MASK = 0x0700,
	ISP_CONTROL_FN0_NET = 0x0400,
	ISP_CONTROL_FN0_SCSI = 0x0500,
	ISP_CONTROL_FN1_NET = 0x0600,
	ISP_CONTROL_FN1_SCSI = 0x0700,
	ISP_CONTROL_LINK_DN_0 = 0x0800,
	ISP_CONTROL_LINK_DN_1 = 0x1000,
	ISP_CONTROL_FSR = 0x2000,
	ISP_CONTROL_FE = 0x4000,
	ISP_CONTROL_SR = 0x8000,
};

/* 32-bit ispInterruptMaskReg */
enum {
	ISP_IMR_ENABLE_INT = 0x0004,
	ISP_IMR_DISABLE_RESET_INT = 0x0008,
	ISP_IMR_DISABLE_CMPL_INT = 0x0010,
	ISP_IMR_DISABLE_PROC_INT = 0x0020,
};

/* 32-bit serialPortInterfaceReg */
enum {
	ISP_SERIAL_PORT_IF_CLK = 0x0001,
	ISP_SERIAL_PORT_IF_CS = 0x0002,
	ISP_SERIAL_PORT_IF_D0 = 0x0004,
	ISP_SERIAL_PORT_IF_DI = 0x0008,
	ISP_NVRAM_MASK = (0x000F << 16),
	ISP_SERIAL_PORT_IF_WE = 0x0010,
	ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,
	ISP_SERIAL_PORT_IF_SCI = 0x0400,
	ISP_SERIAL_PORT_IF_SC0 = 0x0800,
	ISP_SERIAL_PORT_IF_SCE = 0x1000,
	ISP_SERIAL_PORT_IF_SDI = 0x2000,
	ISP_SERIAL_PORT_IF_SDO = 0x4000,
	ISP_SERIAL_PORT_IF_SDE = 0x8000,
	ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00,
};

/* semaphoreReg */
enum {
	QL_RESOURCE_MASK_BASE_CODE = 0x7,
	QL_RESOURCE_BITS_BASE_CODE = 0x4,
	QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1),
	QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),
	QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7),
	QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10),
	QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13),
	QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),
	QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)),
	QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)),
	QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)),
	QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16)),
};

 /*
  * QL3XXX memory-mapped registers
  * QL3XXX has 4 "pages" of registers, each page occupying
  * 256 bytes.  Each page has a "common" area at the start and then
  * page-specific registers after that.
  */
struct ql3xxx_common_registers {
	u32 MB0;		/* Offset 0x00 */
	u32 MB1;		/* Offset 0x04 */
	u32 MB2;		/* Offset 0x08 */
	u32 MB3;		/* Offset 0x0c */
	u32 MB4;		/* Offset 0x10 */
	u32 MB5;		/* Offset 0x14 */
	u32 MB6;		/* Offset 0x18 */
	u32 MB7;		/* Offset 0x1c */
	u32 flashBiosAddr;
	u32 flashBiosData;
	u32 ispControlStatus;
	u32 ispInterruptMaskReg;
	u32 serialPortInterfaceReg;
	u32 semaphoreReg;
	u32 reqQProducerIndex;
	u32 rspQConsumerIndex;

	u32 rxLargeQProducerIndex;
	u32 rxSmallQProducerIndex;
	u32 arcMadiCommand;
	u32 arcMadiData;
};

enum {
	EXT_HW_CONFIG_SP_MASK = 0x0006,
	EXT_HW_CONFIG_SP_NONE = 0x0000,
	EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,
	EXT_HW_CONFIG_SP_ECC = 0x0004,
	EXT_HW_CONFIG_SP_ECCx = 0x0006,
	EXT_HW_CONFIG_SIZE_MASK = 0x0060,
	EXT_HW_CONFIG_SIZE_128M = 0x0000,
	EXT_HW_CONFIG_SIZE_256M = 0x0020,
	EXT_HW_CONFIG_SIZE_512M = 0x0040,
	EXT_HW_CONFIG_SIZE_INVALID = 0x0060,
	EXT_HW_CONFIG_PD = 0x0080,
	EXT_HW_CONFIG_FW = 0x0200,
	EXT_HW_CONFIG_US = 0x0400,
	EXT_HW_CONFIG_DCS_MASK = 0x1800,
	EXT_HW_CONFIG_DCS_9MA = 0x0000,
	EXT_HW_CONFIG_DCS_15MA = 0x0800,
	EXT_HW_CONFIG_DCS_18MA = 0x1000,
	EXT_HW_CONFIG_DCS_24MA = 0x1800,
	EXT_HW_CONFIG_DDS_MASK = 0x6000,
	EXT_HW_CONFIG_DDS_9MA = 0x0000,
	EXT_HW_CONFIG_DDS_15MA = 0x2000,
	EXT_HW_CONFIG_DDS_18MA = 0x4000,
	EXT_HW_CONFIG_DDS_24MA = 0x6000,
};

/* InternalChipConfig */
enum {
	INTERNAL_CHIP_DM = 0x0001,
	INTERNAL_CHIP_SD = 0x0002,
	INTERNAL_CHIP_RAP_MASK = 0x000C,