📄 s2io-regs.h
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/* Media Access Controller Register */ u64 mac_int_status; u64 mac_int_mask;#define MAC_INT_STATUS_TMAC_INT s2BIT(0)#define MAC_INT_STATUS_RMAC_INT s2BIT(1) u64 mac_tmac_err_reg;#define TMAC_ECC_SG_ERR s2BIT(7)#define TMAC_ECC_DB_ERR s2BIT(15)#define TMAC_TX_BUF_OVRN s2BIT(23)#define TMAC_TX_CRI_ERR s2BIT(31)#define TMAC_TX_SM_ERR s2BIT(39)#define TMAC_DESC_ECC_SG_ERR s2BIT(47)#define TMAC_DESC_ECC_DB_ERR s2BIT(55) u64 mac_tmac_err_mask; u64 mac_tmac_err_alarm; u64 mac_rmac_err_reg;#define RMAC_RX_BUFF_OVRN s2BIT(0)#define RMAC_FRM_RCVD_INT s2BIT(1)#define RMAC_UNUSED_INT s2BIT(2)#define RMAC_RTS_PNUM_ECC_SG_ERR s2BIT(5)#define RMAC_RTS_DS_ECC_SG_ERR s2BIT(6)#define RMAC_RD_BUF_ECC_SG_ERR s2BIT(7)#define RMAC_RTH_MAP_ECC_SG_ERR s2BIT(8)#define RMAC_RTH_SPDM_ECC_SG_ERR s2BIT(9)#define RMAC_RTS_VID_ECC_SG_ERR s2BIT(10)#define RMAC_DA_SHADOW_ECC_SG_ERR s2BIT(11)#define RMAC_RTS_PNUM_ECC_DB_ERR s2BIT(13)#define RMAC_RTS_DS_ECC_DB_ERR s2BIT(14)#define RMAC_RD_BUF_ECC_DB_ERR s2BIT(15)#define RMAC_RTH_MAP_ECC_DB_ERR s2BIT(16)#define RMAC_RTH_SPDM_ECC_DB_ERR s2BIT(17)#define RMAC_RTS_VID_ECC_DB_ERR s2BIT(18)#define RMAC_DA_SHADOW_ECC_DB_ERR s2BIT(19)#define RMAC_LINK_STATE_CHANGE_INT s2BIT(31)#define RMAC_RX_SM_ERR s2BIT(39)#define RMAC_SINGLE_ECC_ERR (s2BIT(5) | s2BIT(6) | s2BIT(7) |\ s2BIT(8) | s2BIT(9) | s2BIT(10)|\ s2BIT(11))#define RMAC_DOUBLE_ECC_ERR (s2BIT(13) | s2BIT(14) | s2BIT(15) |\ s2BIT(16) | s2BIT(17) | s2BIT(18)|\ s2BIT(19)) u64 mac_rmac_err_mask; u64 mac_rmac_err_alarm; u8 unused14[0x100 - 0x40]; u64 mac_cfg;#define MAC_CFG_TMAC_ENABLE s2BIT(0)#define MAC_CFG_RMAC_ENABLE s2BIT(1)#define MAC_CFG_LAN_NOT_WAN s2BIT(2)#define MAC_CFG_TMAC_LOOPBACK s2BIT(3)#define MAC_CFG_TMAC_APPEND_PAD s2BIT(4)#define MAC_CFG_RMAC_STRIP_FCS s2BIT(5)#define MAC_CFG_RMAC_STRIP_PAD s2BIT(6)#define MAC_CFG_RMAC_PROM_ENABLE s2BIT(7)#define MAC_RMAC_DISCARD_PFRM s2BIT(8)#define MAC_RMAC_BCAST_ENABLE s2BIT(9)#define MAC_RMAC_ALL_ADDR_ENABLE s2BIT(10)#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) u64 tmac_avg_ipg;#define TMAC_AVG_IPG(val) vBIT(val,0,8) u64 rmac_max_pyld_len;#define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14) u64 rmac_err_cfg;#define RMAC_ERR_FCS s2BIT(0)#define RMAC_ERR_FCS_ACCEPT s2BIT(1)#define RMAC_ERR_TOO_LONG s2BIT(1)#define RMAC_ERR_TOO_LONG_ACCEPT s2BIT(1)#define RMAC_ERR_RUNT s2BIT(2)#define RMAC_ERR_RUNT_ACCEPT s2BIT(2)#define RMAC_ERR_LEN_MISMATCH s2BIT(3)#define RMAC_ERR_LEN_MISMATCH_ACCEPT s2BIT(3) u64 rmac_cfg_key;#define RMAC_CFG_KEY(val) vBIT(val,0,16)#define MAX_MAC_ADDRESSES 16#define MAX_MC_ADDRESSES 32 /* Multicast addresses */#define MAC_MAC_ADDR_START_OFFSET 0#define MAC_MC_ADDR_START_OFFSET 16#define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */ u64 rmac_addr_cmd_mem;#define RMAC_ADDR_CMD_MEM_WE s2BIT(7)#define RMAC_ADDR_CMD_MEM_RD 0#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD s2BIT(15)#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING s2BIT(15)#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) u64 rmac_addr_data0_mem;#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)#define RMAC_ADDR_DATA0_MEM_USER s2BIT(48) u64 rmac_addr_data1_mem;#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) u8 unused15[0x8];/* u64 rmac_addr_cfg;#define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)#define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)#define RMAC_ADDR_BCAST_EN vBIT(0)_48#define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49*/ u64 tmac_ipg_cfg; u64 rmac_pause_cfg;#define RMAC_PAUSE_GEN s2BIT(0)#define RMAC_PAUSE_GEN_ENABLE s2BIT(0)#define RMAC_PAUSE_RX s2BIT(1)#define RMAC_PAUSE_RX_ENABLE s2BIT(1)#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)#define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) u64 rmac_red_cfg; u64 rmac_red_rate_q0q3; u64 rmac_red_rate_q4q7; u64 mac_link_util;#define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)#define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)#define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)#define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)#define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)#define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)#define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \ MAC_RX_LINK_UTIL_DISABLE u64 rmac_invalid_ipg;/* rx traffic steering */#define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) u64 rts_frm_len_n[8]; u64 rts_qos_steering;#define MAX_DIX_MAP 4 u64 rts_dix_map_n[MAX_DIX_MAP];#define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)#define RTS_DIX_MAP_SCW(val) s2BIT(val,21) u64 rts_q_alternates; u64 rts_default_q; u64 rts_ctrl;#define RTS_CTRL_IGNORE_SNAP_OUI s2BIT(2)#define RTS_CTRL_IGNORE_LLC_CTRL s2BIT(3) u64 rts_pn_cam_ctrl;#define RTS_PN_CAM_CTRL_WE s2BIT(7)#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD s2BIT(15)#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED s2BIT(15)#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) u64 rts_pn_cam_data;#define RTS_PN_CAM_DATA_TCP_SELECT s2BIT(7)#define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)#define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) u64 rts_ds_mem_ctrl;#define RTS_DS_MEM_CTRL_WE s2BIT(7)#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD s2BIT(15)#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED s2BIT(15)#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) u64 rts_ds_mem_data;#define RTS_DS_MEM_DATA(n) vBIT(n,0,8) u8 unused16[0x700 - 0x220]; u64 mac_debug_ctrl;#define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL u8 unused17[0x2800 - 0x2708];/* memory controller registers */ u64 mc_int_status;#define MC_INT_STATUS_MC_INT s2BIT(0) u64 mc_int_mask;#define MC_INT_MASK_MC_INT s2BIT(0) u64 mc_err_reg;#define MC_ERR_REG_ECC_DB_ERR_L s2BIT(14)#define MC_ERR_REG_ECC_DB_ERR_U s2BIT(15)#define MC_ERR_REG_MIRI_ECC_DB_ERR_0 s2BIT(18)#define MC_ERR_REG_MIRI_ECC_DB_ERR_1 s2BIT(20)#define MC_ERR_REG_MIRI_CRI_ERR_0 s2BIT(22)#define MC_ERR_REG_MIRI_CRI_ERR_1 s2BIT(23)#define MC_ERR_REG_SM_ERR s2BIT(31)#define MC_ERR_REG_ECC_ALL_SNG (s2BIT(2) | s2BIT(3) | s2BIT(4) | s2BIT(5) |\ s2BIT(17) | s2BIT(19))#define MC_ERR_REG_ECC_ALL_DBL (s2BIT(10) | s2BIT(11) | s2BIT(12) |\ s2BIT(13) | s2BIT(18) | s2BIT(20))#define PLL_LOCK_N s2BIT(39) u64 mc_err_mask; u64 mc_err_alarm; u8 unused18[0x100 - 0x28];/* MC configuration */ u64 rx_queue_cfg;#define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) u64 mc_rldram_mrs;#define MC_RLDRAM_QUEUE_SIZE_ENABLE s2BIT(39)#define MC_RLDRAM_MRS_ENABLE s2BIT(47) u64 mc_rldram_interleave; u64 mc_pause_thresh_q0q3; u64 mc_pause_thresh_q4q7; u64 mc_red_thresh_q[8]; u8 unused19[0x200 - 0x168]; u64 mc_rldram_ref_per; u8 unused20[0x220 - 0x208]; u64 mc_rldram_test_ctrl;#define MC_RLDRAM_TEST_MODE s2BIT(47)#define MC_RLDRAM_TEST_WRITE s2BIT(7)#define MC_RLDRAM_TEST_GO s2BIT(15)#define MC_RLDRAM_TEST_DONE s2BIT(23)#define MC_RLDRAM_TEST_PASS s2BIT(31) u8 unused21[0x240 - 0x228]; u64 mc_rldram_test_add; u8 unused22[0x260 - 0x248]; u64 mc_rldram_test_d0; u8 unused23[0x280 - 0x268]; u64 mc_rldram_test_d1; u8 unused24[0x300 - 0x288]; u64 mc_rldram_test_d2; u8 unused24_1[0x360 - 0x308]; u64 mc_rldram_ctrl;#define MC_RLDRAM_ENABLE_ODT s2BIT(7) u8 unused24_2[0x640 - 0x368]; u64 mc_rldram_ref_per_herc;#define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16) u8 unused24_3[0x660 - 0x648]; u64 mc_rldram_mrs_herc; u8 unused25[0x700 - 0x668]; u64 mc_debug_ctrl; u8 unused26[0x3000 - 0x2f08];/* XGXG */ /* XGXS control registers */ u64 xgxs_int_status;#define XGXS_INT_STATUS_TXGXS s2BIT(0)#define XGXS_INT_STATUS_RXGXS s2BIT(1) u64 xgxs_int_mask;#define XGXS_INT_MASK_TXGXS s2BIT(0)#define XGXS_INT_MASK_RXGXS s2BIT(1) u64 xgxs_txgxs_err_reg;#define TXGXS_ECC_SG_ERR s2BIT(7)#define TXGXS_ECC_DB_ERR s2BIT(15)#define TXGXS_ESTORE_UFLOW s2BIT(31)#define TXGXS_TX_SM_ERR s2BIT(39) u64 xgxs_txgxs_err_mask; u64 xgxs_txgxs_err_alarm; u64 xgxs_rxgxs_err_reg;#define RXGXS_ESTORE_OFLOW s2BIT(7)#define RXGXS_RX_SM_ERR s2BIT(39) u64 xgxs_rxgxs_err_mask; u64 xgxs_rxgxs_err_alarm; u8 unused27[0x100 - 0x40]; u64 xgxs_cfg; u64 xgxs_status; u64 xgxs_cfg_key; u64 xgxs_efifo_cfg; /* CHANGED */ u64 rxgxs_ber_0; /* CHANGED */ u64 rxgxs_ber_1; /* CHANGED */ u64 spi_control;#define SPI_CONTROL_KEY(key) vBIT(key,0,4)#define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3)#define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8)#define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24)#define SPI_CONTROL_SEL1 s2BIT(4)#define SPI_CONTROL_REQ s2BIT(7)#define SPI_CONTROL_NACK s2BIT(5)#define SPI_CONTROL_DONE s2BIT(6) u64 spi_data;#define SPI_DATA_WRITE(data,len) vBIT(data,0,len)};#define XENA_REG_SPACE sizeof(struct XENA_dev_config)#define XENA_EEPROM_SPACE (0x01 << 11)#endif /* _REGS_H */⌨️ 快捷键说明
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