📄 s2io-regs.h
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#define TXDMA_PFC_INT s2BIT(0)#define TXDMA_TDA_INT s2BIT(1)#define TXDMA_PCC_INT s2BIT(2)#define TXDMA_TTI_INT s2BIT(3)#define TXDMA_LSO_INT s2BIT(4)#define TXDMA_TPA_INT s2BIT(5)#define TXDMA_SM_INT s2BIT(6) u64 pfc_err_reg;#define PFC_ECC_SG_ERR s2BIT(7)#define PFC_ECC_DB_ERR s2BIT(15)#define PFC_SM_ERR_ALARM s2BIT(23)#define PFC_MISC_0_ERR s2BIT(31)#define PFC_MISC_1_ERR s2BIT(32)#define PFC_PCIX_ERR s2BIT(39) u64 pfc_err_mask; u64 pfc_err_alarm; u64 tda_err_reg;#define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8)#define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8)#define TDA_SM0_ERR_ALARM s2BIT(22)#define TDA_SM1_ERR_ALARM s2BIT(23)#define TDA_PCIX_ERR s2BIT(39) u64 tda_err_mask; u64 tda_err_alarm; u64 pcc_err_reg;#define PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8)#define PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8)#define PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8)#define PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8)#define PCC_SM_ERR_ALARM vBIT(0xff,32,8)#define PCC_WR_ERR_ALARM vBIT(0xff,40,8)#define PCC_N_SERR vBIT(0xff,48,8)#define PCC_6_COF_OV_ERR s2BIT(56)#define PCC_7_COF_OV_ERR s2BIT(57)#define PCC_6_LSO_OV_ERR s2BIT(58)#define PCC_7_LSO_OV_ERR s2BIT(59)#define PCC_ENABLE_FOUR vBIT(0x0F,0,8) u64 pcc_err_mask; u64 pcc_err_alarm; u64 tti_err_reg;#define TTI_ECC_SG_ERR s2BIT(7)#define TTI_ECC_DB_ERR s2BIT(15)#define TTI_SM_ERR_ALARM s2BIT(23) u64 tti_err_mask; u64 tti_err_alarm; u64 lso_err_reg;#define LSO6_SEND_OFLOW s2BIT(12)#define LSO7_SEND_OFLOW s2BIT(13)#define LSO6_ABORT s2BIT(14)#define LSO7_ABORT s2BIT(15)#define LSO6_SM_ERR_ALARM s2BIT(22)#define LSO7_SM_ERR_ALARM s2BIT(23) u64 lso_err_mask; u64 lso_err_alarm; u64 tpa_err_reg;#define TPA_TX_FRM_DROP s2BIT(7)#define TPA_SM_ERR_ALARM s2BIT(23) u64 tpa_err_mask; u64 tpa_err_alarm; u64 sm_err_reg;#define SM_SM_ERR_ALARM s2BIT(15) u64 sm_err_mask; u64 sm_err_alarm; u8 unused8[0x100 - 0xB8];/* TxDMA arbiter */ u64 tx_dma_wrap_stat;/* Tx FIFO controller */#define X_MAX_FIFOS 8#define X_FIFO_MAX_LEN 0x1FFF /*8191 */ u64 tx_fifo_partition_0;#define TX_FIFO_PARTITION_EN s2BIT(0)#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) u64 tx_fifo_partition_1;#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) u64 tx_fifo_partition_2;#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) u64 tx_fifo_partition_3;#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)#define TX_FIFO_PARTITION_PRI_0 0 /* highest */#define TX_FIFO_PARTITION_PRI_1 1#define TX_FIFO_PARTITION_PRI_2 2#define TX_FIFO_PARTITION_PRI_3 3#define TX_FIFO_PARTITION_PRI_4 4#define TX_FIFO_PARTITION_PRI_5 5#define TX_FIFO_PARTITION_PRI_6 6#define TX_FIFO_PARTITION_PRI_7 7 /* lowest */ u64 tx_w_round_robin_0; u64 tx_w_round_robin_1; u64 tx_w_round_robin_2; u64 tx_w_round_robin_3; u64 tx_w_round_robin_4; u64 tti_command_mem;#define TTI_CMD_MEM_WE s2BIT(7)#define TTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)#define TTI_CMD_MEM_STROBE_BEING_EXECUTED s2BIT(15)#define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) u64 tti_data1_mem;#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)#define TTI_DATA1_MEM_TX_TIMER_AC_EN s2BIT(38)#define TTI_DATA1_MEM_TX_TIMER_CI_EN s2BIT(39)#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) u64 tti_data2_mem;#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)/* Tx Protocol assist */ u64 tx_pa_cfg;#define TX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)#define TX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)#define TX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)#define TX_PA_CFG_IGNORE_L2_ERR s2BIT(6)#define RX_PA_CFG_STRIP_VLAN_TAG s2BIT(15)/* Recent add, used only debug purposes. */ u64 pcc_enable; u8 unused9[0x700 - 0x178]; u64 txdma_debug_ctrl; u8 unused10[0x1800 - 0x1708];/* RxDMA Registers */ u64 rxdma_int_status; u64 rxdma_int_mask;#define RXDMA_INT_RC_INT_M s2BIT(0)#define RXDMA_INT_RPA_INT_M s2BIT(1)#define RXDMA_INT_RDA_INT_M s2BIT(2)#define RXDMA_INT_RTI_INT_M s2BIT(3) u64 rda_err_reg;#define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8)#define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8)#define RDA_FRM_ECC_SG_ERR s2BIT(23)#define RDA_FRM_ECC_DB_N_AERR s2BIT(31)#define RDA_SM1_ERR_ALARM s2BIT(38)#define RDA_SM0_ERR_ALARM s2BIT(39)#define RDA_MISC_ERR s2BIT(47)#define RDA_PCIX_ERR s2BIT(55)#define RDA_RXD_ECC_DB_SERR s2BIT(63) u64 rda_err_mask; u64 rda_err_alarm; u64 rc_err_reg;#define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8)#define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8)#define RC_FTC_ECC_SG_ERR s2BIT(23)#define RC_FTC_ECC_DB_ERR s2BIT(31)#define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8)#define RC_FTC_SM_ERR_ALARM s2BIT(47)#define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8) u64 rc_err_mask; u64 rc_err_alarm; u64 prc_pcix_err_reg;#define PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8)#define PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8)#define PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8)#define PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8)#define PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8)#define PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8) u64 prc_pcix_err_mask; u64 prc_pcix_err_alarm; u64 rpa_err_reg;#define RPA_ECC_SG_ERR s2BIT(7)#define RPA_ECC_DB_ERR s2BIT(15)#define RPA_FLUSH_REQUEST s2BIT(22)#define RPA_SM_ERR_ALARM s2BIT(23)#define RPA_CREDIT_ERR s2BIT(31) u64 rpa_err_mask; u64 rpa_err_alarm; u64 rti_err_reg;#define RTI_ECC_SG_ERR s2BIT(7)#define RTI_ECC_DB_ERR s2BIT(15)#define RTI_SM_ERR_ALARM s2BIT(23) u64 rti_err_mask; u64 rti_err_alarm; u8 unused11[0x100 - 0x88];/* DMA arbiter */ u64 rx_queue_priority;#define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)#define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)#define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)#define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)#define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)#define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)#define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)#define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)#define RX_QUEUE_PRI_0 0 /* highest */#define RX_QUEUE_PRI_1 1#define RX_QUEUE_PRI_2 2#define RX_QUEUE_PRI_3 3#define RX_QUEUE_PRI_4 4#define RX_QUEUE_PRI_5 5#define RX_QUEUE_PRI_6 6#define RX_QUEUE_PRI_7 7 /* lowest */ u64 rx_w_round_robin_0; u64 rx_w_round_robin_1; u64 rx_w_round_robin_2; u64 rx_w_round_robin_3; u64 rx_w_round_robin_4; /* Per-ring controller regs */#define RX_MAX_RINGS 8#if 0#define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */#define RX_MIN_RINGS_SZ 0x3F /* 63 */#endif u64 prc_rxd0_n[RX_MAX_RINGS]; u64 prc_ctrl_n[RX_MAX_RINGS];#define PRC_CTRL_RC_ENABLED s2BIT(7)#define PRC_CTRL_RING_MODE (s2BIT(14)|s2BIT(15))#define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)#define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)#define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)#define PRC_CTRL_RING_MODE_x vBIT(3,14,2)#define PRC_CTRL_NO_SNOOP (s2BIT(22)|s2BIT(23))#define PRC_CTRL_NO_SNOOP_DESC s2BIT(22)#define PRC_CTRL_NO_SNOOP_BUFF s2BIT(23)#define PRC_CTRL_BIMODAL_INTERRUPT s2BIT(37)#define PRC_CTRL_GROUP_READS s2BIT(38)#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) u64 prc_alarm_action;#define PRC_ALARM_ACTION_RR_R0_STOP s2BIT(3)#define PRC_ALARM_ACTION_RW_R0_STOP s2BIT(7)#define PRC_ALARM_ACTION_RR_R1_STOP s2BIT(11)#define PRC_ALARM_ACTION_RW_R1_STOP s2BIT(15)#define PRC_ALARM_ACTION_RR_R2_STOP s2BIT(19)#define PRC_ALARM_ACTION_RW_R2_STOP s2BIT(23)#define PRC_ALARM_ACTION_RR_R3_STOP s2BIT(27)#define PRC_ALARM_ACTION_RW_R3_STOP s2BIT(31)#define PRC_ALARM_ACTION_RR_R4_STOP s2BIT(35)#define PRC_ALARM_ACTION_RW_R4_STOP s2BIT(39)#define PRC_ALARM_ACTION_RR_R5_STOP s2BIT(43)#define PRC_ALARM_ACTION_RW_R5_STOP s2BIT(47)#define PRC_ALARM_ACTION_RR_R6_STOP s2BIT(51)#define PRC_ALARM_ACTION_RW_R6_STOP s2BIT(55)#define PRC_ALARM_ACTION_RR_R7_STOP s2BIT(59)#define PRC_ALARM_ACTION_RW_R7_STOP s2BIT(63)/* Receive traffic interrupts */ u64 rti_command_mem;#define RTI_CMD_MEM_WE s2BIT(7)#define RTI_CMD_MEM_STROBE s2BIT(15)#define RTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED s2BIT(15)#define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) u64 rti_data1_mem;#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)#define RTI_DATA1_MEM_RX_TIMER_AC_EN s2BIT(38)#define RTI_DATA1_MEM_RX_TIMER_CI_EN s2BIT(39)#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) u64 rti_data2_mem;#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) u64 rx_pa_cfg;#define RX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)#define RX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)#define RX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)#define RX_PA_CFG_IGNORE_L2_ERR s2BIT(6) u64 unused_11_1; u64 ring_bump_counter1; u64 ring_bump_counter2; u8 unused12[0x700 - 0x1F0]; u64 rxdma_debug_ctrl; u8 unused13[0x2000 - 0x1f08];⌨️ 快捷键说明
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