📄 s2io-regs.h
字号:
/************************************************************************ * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC * Copyright(c) 2002-2007 Neterion Inc. * This software may be used and distributed according to the terms of * the GNU General Public License (GPL), incorporated herein by reference. * Drivers based on or derived from this code fall under the GPL and must * retain the authorship, copyright and license notice. This file is not * a complete program and may only be used when the entire operating * system is licensed under the GPL. * See the file COPYING in this distribution for more information. ************************************************************************/#ifndef _REGS_H#define _REGS_H#define TBD 0struct XENA_dev_config {/* Convention: mHAL_XXX is mask, vHAL_XXX is value *//* General Control-Status Registers */ u64 general_int_status;#define GEN_INTR_TXPIC s2BIT(0)#define GEN_INTR_TXDMA s2BIT(1)#define GEN_INTR_TXMAC s2BIT(2)#define GEN_INTR_TXXGXS s2BIT(3)#define GEN_INTR_TXTRAFFIC s2BIT(8)#define GEN_INTR_RXPIC s2BIT(32)#define GEN_INTR_RXDMA s2BIT(33)#define GEN_INTR_RXMAC s2BIT(34)#define GEN_INTR_MC s2BIT(35)#define GEN_INTR_RXXGXS s2BIT(36)#define GEN_INTR_RXTRAFFIC s2BIT(40)#define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \ GEN_INTR_TXDMA | GEN_INTR_RXDMA | \ GEN_INTR_TXMAC | GEN_INTR_RXMAC | \ GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \ GEN_INTR_MC u64 general_int_mask; u8 unused0[0x100 - 0x10]; u64 sw_reset;/* XGXS must be removed from reset only once. */#define SW_RESET_XENA vBIT(0xA5,0,8)#define SW_RESET_FLASH vBIT(0xA5,8,8)#define SW_RESET_EOI vBIT(0xA5,16,8)#define SW_RESET_ALL (SW_RESET_XENA | \ SW_RESET_FLASH | \ SW_RESET_EOI)/* The SW_RESET register must read this value after a successful reset. */#define SW_RESET_RAW_VAL 0xA5000000 u64 adapter_status;#define ADAPTER_STATUS_TDMA_READY s2BIT(0)#define ADAPTER_STATUS_RDMA_READY s2BIT(1)#define ADAPTER_STATUS_PFC_READY s2BIT(2)#define ADAPTER_STATUS_TMAC_BUF_EMPTY s2BIT(3)#define ADAPTER_STATUS_PIC_QUIESCENT s2BIT(5)#define ADAPTER_STATUS_RMAC_REMOTE_FAULT s2BIT(6)#define ADAPTER_STATUS_RMAC_LOCAL_FAULT s2BIT(7)#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8)#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)#define ADAPTER_STATUS_MC_DRAM_READY s2BIT(24)#define ADAPTER_STATUS_MC_QUEUES_READY s2BIT(25)#define ADAPTER_STATUS_RIC_RUNNING s2BIT(26)#define ADAPTER_STATUS_M_PLL_LOCK s2BIT(30)#define ADAPTER_STATUS_P_PLL_LOCK s2BIT(31) u64 adapter_control;#define ADAPTER_CNTL_EN s2BIT(7)#define ADAPTER_EOI_TX_ON s2BIT(15)#define ADAPTER_LED_ON s2BIT(23)#define ADAPTER_UDPI(val) vBIT(val,36,4)#define ADAPTER_WAIT_INT s2BIT(48)#define ADAPTER_ECC_EN s2BIT(55) u64 serr_source;#define SERR_SOURCE_PIC s2BIT(0)#define SERR_SOURCE_TXDMA s2BIT(1)#define SERR_SOURCE_RXDMA s2BIT(2)#define SERR_SOURCE_MAC s2BIT(3)#define SERR_SOURCE_MC s2BIT(4)#define SERR_SOURCE_XGXS s2BIT(5)#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \ SERR_SOURCE_TXDMA | \ SERR_SOURCE_RXDMA | \ SERR_SOURCE_MAC | \ SERR_SOURCE_MC | \ SERR_SOURCE_XGXS) u64 pci_mode;#define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60)#define PCI_MODE_PCI_33 0#define PCI_MODE_PCI_66 0x1#define PCI_MODE_PCIX_M1_66 0x2#define PCI_MODE_PCIX_M1_100 0x3#define PCI_MODE_PCIX_M1_133 0x4#define PCI_MODE_PCIX_M2_66 0x5#define PCI_MODE_PCIX_M2_100 0x6#define PCI_MODE_PCIX_M2_133 0x7#define PCI_MODE_UNSUPPORTED s2BIT(0)#define PCI_MODE_32_BITS s2BIT(8)#define PCI_MODE_UNKNOWN_MODE s2BIT(9) u8 unused_0[0x800 - 0x128];/* PCI-X Controller registers */ u64 pic_int_status; u64 pic_int_mask;#define PIC_INT_TX s2BIT(0)#define PIC_INT_FLSH s2BIT(1)#define PIC_INT_MDIO s2BIT(2)#define PIC_INT_IIC s2BIT(3)#define PIC_INT_GPIO s2BIT(4)#define PIC_INT_RX s2BIT(32) u64 txpic_int_reg; u64 txpic_int_mask;#define PCIX_INT_REG_ECC_SG_ERR s2BIT(0)#define PCIX_INT_REG_ECC_DB_ERR s2BIT(1)#define PCIX_INT_REG_FLASHR_R_FSM_ERR s2BIT(8)#define PCIX_INT_REG_FLASHR_W_FSM_ERR s2BIT(9)#define PCIX_INT_REG_INI_TX_FSM_SERR s2BIT(10)#define PCIX_INT_REG_INI_TXO_FSM_ERR s2BIT(11)#define PCIX_INT_REG_TRT_FSM_SERR s2BIT(13)#define PCIX_INT_REG_SRT_FSM_SERR s2BIT(14)#define PCIX_INT_REG_PIFR_FSM_SERR s2BIT(15)#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR s2BIT(21)#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR s2BIT(23)#define PCIX_INT_REG_INI_RX_FSM_SERR s2BIT(48)#define PCIX_INT_REG_RA_RX_FSM_SERR s2BIT(50)/*#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR s2BIT(52)#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR s2BIT(54)#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR s2BIT(58)*/ u64 txpic_alarms; u64 rxpic_int_reg; u64 rxpic_int_mask; u64 rxpic_alarms; u64 flsh_int_reg; u64 flsh_int_mask;#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR s2BIT(63)#define PIC_FLSH_INT_REG_ERR s2BIT(62) u64 flash_alarms; u64 mdio_int_reg; u64 mdio_int_mask;#define MDIO_INT_REG_MDIO_BUS_ERR s2BIT(0)#define MDIO_INT_REG_DTX_BUS_ERR s2BIT(8)#define MDIO_INT_REG_LASI s2BIT(39) u64 mdio_alarms; u64 iic_int_reg; u64 iic_int_mask;#define IIC_INT_REG_BUS_FSM_ERR s2BIT(4)#define IIC_INT_REG_BIT_FSM_ERR s2BIT(5)#define IIC_INT_REG_CYCLE_FSM_ERR s2BIT(6)#define IIC_INT_REG_REQ_FSM_ERR s2BIT(7)#define IIC_INT_REG_ACK_ERR s2BIT(8) u64 iic_alarms; u8 unused4[0x08]; u64 gpio_int_reg;#define GPIO_INT_REG_DP_ERR_INT s2BIT(0)#define GPIO_INT_REG_LINK_DOWN s2BIT(1)#define GPIO_INT_REG_LINK_UP s2BIT(2) u64 gpio_int_mask;#define GPIO_INT_MASK_LINK_DOWN s2BIT(1)#define GPIO_INT_MASK_LINK_UP s2BIT(2) u64 gpio_alarms; u8 unused5[0x38]; u64 tx_traffic_int;#define TX_TRAFFIC_INT_n(n) s2BIT(n) u64 tx_traffic_mask; u64 rx_traffic_int;#define RX_TRAFFIC_INT_n(n) s2BIT(n) u64 rx_traffic_mask;/* PIC Control registers */ u64 pic_control;#define PIC_CNTL_RX_ALARM_MAP_1 s2BIT(0)#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5) u64 swapper_ctrl;#define SWAPPER_CTRL_PIF_R_FE s2BIT(0)#define SWAPPER_CTRL_PIF_R_SE s2BIT(1)#define SWAPPER_CTRL_PIF_W_FE s2BIT(8)#define SWAPPER_CTRL_PIF_W_SE s2BIT(9)#define SWAPPER_CTRL_TXP_FE s2BIT(16)#define SWAPPER_CTRL_TXP_SE s2BIT(17)#define SWAPPER_CTRL_TXD_R_FE s2BIT(18)#define SWAPPER_CTRL_TXD_R_SE s2BIT(19)#define SWAPPER_CTRL_TXD_W_FE s2BIT(20)#define SWAPPER_CTRL_TXD_W_SE s2BIT(21)#define SWAPPER_CTRL_TXF_R_FE s2BIT(22)#define SWAPPER_CTRL_TXF_R_SE s2BIT(23)#define SWAPPER_CTRL_RXD_R_FE s2BIT(32)#define SWAPPER_CTRL_RXD_R_SE s2BIT(33)#define SWAPPER_CTRL_RXD_W_FE s2BIT(34)#define SWAPPER_CTRL_RXD_W_SE s2BIT(35)#define SWAPPER_CTRL_RXF_W_FE s2BIT(36)#define SWAPPER_CTRL_RXF_W_SE s2BIT(37)#define SWAPPER_CTRL_XMSI_FE s2BIT(40)#define SWAPPER_CTRL_XMSI_SE s2BIT(41)#define SWAPPER_CTRL_STATS_FE s2BIT(48)#define SWAPPER_CTRL_STATS_SE s2BIT(49) u64 pif_rd_swapper_fb;#define IF_RD_SWAPPER_FB 0x0123456789ABCDEF u64 scheduled_int_ctrl;#define SCHED_INT_CTRL_TIMER_EN s2BIT(0)#define SCHED_INT_CTRL_ONE_SHOT s2BIT(1)#define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6)#define SCHED_INT_PERIOD TBD u64 txreqtimeout;#define TXREQTO_VAL(val) vBIT(val,0,32)#define TXREQTO_EN s2BIT(63) u64 statsreqtimeout;#define STATREQTO_VAL(n) TBD#define STATREQTO_EN s2BIT(63) u64 read_retry_delay; u64 read_retry_acceleration; u64 write_retry_delay; u64 write_retry_acceleration; u64 xmsi_control; u64 xmsi_access; u64 xmsi_address; u64 xmsi_data; u64 rx_mat;#define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8) u8 unused6[0x8]; u64 tx_mat0_n[0x8];#define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8) u8 unused_1[0x8]; u64 stat_byte_cnt;#define STAT_BC(n) vBIT(n,4,12) /* Automated statistics collection */ u64 stat_cfg;#define STAT_CFG_STAT_EN s2BIT(0)#define STAT_CFG_ONE_SHOT_EN s2BIT(1)#define STAT_CFG_STAT_NS_EN s2BIT(8)#define STAT_CFG_STAT_RO s2BIT(9)#define STAT_TRSF_PER(n) TBD#define PER_SEC 0x208d5#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)#define SET_UPDT_CLICKS(val) vBIT(val, 32, 32) u64 stat_addr; /* General Configuration */ u64 mdio_control;#define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16)#define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5)#define MDIO_MMD_PMA_DEV_ADDR 0x1#define MDIO_MMD_PMD_DEV_ADDR 0x1#define MDIO_MMD_WIS_DEV_ADDR 0x2#define MDIO_MMD_PCS_DEV_ADDR 0x3#define MDIO_MMD_PHYXS_DEV_ADDR 0x4#define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5)#define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4)#define MDIO_OP(val) vBIT(val, 60, 2)#define MDIO_OP_ADDR_TRANS 0x0#define MDIO_OP_WRITE_TRANS 0x1#define MDIO_OP_READ_POST_INC_TRANS 0x2#define MDIO_OP_READ_TRANS 0x3#define MDIO_MDIO_DATA(val) vBIT(val, 32, 16) u64 dtx_control; u64 i2c_control;#define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)#define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)#define I2C_CONTROL_READ s2BIT(24)#define I2C_CONTROL_NACK s2BIT(25)#define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)#define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) u64 gpio_control;#define GPIO_CTRL_GPIO_0 s2BIT(8) u64 misc_control;#define FAULT_BEHAVIOUR s2BIT(0)#define EXT_REQ_EN s2BIT(1)#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3) u8 unused7_1[0x230 - 0x208]; u64 pic_control2; u64 ini_dperr_ctrl; u64 wreq_split_mask;#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12) u8 unused7_2[0x800 - 0x248];/* TxDMA registers */ u64 txdma_int_status; u64 txdma_int_mask;⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -