t3_cpl.h

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/*
 * Copyright (c) 2004-2007 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef T3_CPL_H
#define T3_CPL_H

#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
# include <asm/byteorder.h>
#endif

enum CPL_opcode {
	CPL_PASS_OPEN_REQ = 0x1,
	CPL_PASS_ACCEPT_RPL = 0x2,
	CPL_ACT_OPEN_REQ = 0x3,
	CPL_SET_TCB = 0x4,
	CPL_SET_TCB_FIELD = 0x5,
	CPL_GET_TCB = 0x6,
	CPL_PCMD = 0x7,
	CPL_CLOSE_CON_REQ = 0x8,
	CPL_CLOSE_LISTSRV_REQ = 0x9,
	CPL_ABORT_REQ = 0xA,
	CPL_ABORT_RPL = 0xB,
	CPL_TX_DATA = 0xC,
	CPL_RX_DATA_ACK = 0xD,
	CPL_TX_PKT = 0xE,
	CPL_RTE_DELETE_REQ = 0xF,
	CPL_RTE_WRITE_REQ = 0x10,
	CPL_RTE_READ_REQ = 0x11,
	CPL_L2T_WRITE_REQ = 0x12,
	CPL_L2T_READ_REQ = 0x13,
	CPL_SMT_WRITE_REQ = 0x14,
	CPL_SMT_READ_REQ = 0x15,
	CPL_TX_PKT_LSO = 0x16,
	CPL_PCMD_READ = 0x17,
	CPL_BARRIER = 0x18,
	CPL_TID_RELEASE = 0x1A,

	CPL_CLOSE_LISTSRV_RPL = 0x20,
	CPL_ERROR = 0x21,
	CPL_GET_TCB_RPL = 0x22,
	CPL_L2T_WRITE_RPL = 0x23,
	CPL_PCMD_READ_RPL = 0x24,
	CPL_PCMD_RPL = 0x25,
	CPL_PEER_CLOSE = 0x26,
	CPL_RTE_DELETE_RPL = 0x27,
	CPL_RTE_WRITE_RPL = 0x28,
	CPL_RX_DDP_COMPLETE = 0x29,
	CPL_RX_PHYS_ADDR = 0x2A,
	CPL_RX_PKT = 0x2B,
	CPL_RX_URG_NOTIFY = 0x2C,
	CPL_SET_TCB_RPL = 0x2D,
	CPL_SMT_WRITE_RPL = 0x2E,
	CPL_TX_DATA_ACK = 0x2F,

	CPL_ABORT_REQ_RSS = 0x30,
	CPL_ABORT_RPL_RSS = 0x31,
	CPL_CLOSE_CON_RPL = 0x32,
	CPL_ISCSI_HDR = 0x33,
	CPL_L2T_READ_RPL = 0x34,
	CPL_RDMA_CQE = 0x35,
	CPL_RDMA_CQE_READ_RSP = 0x36,
	CPL_RDMA_CQE_ERR = 0x37,
	CPL_RTE_READ_RPL = 0x38,
	CPL_RX_DATA = 0x39,

	CPL_ACT_OPEN_RPL = 0x40,
	CPL_PASS_OPEN_RPL = 0x41,
	CPL_RX_DATA_DDP = 0x42,
	CPL_SMT_READ_RPL = 0x43,

	CPL_ACT_ESTABLISH = 0x50,
	CPL_PASS_ESTABLISH = 0x51,

	CPL_PASS_ACCEPT_REQ = 0x70,

	CPL_ASYNC_NOTIF = 0x80,	/* fake opcode for async notifications */

	CPL_TX_DMA_ACK = 0xA0,
	CPL_RDMA_READ_REQ = 0xA1,
	CPL_RDMA_TERMINATE = 0xA2,
	CPL_TRACE_PKT = 0xA3,
	CPL_RDMA_EC_STATUS = 0xA5,

	NUM_CPL_CMDS		/* must be last and previous entries must be sorted */
};

enum CPL_error {
	CPL_ERR_NONE = 0,
	CPL_ERR_TCAM_PARITY = 1,
	CPL_ERR_TCAM_FULL = 3,
	CPL_ERR_CONN_RESET = 20,
	CPL_ERR_CONN_EXIST = 22,
	CPL_ERR_ARP_MISS = 23,
	CPL_ERR_BAD_SYN = 24,
	CPL_ERR_CONN_TIMEDOUT = 30,
	CPL_ERR_XMIT_TIMEDOUT = 31,
	CPL_ERR_PERSIST_TIMEDOUT = 32,
	CPL_ERR_FINWAIT2_TIMEDOUT = 33,
	CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
	CPL_ERR_RTX_NEG_ADVICE = 35,
	CPL_ERR_PERSIST_NEG_ADVICE = 36,
	CPL_ERR_ABORT_FAILED = 42,
	CPL_ERR_GENERAL = 99
};

enum {
	CPL_CONN_POLICY_AUTO = 0,
	CPL_CONN_POLICY_ASK = 1,
	CPL_CONN_POLICY_DENY = 3
};

enum {
	ULP_MODE_NONE = 0,
	ULP_MODE_ISCSI = 2,
	ULP_MODE_RDMA = 4,
	ULP_MODE_TCPDDP = 5
};

enum {
	ULP_CRC_HEADER = 1 << 0,
	ULP_CRC_DATA = 1 << 1
};

enum {
	CPL_PASS_OPEN_ACCEPT,
	CPL_PASS_OPEN_REJECT
};

enum {
	CPL_ABORT_SEND_RST = 0,
	CPL_ABORT_NO_RST,
	CPL_ABORT_POST_CLOSE_REQ = 2
};

enum {				/* TX_PKT_LSO ethernet types */
	CPL_ETH_II,
	CPL_ETH_II_VLAN,
	CPL_ETH_802_3,
	CPL_ETH_802_3_VLAN
};

enum {				/* TCP congestion control algorithms */
	CONG_ALG_RENO,
	CONG_ALG_TAHOE,
	CONG_ALG_NEWRENO,
	CONG_ALG_HIGHSPEED
};

union opcode_tid {
	__be32 opcode_tid;
	__u8 opcode;
};

#define S_OPCODE 24
#define V_OPCODE(x) ((x) << S_OPCODE)
#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
#define G_TID(x)    ((x) & 0xFFFFFF)

/* tid is assumed to be 24-bits */
#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))

#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)

/* extract the TID from a CPL command */
#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))

struct tcp_options {
	__be16 mss;
	__u8 wsf;
#if defined(__LITTLE_ENDIAN_BITFIELD)
	 __u8:5;
	__u8 ecn:1;
	__u8 sack:1;
	__u8 tstamp:1;
#else
	__u8 tstamp:1;
	__u8 sack:1;
	__u8 ecn:1;
	 __u8:5;
#endif
};

struct rss_header {
	__u8 opcode;
#if defined(__LITTLE_ENDIAN_BITFIELD)
	__u8 cpu_idx:6;
	__u8 hash_type:2;
#else
	__u8 hash_type:2;
	__u8 cpu_idx:6;
#endif
	__be16 cq_idx;
	__be32 rss_hash_val;
};

#ifndef CHELSIO_FW
struct work_request_hdr {
	__be32 wr_hi;
	__be32 wr_lo;
};

/* wr_hi fields */
#define S_WR_SGE_CREDITS    0
#define M_WR_SGE_CREDITS    0xFF
#define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
#define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)

#define S_WR_SGLSFLT    8
#define M_WR_SGLSFLT    0xFF
#define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
#define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)

#define S_WR_BCNTLFLT    16
#define M_WR_BCNTLFLT    0xF
#define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
#define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)

#define S_WR_DATATYPE    20
#define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
#define F_WR_DATATYPE    V_WR_DATATYPE(1U)

#define S_WR_COMPL    21
#define V_WR_COMPL(x) ((x) << S_WR_COMPL)
#define F_WR_COMPL    V_WR_COMPL(1U)

#define S_WR_EOP    22
#define V_WR_EOP(x) ((x) << S_WR_EOP)
#define F_WR_EOP    V_WR_EOP(1U)

#define S_WR_SOP    23
#define V_WR_SOP(x) ((x) << S_WR_SOP)
#define F_WR_SOP    V_WR_SOP(1U)

#define S_WR_OP    24
#define M_WR_OP    0xFF
#define V_WR_OP(x) ((x) << S_WR_OP)
#define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)

/* wr_lo fields */
#define S_WR_LEN    0
#define M_WR_LEN    0xFF
#define V_WR_LEN(x) ((x) << S_WR_LEN)
#define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)

#define S_WR_TID    8
#define M_WR_TID    0xFFFFF
#define V_WR_TID(x) ((x) << S_WR_TID)
#define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)

#define S_WR_CR_FLUSH    30
#define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
#define F_WR_CR_FLUSH    V_WR_CR_FLUSH(1U)

#define S_WR_GEN    31
#define V_WR_GEN(x) ((x) << S_WR_GEN)
#define F_WR_GEN    V_WR_GEN(1U)

# define WR_HDR struct work_request_hdr wr
# define RSS_HDR
#else
# define WR_HDR
# define RSS_HDR struct rss_header rss_hdr;
#endif

/* option 0 lower-half fields */
#define S_CPL_STATUS    0
#define M_CPL_STATUS    0xFF
#define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
#define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)

#define S_INJECT_TIMER    6
#define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
#define F_INJECT_TIMER    V_INJECT_TIMER(1U)

#define S_NO_OFFLOAD    7
#define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
#define F_NO_OFFLOAD    V_NO_OFFLOAD(1U)

#define S_ULP_MODE    8
#define M_ULP_MODE    0xF
#define V_ULP_MODE(x) ((x) << S_ULP_MODE)
#define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)

#define S_RCV_BUFSIZ    12
#define M_RCV_BUFSIZ    0x3FFF
#define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
#define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)

#define S_TOS    26
#define M_TOS    0x3F
#define V_TOS(x) ((x) << S_TOS)
#define G_TOS(x) (((x) >> S_TOS) & M_TOS)

/* option 0 upper-half fields */
#define S_DELACK    0
#define V_DELACK(x) ((x) << S_DELACK)
#define F_DELACK    V_DELACK(1U)

#define S_NO_CONG    1
#define V_NO_CONG(x) ((x) << S_NO_CONG)
#define F_NO_CONG    V_NO_CONG(1U)

#define S_SRC_MAC_SEL    2
#define M_SRC_MAC_SEL    0x3
#define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
#define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)

#define S_L2T_IDX    4
#define M_L2T_IDX    0x7FF
#define V_L2T_IDX(x) ((x) << S_L2T_IDX)
#define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)

#define S_TX_CHANNEL    15
#define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
#define F_TX_CHANNEL    V_TX_CHANNEL(1U)

#define S_TCAM_BYPASS    16
#define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
#define F_TCAM_BYPASS    V_TCAM_BYPASS(1U)

#define S_NAGLE    17
#define V_NAGLE(x) ((x) << S_NAGLE)
#define F_NAGLE    V_NAGLE(1U)

#define S_WND_SCALE    18
#define M_WND_SCALE    0xF
#define V_WND_SCALE(x) ((x) << S_WND_SCALE)
#define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)

#define S_KEEP_ALIVE    22
#define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
#define F_KEEP_ALIVE    V_KEEP_ALIVE(1U)

#define S_MAX_RETRANS    23
#define M_MAX_RETRANS    0xF
#define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
#define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)

#define S_MAX_RETRANS_OVERRIDE    27
#define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
#define F_MAX_RETRANS_OVERRIDE    V_MAX_RETRANS_OVERRIDE(1U)

#define S_MSS_IDX    28
#define M_MSS_IDX    0xF
#define V_MSS_IDX(x) ((x) << S_MSS_IDX)
#define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)

/* option 1 fields */
#define S_RSS_ENABLE    0
#define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
#define F_RSS_ENABLE    V_RSS_ENABLE(1U)

#define S_RSS_MASK_LEN    1
#define M_RSS_MASK_LEN    0x7
#define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
#define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)

#define S_CPU_IDX    4
#define M_CPU_IDX    0x3F
#define V_CPU_IDX(x) ((x) << S_CPU_IDX)
#define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)

#define S_MAC_MATCH_VALID    18
#define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
#define F_MAC_MATCH_VALID    V_MAC_MATCH_VALID(1U)

#define S_CONN_POLICY    19
#define M_CONN_POLICY    0x3
#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)

#define S_SYN_DEFENSE    21
#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
#define F_SYN_DEFENSE    V_SYN_DEFENSE(1U)

#define S_VLAN_PRI    22
#define M_VLAN_PRI    0x3
#define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
#define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)

#define S_VLAN_PRI_VALID    24
#define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
#define F_VLAN_PRI_VALID    V_VLAN_PRI_VALID(1U)

#define S_PKT_TYPE    25
#define M_PKT_TYPE    0x3
#define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
#define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)

#define S_MAC_MATCH    27
#define M_MAC_MATCH    0x1F
#define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
#define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)

/* option 2 fields */
#define S_CPU_INDEX    0
#define M_CPU_INDEX    0x7F
#define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
#define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)

#define S_CPU_INDEX_VALID    7
#define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
#define F_CPU_INDEX_VALID    V_CPU_INDEX_VALID(1U)

#define S_RX_COALESCE    8
#define M_RX_COALESCE    0x3
#define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
#define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)

#define S_RX_COALESCE_VALID    10
#define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
#define F_RX_COALESCE_VALID    V_RX_COALESCE_VALID(1U)

#define S_CONG_CONTROL_FLAVOR    11
#define M_CONG_CONTROL_FLAVOR    0x3
#define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
#define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)

#define S_PACING_FLAVOR    13
#define M_PACING_FLAVOR    0x3
#define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
#define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)

#define S_FLAVORS_VALID    15
#define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
#define F_FLAVORS_VALID    V_FLAVORS_VALID(1U)

#define S_RX_FC_DISABLE    16
#define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
#define F_RX_FC_DISABLE    V_RX_FC_DISABLE(1U)

#define S_RX_FC_VALID    17
#define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
#define F_RX_FC_VALID    V_RX_FC_VALID(1U)

struct cpl_pass_open_req {
	WR_HDR;
	union opcode_tid ot;
	__be16 local_port;
	__be16 peer_port;
	__be32 local_ip;
	__be32 peer_ip;
	__be32 opt0h;
	__be32 opt0l;
	__be32 peer_netmask;
	__be32 opt1;
};

struct cpl_pass_open_rpl {
	RSS_HDR union opcode_tid ot;
	__be16 local_port;
	__be16 peer_port;
	__be32 local_ip;
	__be32 peer_ip;