atl1_hw.h

linux 内核源代码

#define MII_AT001_PSSR_1000MBS				0x8000	/* 10=1000Mbs */

/* PCI Command Register Bit Definitions */
#define PCI_REG_COMMAND					0x04	/* PCI Command Register */
#define CMD_IO_SPACE					0x0001
#define CMD_MEMORY_SPACE				0x0002
#define CMD_BUS_MASTER					0x0004

/* Wake Up Filter Control */
#define ATL1_WUFC_LNKC	0x00000001	/* Link Status Change Wakeup Enable */
#define ATL1_WUFC_MAG	0x00000002	/* Magic Packet Wakeup Enable */
#define ATL1_WUFC_EX	0x00000004	/* Directed Exact Wakeup Enable */
#define ATL1_WUFC_MC	0x00000008	/* Multicast Wakeup Enable */
#define ATL1_WUFC_BC	0x00000010	/* Broadcast Wakeup Enable */

/* Error Codes */
#define ATL1_SUCCESS			0
#define ATL1_ERR_EEPROM			1
#define ATL1_ERR_PHY			2
#define ATL1_ERR_CONFIG			3
#define ATL1_ERR_PARAM			4
#define ATL1_ERR_MAC_TYPE		5
#define ATL1_ERR_PHY_TYPE		6
#define ATL1_ERR_PHY_SPEED		7
#define ATL1_ERR_PHY_RES		8

#define SPEED_0		0xffff
#define SPEED_10	10
#define SPEED_100	100
#define SPEED_1000	1000
#define HALF_DUPLEX	1
#define FULL_DUPLEX	2

#define MEDIA_TYPE_AUTO_SENSOR	0
#define MEDIA_TYPE_1000M_FULL	1
#define MEDIA_TYPE_100M_FULL	2
#define MEDIA_TYPE_100M_HALF	3
#define MEDIA_TYPE_10M_FULL	4
#define MEDIA_TYPE_10M_HALF	5

#define ADVERTISE_10_HALF		0x0001
#define ADVERTISE_10_FULL		0x0002
#define ADVERTISE_100_HALF		0x0004
#define ADVERTISE_100_FULL		0x0008
#define ADVERTISE_1000_HALF		0x0010
#define ADVERTISE_1000_FULL		0x0020
#define AUTONEG_ADVERTISE_SPEED_DEFAULT	0x002F	/* Everything but 1000-Half */
#define AUTONEG_ADVERTISE_10_100_ALL	0x000F	/* All 10/100 speeds */
#define AUTONEG_ADVERTISE_10_ALL	0x0003	/* 10Mbps Full & Half speeds */

#define MAX_JUMBO_FRAME_SIZE		0x2800

#define PHY_AUTO_NEG_TIME	45	/* 4.5 Seconds */
#define PHY_FORCE_TIME		20	/* 2.0 Seconds */

/* For checksumming , the sum of all words in the EEPROM should equal 0xBABA */
#define EEPROM_SUM		0xBABA

#define ATL1_EEDUMP_LEN		48

/* Statistics counters collected by the MAC */
struct stats_msg_block {
	/* rx */
	u32 rx_ok;		/* The number of good packet received. */
	u32 rx_bcast;		/* The number of good broadcast packet received. */
	u32 rx_mcast;		/* The number of good multicast packet received. */
	u32 rx_pause;		/* The number of Pause packet received. */
	u32 rx_ctrl;		/* The number of Control packet received other than Pause frame. */
	u32 rx_fcs_err;		/* The number of packets with bad FCS. */
	u32 rx_len_err;		/* The number of packets with mismatch of length field and actual size. */
	u32 rx_byte_cnt;	/* The number of bytes of good packet received. FCS is NOT included. */
	u32 rx_runt;		/* The number of packets received that are less than 64 byte long and with good FCS. */
	u32 rx_frag;		/* The number of packets received that are less than 64 byte long and with bad FCS. */
	u32 rx_sz_64;		/* The number of good and bad packets received that are 64 byte long. */
	u32 rx_sz_65_127;	/* The number of good and bad packets received that are between 65 and 127-byte long. */
	u32 rx_sz_128_255;	/* The number of good and bad packets received that are between 128 and 255-byte long. */
	u32 rx_sz_256_511;	/* The number of good and bad packets received that are between 256 and 511-byte long. */
	u32 rx_sz_512_1023;	/* The number of good and bad packets received that are between 512 and 1023-byte long. */
	u32 rx_sz_1024_1518;	/* The number of good and bad packets received that are between 1024 and 1518-byte long. */
	u32 rx_sz_1519_max;	/* The number of good and bad packets received that are between 1519-byte and MTU. */
	u32 rx_sz_ov;		/* The number of good and bad packets received that are more than MTU size šC truncated by Selene. */
	u32 rx_rxf_ov;		/* The number of frame dropped due to occurrence of RX FIFO overflow. */
	u32 rx_rrd_ov;		/* The number of frame dropped due to occurrence of RRD overflow. */
	u32 rx_align_err;	/* Alignment Error */
	u32 rx_bcast_byte_cnt;	/* The byte count of broadcast packet received, excluding FCS. */
	u32 rx_mcast_byte_cnt;	/* The byte count of multicast packet received, excluding FCS. */
	u32 rx_err_addr;	/* The number of packets dropped due to address filtering. */

	/* tx */
	u32 tx_ok;		/* The number of good packet transmitted. */
	u32 tx_bcast;		/* The number of good broadcast packet transmitted. */
	u32 tx_mcast;		/* The number of good multicast packet transmitted. */
	u32 tx_pause;		/* The number of Pause packet transmitted. */
	u32 tx_exc_defer;	/* The number of packets transmitted with excessive deferral. */
	u32 tx_ctrl;		/* The number of packets transmitted is a control frame, excluding Pause frame. */
	u32 tx_defer;		/* The number of packets transmitted that is deferred. */
	u32 tx_byte_cnt;	/* The number of bytes of data transmitted. FCS is NOT included. */
	u32 tx_sz_64;		/* The number of good and bad packets transmitted that are 64 byte long. */
	u32 tx_sz_65_127;	/* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
	u32 tx_sz_128_255;	/* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
	u32 tx_sz_256_511;	/* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
	u32 tx_sz_512_1023;	/* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
	u32 tx_sz_1024_1518;	/* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
	u32 tx_sz_1519_max;	/* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
	u32 tx_1_col;		/* The number of packets subsequently transmitted successfully with a single prior collision. */
	u32 tx_2_col;		/* The number of packets subsequently transmitted successfully with multiple prior collisions. */
	u32 tx_late_col;	/* The number of packets transmitted with late collisions. */
	u32 tx_abort_col;	/* The number of transmit packets aborted due to excessive collisions. */
	u32 tx_underrun;	/* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
	u32 tx_rd_eop;		/* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
	u32 tx_len_err;		/* The number of transmit packets with length field does NOT match the actual frame size. */
	u32 tx_trunc;		/* The number of transmit packets truncated due to size exceeding MTU. */
	u32 tx_bcast_byte;	/* The byte count of broadcast packet transmitted, excluding FCS. */
	u32 tx_mcast_byte;	/* The byte count of multicast packet transmitted, excluding FCS. */
	u32 smb_updated;	/* 1: SMB Updated. This is used by software as the indication of the statistics update.
				 * Software should clear this bit as soon as retrieving the statistics information. */
};

/* Coalescing Message Block */
struct coals_msg_block {
	u32 int_stats;		/* interrupt status */
	u16 rrd_prod_idx;	/* TRD Producer Index. */
	u16 rfd_cons_idx;	/* RFD Consumer Index. */
	u16 update;		/* Selene sets this bit every time it DMA the CMB to host memory.
				 * Software supposes to clear this bit when CMB information is processed. */
	u16 tpd_cons_idx;	/* TPD Consumer Index. */
};

/* RRD descriptor */
struct rx_return_desc {
	u8 num_buf;		/* Number of RFD buffers used by the received packet */
	u8 resved;
	u16 buf_indx;		/* RFD Index of the first buffer */
	union {
		u32 valid;
		struct {
			u16 rx_chksum;
			u16 pkt_size;
		} xsum_sz;
	} xsz;

	u16 pkt_flg;		/* Packet flags */
	u16 err_flg;		/* Error flags */
	u16 resved2;
	u16 vlan_tag;		/* VLAN TAG */
};

#define PACKET_FLAG_ETH_TYPE	0x0080
#define PACKET_FLAG_VLAN_INS	0x0100
#define PACKET_FLAG_ERR		0x0200
#define PACKET_FLAG_IPV4	0x0400
#define PACKET_FLAG_UDP		0x0800
#define PACKET_FLAG_TCP		0x1000
#define PACKET_FLAG_BCAST	0x2000
#define PACKET_FLAG_MCAST	0x4000
#define PACKET_FLAG_PAUSE	0x8000

#define ERR_FLAG_CRC		0x0001
#define ERR_FLAG_CODE		0x0002
#define ERR_FLAG_DRIBBLE	0x0004
#define ERR_FLAG_RUNT		0x0008
#define ERR_FLAG_OV		0x0010
#define ERR_FLAG_TRUNC		0x0020
#define ERR_FLAG_IP_CHKSUM	0x0040
#define ERR_FLAG_L4_CHKSUM	0x0080
#define ERR_FLAG_LEN		0x0100
#define ERR_FLAG_DES_ADDR	0x0200

/* RFD descriptor */
struct rx_free_desc {
	__le64 buffer_addr;	/* Address of the descriptor's data buffer */
	__le16 buf_len;		/* Size of the receive buffer in host memory, in byte */
	u16 coalese;		/* Update consumer index to host after the reception of this frame */
	/* __attribute__ ((packed)) is required */
} __attribute__ ((packed));

/* tsopu defines */
#define TSO_PARAM_BUFLEN_MASK           0x3FFF
#define TSO_PARAM_BUFLEN_SHIFT          0
#define TSO_PARAM_DMAINT_MASK           0x0001
#define TSO_PARAM_DMAINT_SHIFT          14
#define TSO_PARAM_PKTNT_MASK            0x0001
#define TSO_PARAM_PKTINT_SHIFT          15
#define TSO_PARAM_VLANTAG_MASK          0xFFFF
#define TSO_PARAM_VLAN_SHIFT            16

/* tsopl defines */
#define TSO_PARAM_EOP_MASK              0x0001
#define TSO_PARAM_EOP_SHIFT             0
#define TSO_PARAM_COALESCE_MASK         0x0001
#define TSO_PARAM_COALESCE_SHIFT        1
#define TSO_PARAM_INSVLAG_MASK          0x0001
#define TSO_PARAM_INSVLAG_SHIFT         2
#define TSO_PARAM_CUSTOMCKSUM_MASK      0x0001
#define TSO_PARAM_CUSTOMCKSUM_SHIFT     3
#define TSO_PARAM_SEGMENT_MASK          0x0001
#define TSO_PARAM_SEGMENT_SHIFT         4
#define TSO_PARAM_IPCKSUM_MASK          0x0001
#define TSO_PARAM_IPCKSUM_SHIFT         5
#define TSO_PARAM_TCPCKSUM_MASK         0x0001
#define TSO_PARAM_TCPCKSUM_SHIFT        6
#define TSO_PARAM_UDPCKSUM_MASK         0x0001
#define TSO_PARAM_UDPCKSUM_SHIFT        7
#define TSO_PARAM_VLANTAGGED_MASK       0x0001
#define TSO_PARAM_VLANTAGGED_SHIFT      8
#define TSO_PARAM_ETHTYPE_MASK          0x0001
#define TSO_PARAM_ETHTYPE_SHIFT         9
#define TSO_PARAM_IPHL_MASK             0x000F
#define TSO_PARAM_IPHL_SHIFT            10
#define TSO_PARAM_TCPHDRLEN_MASK        0x000F
#define TSO_PARAM_TCPHDRLEN_SHIFT       14
#define TSO_PARAM_HDRFLAG_MASK          0x0001
#define TSO_PARAM_HDRFLAG_SHIFT         18
#define TSO_PARAM_MSS_MASK              0x1FFF
#define TSO_PARAM_MSS_SHIFT             19

/* csumpu defines */
#define CSUM_PARAM_BUFLEN_MASK          0x3FFF
#define CSUM_PARAM_BUFLEN_SHIFT         0
#define CSUM_PARAM_DMAINT_MASK          0x0001
#define CSUM_PARAM_DMAINT_SHIFT         14
#define CSUM_PARAM_PKTINT_MASK          0x0001
#define CSUM_PARAM_PKTINT_SHIFT         15
#define CSUM_PARAM_VALANTAG_MASK        0xFFFF
#define CSUM_PARAM_VALAN_SHIFT          16

/* csumpl defines*/
#define CSUM_PARAM_EOP_MASK             0x0001
#define CSUM_PARAM_EOP_SHIFT            0
#define CSUM_PARAM_COALESCE_MASK        0x0001
#define CSUM_PARAM_COALESCE_SHIFT       1
#define CSUM_PARAM_INSVLAG_MASK         0x0001
#define CSUM_PARAM_INSVLAG_SHIFT        2
#define CSUM_PARAM_CUSTOMCKSUM_MASK     0x0001
#define CSUM_PARAM_CUSTOMCKSUM_SHIFT    3
#define CSUM_PARAM_SEGMENT_MASK         0x0001
#define CSUM_PARAM_SEGMENT_SHIFT        4
#define CSUM_PARAM_IPCKSUM_MASK         0x0001
#define CSUM_PARAM_IPCKSUM_SHIFT        5
#define CSUM_PARAM_TCPCKSUM_MASK        0x0001
#define CSUM_PARAM_TCPCKSUM_SHIFT       6
#define CSUM_PARAM_UDPCKSUM_MASK        0x0001
#define CSUM_PARAM_UDPCKSUM_SHIFT       7
#define CSUM_PARAM_VLANTAGGED_MASK      0x0001
#define CSUM_PARAM_VLANTAGGED_SHIFT     8
#define CSUM_PARAM_ETHTYPE_MASK         0x0001
#define CSUM_PARAM_ETHTYPE_SHIFT        9
#define CSUM_PARAM_IPHL_MASK            0x000F
#define CSUM_PARAM_IPHL_SHIFT           10
#define CSUM_PARAM_PLOADOFFSET_MASK     0x00FF
#define CSUM_PARAM_PLOADOFFSET_SHIFT    16
#define CSUM_PARAM_XSUMOFFSET_MASK      0x00FF
#define CSUM_PARAM_XSUMOFFSET_SHIFT     24

/* TPD descriptor */
struct tso_param {
        /* The order of these declarations is important -- don't change it */
        u32 tsopu;      /* tso_param upper word */
        u32 tsopl;      /* tso_param lower word */
};

struct csum_param {
        /* The order of these declarations is important -- don't change it */
        u32 csumpu;     /* csum_param upper word */
        u32 csumpl;     /* csum_param lower word */
};

union tpd_descr {
	u64 data;
	struct csum_param csum;
	struct tso_param tso;
};

struct tx_packet_desc {
	__le64 buffer_addr;
	union tpd_descr desc;
};

/* DMA Order Settings */
enum atl1_dma_order {
	atl1_dma_ord_in = 1,
	atl1_dma_ord_enh = 2,
	atl1_dma_ord_out = 4
};

enum atl1_dma_rcb {
	atl1_rcb_64 = 0,
	atl1_rcb_128 = 1
};

enum atl1_dma_req_block {
	atl1_dma_req_128 = 0,
	atl1_dma_req_256 = 1,
	atl1_dma_req_512 = 2,
	atl1_dma_req_1024 = 3,
	atl1_dma_req_2048 = 4,
	atl1_dma_req_4096 = 5
};

struct atl1_spi_flash_dev {
	const char *manu_name;	/* manufacturer id */
	/* op-code */
	u8 cmd_wrsr;
	u8 cmd_read;
	u8 cmd_program;
	u8 cmd_wren;
	u8 cmd_wrdi;
	u8 cmd_rdsr;
	u8 cmd_rdid;
	u8 cmd_sector_erase;
	u8 cmd_chip_erase;
};

#endif	/* _ATL1_HW_H_ */