atl1_hw.h

linux 内核源代码

#define SRAM_TCPH_ADDR_SHIFT			0
#define SRAM_PATH_ADDR_MASK			0x0fff
#define SRAM_PATH_ADDR_SHIFT			16

/* Load Ptr Register */
#define REG_LOAD_PTR				(REG_SRAM_RFD_ADDR+52)

/* Descriptor Control register */
#define REG_DESC_BASE_ADDR_HI			0x1540
#define REG_DESC_RFD_ADDR_LO			(REG_DESC_BASE_ADDR_HI+4)
#define REG_DESC_RRD_ADDR_LO			(REG_DESC_BASE_ADDR_HI+8)
#define REG_DESC_TPD_ADDR_LO			(REG_DESC_BASE_ADDR_HI+12)
#define REG_DESC_CMB_ADDR_LO			(REG_DESC_BASE_ADDR_HI+16)
#define REG_DESC_SMB_ADDR_LO			(REG_DESC_BASE_ADDR_HI+20)
#define REG_DESC_RFD_RRD_RING_SIZE		(REG_DESC_BASE_ADDR_HI+24)
#define DESC_RFD_RING_SIZE_MASK			0x7ff
#define DESC_RFD_RING_SIZE_SHIFT		0
#define DESC_RRD_RING_SIZE_MASK			0x7ff
#define DESC_RRD_RING_SIZE_SHIFT		16
#define REG_DESC_TPD_RING_SIZE			(REG_DESC_BASE_ADDR_HI+28)
#define DESC_TPD_RING_SIZE_MASK			0x3ff
#define DESC_TPD_RING_SIZE_SHIFT		0

/* TXQ Control Register */
#define REG_TXQ_CTRL				0x1580
#define TXQ_CTRL_TPD_BURST_NUM_SHIFT		0
#define TXQ_CTRL_TPD_BURST_NUM_MASK		0x1f
#define TXQ_CTRL_EN				0x20
#define TXQ_CTRL_ENH_MODE			0x40
#define TXQ_CTRL_TPD_FETCH_TH_SHIFT		8
#define TXQ_CTRL_TPD_FETCH_TH_MASK		0x3f
#define TXQ_CTRL_TXF_BURST_NUM_SHIFT		16
#define TXQ_CTRL_TXF_BURST_NUM_MASK		0xffff

/* Jumbo packet Threshold for task offload */
#define REG_TX_JUMBO_TASK_TH_TPD_IPG		0x1584
#define TX_JUMBO_TASK_TH_MASK			0x7ff
#define TX_JUMBO_TASK_TH_SHIFT			0
#define TX_TPD_MIN_IPG_MASK			0x1f
#define TX_TPD_MIN_IPG_SHIFT			16

/* RXQ Control Register */
#define REG_RXQ_CTRL				0x15a0
#define RXQ_CTRL_RFD_BURST_NUM_SHIFT		0
#define RXQ_CTRL_RFD_BURST_NUM_MASK		0xff
#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT		8
#define RXQ_CTRL_RRD_BURST_THRESH_MASK		0xff
#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT		16
#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK		0x1f
#define RXQ_CTRL_CUT_THRU_EN			0x40000000
#define RXQ_CTRL_EN				0x80000000

/* Rx jumbo packet threshold and rrd  retirement timer */
#define REG_RXQ_JMBOSZ_RRDTIM			(REG_RXQ_CTRL+ 4)
#define RXQ_JMBOSZ_TH_MASK			0x7ff
#define RXQ_JMBOSZ_TH_SHIFT			0
#define RXQ_JMBO_LKAH_MASK			0xf
#define RXQ_JMBO_LKAH_SHIFT			11
#define RXQ_RRD_TIMER_MASK			0xffff
#define RXQ_RRD_TIMER_SHIFT			16

/* RFD flow control register */
#define REG_RXQ_RXF_PAUSE_THRESH		(REG_RXQ_CTRL+ 8)
#define RXQ_RXF_PAUSE_TH_HI_SHIFT		16
#define RXQ_RXF_PAUSE_TH_HI_MASK		0xfff
#define RXQ_RXF_PAUSE_TH_LO_SHIFT		0
#define RXQ_RXF_PAUSE_TH_LO_MASK		0xfff

/* RRD flow control register */
#define REG_RXQ_RRD_PAUSE_THRESH		(REG_RXQ_CTRL+12)
#define RXQ_RRD_PAUSE_TH_HI_SHIFT		0
#define RXQ_RRD_PAUSE_TH_HI_MASK		0xfff
#define RXQ_RRD_PAUSE_TH_LO_SHIFT		16
#define RXQ_RRD_PAUSE_TH_LO_MASK		0xfff

/* DMA Engine Control Register */
#define REG_DMA_CTRL				0x15c0
#define DMA_CTRL_DMAR_IN_ORDER			0x1
#define DMA_CTRL_DMAR_ENH_ORDER			0x2
#define DMA_CTRL_DMAR_OUT_ORDER			0x4
#define DMA_CTRL_RCB_VALUE			0x8
#define DMA_CTRL_DMAR_BURST_LEN_SHIFT		4
#define DMA_CTRL_DMAR_BURST_LEN_MASK		7
#define DMA_CTRL_DMAW_BURST_LEN_SHIFT		7
#define DMA_CTRL_DMAW_BURST_LEN_MASK		7
#define DMA_CTRL_DMAR_EN				0x400
#define DMA_CTRL_DMAW_EN				0x800

/* CMB/SMB Control Register */
#define REG_CSMB_CTRL				0x15d0
#define CSMB_CTRL_CMB_NOW			1
#define CSMB_CTRL_SMB_NOW			2
#define CSMB_CTRL_CMB_EN			4
#define CSMB_CTRL_SMB_EN			8

/* CMB DMA Write Threshold Register */
#define REG_CMB_WRITE_TH			(REG_CSMB_CTRL+ 4)
#define CMB_RRD_TH_SHIFT			0
#define CMB_RRD_TH_MASK				0x7ff
#define CMB_TPD_TH_SHIFT			16
#define CMB_TPD_TH_MASK				0x7ff

/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
#define REG_CMB_WRITE_TIMER			(REG_CSMB_CTRL+ 8)
#define CMB_RX_TM_SHIFT				0
#define CMB_RX_TM_MASK				0xffff
#define CMB_TX_TM_SHIFT				16
#define CMB_TX_TM_MASK				0xffff

/* Number of packet received since last CMB write */
#define REG_CMB_RX_PKT_CNT			(REG_CSMB_CTRL+12)

/* Number of packet transmitted since last CMB write */
#define REG_CMB_TX_PKT_CNT			(REG_CSMB_CTRL+16)

/* SMB auto DMA timer register */
#define REG_SMB_TIMER				(REG_CSMB_CTRL+20)

/* Mailbox Register */
#define REG_MAILBOX				0x15f0
#define MB_RFD_PROD_INDX_SHIFT			0
#define MB_RFD_PROD_INDX_MASK			0x7ff
#define MB_RRD_CONS_INDX_SHIFT			11
#define MB_RRD_CONS_INDX_MASK			0x7ff
#define MB_TPD_PROD_INDX_SHIFT			22
#define MB_TPD_PROD_INDX_MASK			0x3ff

/* Interrupt Status Register */
#define REG_ISR					0x1600
#define ISR_SMB					1
#define ISR_TIMER				2
#define ISR_MANUAL				4
#define ISR_RXF_OV				8
#define ISR_RFD_UNRUN				0x10
#define ISR_RRD_OV				0x20
#define ISR_TXF_UNRUN				0x40
#define ISR_LINK				0x80
#define ISR_HOST_RFD_UNRUN			0x100
#define ISR_HOST_RRD_OV				0x200
#define ISR_DMAR_TO_RST				0x400
#define ISR_DMAW_TO_RST				0x800
#define ISR_GPHY				0x1000
#define ISR_RX_PKT				0x10000
#define ISR_TX_PKT				0x20000
#define ISR_TX_DMA				0x40000
#define ISR_RX_DMA				0x80000
#define ISR_CMB_RX				0x100000
#define ISR_CMB_TX				0x200000
#define ISR_MAC_RX				0x400000
#define ISR_MAC_TX				0x800000
#define ISR_UR_DETECTED				0x1000000
#define ISR_FERR_DETECTED			0x2000000
#define ISR_NFERR_DETECTED			0x4000000
#define ISR_CERR_DETECTED			0x8000000
#define ISR_PHY_LINKDOWN			0x10000000
#define ISR_DIS_SMB				0x20000000
#define ISR_DIS_DMA				0x40000000
#define ISR_DIS_INT				0x80000000

/* Interrupt Mask Register */
#define REG_IMR					0x1604

/* Normal Interrupt mask  */
#define IMR_NORMAL_MASK	(\
	ISR_SMB		|\
	ISR_GPHY	|\
	ISR_PHY_LINKDOWN|\
	ISR_DMAR_TO_RST	|\
	ISR_DMAW_TO_RST	|\
	ISR_CMB_TX	|\
	ISR_CMB_RX	)

/* Debug Interrupt Mask  (enable all interrupt) */
#define IMR_DEBUG_MASK	(\
	ISR_SMB		|\
	ISR_TIMER	|\
	ISR_MANUAL	|\
	ISR_RXF_OV	|\
	ISR_RFD_UNRUN	|\
	ISR_RRD_OV	|\
	ISR_TXF_UNRUN	|\
	ISR_LINK	|\
	ISR_CMB_TX	|\
	ISR_CMB_RX	|\
	ISR_RX_PKT	|\
	ISR_TX_PKT	|\
	ISR_MAC_RX	|\
	ISR_MAC_TX	)

/* Interrupt Status Register */
#define REG_RFD_RRD_IDX				0x1800
#define REG_TPD_IDX				0x1804

/*  MII definition */
/* PHY Common Register */
#define MII_AT001_CR					0x09
#define MII_AT001_SR					0x0A
#define MII_AT001_ESR					0x0F
#define MII_AT001_PSCR					0x10
#define MII_AT001_PSSR					0x11

/* PHY Control Register */
#define MII_CR_SPEED_SELECT_MSB				0x0040	/* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_COLL_TEST_ENABLE				0x0080	/* Collision test enable */
#define MII_CR_FULL_DUPLEX				0x0100	/* FDX =1, half duplex =0 */
#define MII_CR_RESTART_AUTO_NEG				0x0200	/* Restart auto negotiation */
#define MII_CR_ISOLATE					0x0400	/* Isolate PHY from MII */
#define MII_CR_POWER_DOWN				0x0800	/* Power down */
#define MII_CR_AUTO_NEG_EN				0x1000	/* Auto Neg Enable */
#define MII_CR_SPEED_SELECT_LSB				0x2000	/* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_LOOPBACK					0x4000	/* 0 = normal, 1 = loopback */
#define MII_CR_RESET					0x8000	/* 0 = normal, 1 = PHY reset */
#define MII_CR_SPEED_MASK				0x2040
#define MII_CR_SPEED_1000				0x0040
#define MII_CR_SPEED_100				0x2000
#define MII_CR_SPEED_10					0x0000

/* PHY Status Register */
#define MII_SR_EXTENDED_CAPS				0x0001	/* Extended register capabilities */
#define MII_SR_JABBER_DETECT				0x0002	/* Jabber Detected */
#define MII_SR_LINK_STATUS				0x0004	/* Link Status 1 = link */
#define MII_SR_AUTONEG_CAPS				0x0008	/* Auto Neg Capable */
#define MII_SR_REMOTE_FAULT				0x0010	/* Remote Fault Detect */
#define MII_SR_AUTONEG_COMPLETE				0x0020	/* Auto Neg Complete */
#define MII_SR_PREAMBLE_SUPPRESS			0x0040	/* Preamble may be suppressed */
#define MII_SR_EXTENDED_STATUS				0x0100	/* Ext. status info in Reg 0x0F */
#define MII_SR_100T2_HD_CAPS				0x0200	/* 100T2 Half Duplex Capable */
#define MII_SR_100T2_FD_CAPS				0x0400	/* 100T2 Full Duplex Capable */
#define MII_SR_10T_HD_CAPS				0x0800	/* 10T   Half Duplex Capable */
#define MII_SR_10T_FD_CAPS				0x1000	/* 10T   Full Duplex Capable */
#define MII_SR_100X_HD_CAPS				0x2000	/* 100X  Half Duplex Capable */
#define MII_SR_100X_FD_CAPS				0x4000	/* 100X  Full Duplex Capable */
#define MII_SR_100T4_CAPS				0x8000	/* 100T4 Capable */

/* Link partner ability register. */
#define MII_LPA_SLCT					0x001f	/* Same as advertise selector  */
#define MII_LPA_10HALF					0x0020	/* Can do 10mbps half-duplex   */
#define MII_LPA_10FULL					0x0040	/* Can do 10mbps full-duplex   */
#define MII_LPA_100HALF					0x0080	/* Can do 100mbps half-duplex  */
#define MII_LPA_100FULL					0x0100	/* Can do 100mbps full-duplex  */
#define MII_LPA_100BASE4				0x0200	/* 100BASE-T4  */
#define MII_LPA_PAUSE					0x0400	/* PAUSE */
#define MII_LPA_ASYPAUSE				0x0800	/* Asymmetrical PAUSE */
#define MII_LPA_RFAULT					0x2000	/* Link partner faulted        */
#define MII_LPA_LPACK					0x4000	/* Link partner acked us       */
#define MII_LPA_NPAGE					0x8000	/* Next page bit               */

/* Autoneg Advertisement Register */
#define MII_AR_SELECTOR_FIELD				0x0001	/* indicates IEEE 802.3 CSMA/CD */
#define MII_AR_10T_HD_CAPS				0x0020	/* 10T   Half Duplex Capable */
#define MII_AR_10T_FD_CAPS				0x0040	/* 10T   Full Duplex Capable */
#define MII_AR_100TX_HD_CAPS				0x0080	/* 100TX Half Duplex Capable */
#define MII_AR_100TX_FD_CAPS				0x0100	/* 100TX Full Duplex Capable */
#define MII_AR_100T4_CAPS				0x0200	/* 100T4 Capable */
#define MII_AR_PAUSE					0x0400	/* Pause operation desired */
#define MII_AR_ASM_DIR					0x0800	/* Asymmetric Pause Direction bit */
#define MII_AR_REMOTE_FAULT				0x2000	/* Remote Fault detected */
#define MII_AR_NEXT_PAGE				0x8000	/* Next Page ability supported */
#define MII_AR_SPEED_MASK				0x01E0
#define MII_AR_DEFAULT_CAP_MASK				0x0DE0

/* 1000BASE-T Control Register */
#define MII_AT001_CR_1000T_HD_CAPS			0x0100	/* Advertise 1000T HD capability */
#define MII_AT001_CR_1000T_FD_CAPS			0x0200	/* Advertise 1000T FD capability  */
#define MII_AT001_CR_1000T_REPEATER_DTE			0x0400	/* 1=Repeater/switch device port, 0=DTE device */
#define MII_AT001_CR_1000T_MS_VALUE			0x0800	/* 1=Configure PHY as Master, 0=Configure PHY as Slave */
#define MII_AT001_CR_1000T_MS_ENABLE			0x1000	/* 1=Master/Slave manual config value, 0=Automatic Master/Slave config */
#define MII_AT001_CR_1000T_TEST_MODE_NORMAL		0x0000	/* Normal Operation */
#define MII_AT001_CR_1000T_TEST_MODE_1			0x2000	/* Transmit Waveform test */
#define MII_AT001_CR_1000T_TEST_MODE_2			0x4000	/* Master Transmit Jitter test */
#define MII_AT001_CR_1000T_TEST_MODE_3			0x6000	/* Slave Transmit Jitter test */
#define MII_AT001_CR_1000T_TEST_MODE_4			0x8000	/* Transmitter Distortion test */
#define MII_AT001_CR_1000T_SPEED_MASK			0x0300
#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK		0x0300

/* 1000BASE-T Status Register */
#define MII_AT001_SR_1000T_LP_HD_CAPS			0x0400	/* LP is 1000T HD capable */
#define MII_AT001_SR_1000T_LP_FD_CAPS			0x0800	/* LP is 1000T FD capable */
#define MII_AT001_SR_1000T_REMOTE_RX_STATUS		0x1000	/* Remote receiver OK */
#define MII_AT001_SR_1000T_LOCAL_RX_STATUS		0x2000	/* Local receiver OK */
#define MII_AT001_SR_1000T_MS_CONFIG_RES		0x4000	/* 1=Local TX is Master, 0=Slave */
#define MII_AT001_SR_1000T_MS_CONFIG_FAULT		0x8000	/* Master/Slave config fault */
#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT	12
#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT	13

/* Extended Status Register */
#define MII_AT001_ESR_1000T_HD_CAPS			0x1000	/* 1000T HD capable */
#define MII_AT001_ESR_1000T_FD_CAPS			0x2000	/* 1000T FD capable */
#define MII_AT001_ESR_1000X_HD_CAPS			0x4000	/* 1000X HD capable */
#define MII_AT001_ESR_1000X_FD_CAPS			0x8000	/* 1000X FD capable */

/* AT001 PHY Specific Control Register */
#define MII_AT001_PSCR_JABBER_DISABLE			0x0001	/* 1=Jabber Function disabled */
#define MII_AT001_PSCR_POLARITY_REVERSAL		0x0002	/* 1=Polarity Reversal enabled */
#define MII_AT001_PSCR_SQE_TEST				0x0004	/* 1=SQE Test enabled */
#define MII_AT001_PSCR_MAC_POWERDOWN			0x0008
#define MII_AT001_PSCR_CLK125_DISABLE			0x0010	/* 1=CLK125 low, 0=CLK125 toggling */
#define MII_AT001_PSCR_MDI_MANUAL_MODE			0x0000	/* MDI Crossover Mode bits 6:5, Manual MDI configuration */
#define MII_AT001_PSCR_MDIX_MANUAL_MODE			0x0020	/* Manual MDIX configuration */
#define MII_AT001_PSCR_AUTO_X_1000T			0x0040	/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
#define MII_AT001_PSCR_AUTO_X_MODE			0x0060	/* Auto crossover enabled all speeds. */
#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE		0x0080	/* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold), 0=Normal 10BASE-T RX Threshold */
#define MII_AT001_PSCR_MII_5BIT_ENABLE			0x0100	/* 1=5-Bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
#define MII_AT001_PSCR_SCRAMBLER_DISABLE		0x0200	/* 1=Scrambler disable */
#define MII_AT001_PSCR_FORCE_LINK_GOOD			0x0400	/* 1=Force link good */
#define MII_AT001_PSCR_ASSERT_CRS_ON_TX			0x0800	/* 1=Assert CRS on Transmit */
#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT		1
#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT		5
#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT	7

/* AT001 PHY Specific Status Register */
#define MII_AT001_PSSR_SPD_DPLX_RESOLVED		0x0800	/* 1=Speed & Duplex resolved */
#define MII_AT001_PSSR_DPLX				0x2000	/* 1=Duplex 0=Half Duplex */
#define MII_AT001_PSSR_SPEED				0xC000	/* Speed, bits 14:15 */
#define MII_AT001_PSSR_10MBS				0x0000	/* 00=10Mbs */
#define MII_AT001_PSSR_100MBS				0x4000	/* 01=100Mbs */