s2io.h

linux 内核源代码

	/* Save virtual address of TxD page with zero DMA addr(if any) */
	void *zerodma_virt_addr;

/* rx side stuff */
	/* Ring specific structure */
	struct ring_info rings[MAX_RX_RINGS];

	u16 rmac_pause_time;
	u16 mc_pause_threshold_q0q3;
	u16 mc_pause_threshold_q4q7;

	void *stats_mem;	/* orignal pointer to allocated mem */
	dma_addr_t stats_mem_phy;	/* Physical address of the stat block */
	u32 stats_mem_sz;
	struct stat_block *stats_info;	/* Logical address of the stat block */
};

/* structure representing the user defined MAC addresses */
struct usr_addr {
	char addr[ETH_ALEN];
	int usage_cnt;
};

/* Default Tunable parameters of the NIC. */
#define DEFAULT_FIFO_0_LEN 4096
#define DEFAULT_FIFO_1_7_LEN 512
#define SMALL_BLK_CNT	30
#define LARGE_BLK_CNT	100

/*
 * Structure to keep track of the MSI-X vectors and the corresponding
 * argument registered against each vector
 */
#define MAX_REQUESTED_MSI_X	17
struct s2io_msix_entry
{
	u16 vector;
	u16 entry;
	void *arg;

	u8 type;
#define	MSIX_FIFO_TYPE	1
#define	MSIX_RING_TYPE	2

	u8 in_use;
#define MSIX_REGISTERED_SUCCESS	0xAA
};

struct msix_info_st {
	u64 addr;
	u64 data;
};

/* Data structure to represent a LRO session */
struct lro {
	struct sk_buff	*parent;
	struct sk_buff  *last_frag;
	u8		*l2h;
	struct iphdr	*iph;
	struct tcphdr	*tcph;
	u32		tcp_next_seq;
	__be32		tcp_ack;
	int		total_len;
	int		frags_len;
	int		sg_num;
	int		in_use;
	__be16		window;
	u32		cur_tsval;
	u32		cur_tsecr;
	u8		saw_ts;
};

/* These flags represent the devices temporary state */
enum s2io_device_state_t
{
	__S2IO_STATE_LINK_TASK=0,
	__S2IO_STATE_CARD_UP
};

/* Structure representing one instance of the NIC */
struct s2io_nic {
	int rxd_mode;
	/*
	 * Count of packets to be processed in a given iteration, it will be indicated
	 * by the quota field of the device structure when NAPI is enabled.
	 */
	int pkts_to_process;
	struct net_device *dev;
	struct napi_struct napi;
	struct mac_info mac_control;
	struct config_param config;
	struct pci_dev *pdev;
	void __iomem *bar0;
	void __iomem *bar1;
#define MAX_MAC_SUPPORTED   16
#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED

	struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED];

	struct net_device_stats stats;
	int high_dma_flag;
	int device_enabled_once;

	char name[60];
	struct tasklet_struct task;
	volatile unsigned long tasklet_status;

	/* Timer that handles I/O errors/exceptions */
	struct timer_list alarm_timer;

	/* Space to back up the PCI config space */
	u32 config_space[256 / sizeof(u32)];

	atomic_t rx_bufs_left[MAX_RX_RINGS];

	spinlock_t tx_lock;
	spinlock_t put_lock;

#define PROMISC     1
#define ALL_MULTI   2

#define MAX_ADDRS_SUPPORTED 64
	u16 usr_addr_count;
	u16 mc_addr_count;
	struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED];

	u16 m_cast_flg;
	u16 all_multi_pos;
	u16 promisc_flg;

	/*  Id timer, used to blink NIC to physically identify NIC. */
	struct timer_list id_timer;

	/*  Restart timer, used to restart NIC if the device is stuck and
	 *  a schedule task that will set the correct Link state once the
	 *  NIC's PHY has stabilized after a state change.
	 */
	struct work_struct rst_timer_task;
	struct work_struct set_link_task;

	/* Flag that can be used to turn on or turn off the Rx checksum
	 * offload feature.
	 */
	int rx_csum;

	/*  after blink, the adapter must be restored with original
	 *  values.
	 */
	u64 adapt_ctrl_org;

	/* Last known link state. */
	u16 last_link_state;
#define	LINK_DOWN	1
#define	LINK_UP		2

	int task_flag;
	unsigned long long start_time;
	struct vlan_group *vlgrp;
#define MSIX_FLG                0xA5
	struct msix_entry *entries;
	int msi_detected;
	wait_queue_head_t msi_wait;
	struct s2io_msix_entry *s2io_entries;
	char desc[MAX_REQUESTED_MSI_X][25];

	int avail_msix_vectors; /* No. of MSI-X vectors granted by system */

	struct msix_info_st msix_info[0x3f];

#define XFRAME_I_DEVICE		1
#define XFRAME_II_DEVICE	2
	u8 device_type;

#define MAX_LRO_SESSIONS	32
	struct lro lro0_n[MAX_LRO_SESSIONS];
	unsigned long	clubbed_frms_cnt;
	unsigned long	sending_both;
	u8		lro;
	u16		lro_max_aggr_per_sess;
	volatile unsigned long state;
	spinlock_t	rx_lock;
	u64		general_int_mask;
	u64 *ufo_in_band_v;
#define VPD_STRING_LEN 80
	u8  product_name[VPD_STRING_LEN];
	u8  serial_num[VPD_STRING_LEN];
};

#define RESET_ERROR 1;
#define CMD_ERROR   2;

/*  OS related system calls */
#ifndef readq
static inline u64 readq(void __iomem *addr)
{
	u64 ret = 0;
	ret = readl(addr + 4);
	ret <<= 32;
	ret |= readl(addr);

	return ret;
}
#endif

#ifndef writeq
static inline void writeq(u64 val, void __iomem *addr)
{
	writel((u32) (val), addr);
	writel((u32) (val >> 32), (addr + 4));
}
#endif

/*
 * Some registers have to be written in a particular order to
 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
 * is used to perform such ordered writes. Defines UF (Upper First)
 * and LF (Lower First) will be used to specify the required write order.
 */
#define UF	1
#define LF	2
static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
{
	u32 ret;

	if (order == LF) {
		writel((u32) (val), addr);
		ret = readl(addr);
		writel((u32) (val >> 32), (addr + 4));
		ret = readl(addr + 4);
	} else {
		writel((u32) (val >> 32), (addr + 4));
		ret = readl(addr + 4);
		writel((u32) (val), addr);
		ret = readl(addr);
	}
}

/*  Interrupt related values of Xena */

#define ENABLE_INTRS    1
#define DISABLE_INTRS   2

/*  Highest level interrupt blocks */
#define TX_PIC_INTR     (0x0001<<0)
#define TX_DMA_INTR     (0x0001<<1)
#define TX_MAC_INTR     (0x0001<<2)
#define TX_XGXS_INTR    (0x0001<<3)
#define TX_TRAFFIC_INTR (0x0001<<4)
#define RX_PIC_INTR     (0x0001<<5)
#define RX_DMA_INTR     (0x0001<<6)
#define RX_MAC_INTR     (0x0001<<7)
#define RX_XGXS_INTR    (0x0001<<8)
#define RX_TRAFFIC_INTR (0x0001<<9)
#define MC_INTR         (0x0001<<10)
#define ENA_ALL_INTRS    (   TX_PIC_INTR     | \
                            TX_DMA_INTR     | \
                            TX_MAC_INTR     | \
                            TX_XGXS_INTR    | \
                            TX_TRAFFIC_INTR | \
                            RX_PIC_INTR     | \
                            RX_DMA_INTR     | \
                            RX_MAC_INTR     | \
                            RX_XGXS_INTR    | \
                            RX_TRAFFIC_INTR | \
                            MC_INTR )

/*  Interrupt masks for the general interrupt mask register */
#define DISABLE_ALL_INTRS   0xFFFFFFFFFFFFFFFFULL

#define TXPIC_INT_M         s2BIT(0)
#define TXDMA_INT_M         s2BIT(1)
#define TXMAC_INT_M         s2BIT(2)
#define TXXGXS_INT_M        s2BIT(3)
#define TXTRAFFIC_INT_M     s2BIT(8)
#define PIC_RX_INT_M        s2BIT(32)
#define RXDMA_INT_M         s2BIT(33)
#define RXMAC_INT_M         s2BIT(34)
#define MC_INT_M            s2BIT(35)
#define RXXGXS_INT_M        s2BIT(36)
#define RXTRAFFIC_INT_M     s2BIT(40)

/*  PIC level Interrupts TODO*/

/*  DMA level Inressupts */
#define TXDMA_PFC_INT_M     s2BIT(0)
#define TXDMA_PCC_INT_M     s2BIT(2)

/*  PFC block interrupts */
#define PFC_MISC_ERR_1      s2BIT(0)	/* Interrupt to indicate FIFO full */

/* PCC block interrupts. */
#define	PCC_FB_ECC_ERR	   vBIT(0xff, 16, 8)	/* Interrupt to indicate
						   PCC_FB_ECC Error. */

#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
/*
 * Prototype declaration.
 */
static int __devinit s2io_init_nic(struct pci_dev *pdev,
				   const struct pci_device_id *pre);
static void __devexit s2io_rem_nic(struct pci_dev *pdev);
static int init_shared_mem(struct s2io_nic *sp);
static void free_shared_mem(struct s2io_nic *sp);
static int init_nic(struct s2io_nic *nic);
static void rx_intr_handler(struct ring_info *ring_data);
static void tx_intr_handler(struct fifo_info *fifo_data);
static void s2io_handle_errors(void * dev_id);

static int s2io_starter(void);
static void s2io_closer(void);
static void s2io_tx_watchdog(struct net_device *dev);
static void s2io_tasklet(unsigned long dev_addr);
static void s2io_set_multicast(struct net_device *dev);
static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
static void s2io_link(struct s2io_nic * sp, int link);
static void s2io_reset(struct s2io_nic * sp);
static int s2io_poll(struct napi_struct *napi, int budget);
static void s2io_init_pci(struct s2io_nic * sp);
static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
static void s2io_alarm_handle(unsigned long data);
static irqreturn_t
s2io_msix_ring_handle(int irq, void *dev_id);
static irqreturn_t
s2io_msix_fifo_handle(int irq, void *dev_id);
static irqreturn_t s2io_isr(int irq, void *dev_id);
static int verify_xena_quiescence(struct s2io_nic *sp);
static const struct ethtool_ops netdev_ethtool_ops;
static void s2io_set_link(struct work_struct *work);
static int s2io_set_swapper(struct s2io_nic * sp);
static void s2io_card_down(struct s2io_nic *nic);
static int s2io_card_up(struct s2io_nic *nic);
static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
					int bit_state);
static int s2io_add_isr(struct s2io_nic * sp);
static void s2io_rem_isr(struct s2io_nic * sp);

static void restore_xmsi_data(struct s2io_nic *nic);

static int
s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
		      struct RxD_t *rxdp, struct s2io_nic *sp);
static void clear_lro_session(struct lro *lro);
static void queue_rx_frame(struct sk_buff *skb);
static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
			   struct sk_buff *skb, u32 tcp_len);
static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);

static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
			                      pci_channel_state_t state);
static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
static void s2io_io_resume(struct pci_dev *pdev);

#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type

#define S2IO_PARM_INT(X, def_val) \
	static unsigned int X = def_val;\
		module_param(X , uint, 0);

#endif				/* _S2IO_H */