sunqe.c

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	return IRQ_HANDLED;
}

static int qe_open(struct net_device *dev)
{
	struct sunqe *qep = (struct sunqe *) dev->priv;

	qep->mconfig = (MREGS_MCONFIG_TXENAB |
			MREGS_MCONFIG_RXENAB |
			MREGS_MCONFIG_MBAENAB);
	return qe_init(qep, 0);
}

static int qe_close(struct net_device *dev)
{
	struct sunqe *qep = (struct sunqe *) dev->priv;

	qe_stop(qep);
	return 0;
}

/* Reclaim TX'd frames from the ring.  This must always run under
 * the IRQ protected qep->lock.
 */
static void qe_tx_reclaim(struct sunqe *qep)
{
	struct qe_txd *txbase = &qep->qe_block->qe_txd[0];
	int elem = qep->tx_old;

	while (elem != qep->tx_new) {
		u32 flags = txbase[elem].tx_flags;

		if (flags & TXD_OWN)
			break;
		elem = NEXT_TX(elem);
	}
	qep->tx_old = elem;
}

static void qe_tx_timeout(struct net_device *dev)
{
	struct sunqe *qep = (struct sunqe *) dev->priv;
	int tx_full;

	spin_lock_irq(&qep->lock);

	/* Try to reclaim, if that frees up some tx
	 * entries, we're fine.
	 */
	qe_tx_reclaim(qep);
	tx_full = TX_BUFFS_AVAIL(qep) <= 0;

	spin_unlock_irq(&qep->lock);

	if (! tx_full)
		goto out;

	printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
	qe_init(qep, 1);

out:
	netif_wake_queue(dev);
}

/* Get a packet queued to go onto the wire. */
static int qe_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct sunqe *qep = (struct sunqe *) dev->priv;
	struct sunqe_buffers *qbufs = qep->buffers;
	__u32 txbuf_dvma, qbufs_dvma = qep->buffers_dvma;
	unsigned char *txbuf;
	int len, entry;

	spin_lock_irq(&qep->lock);

	qe_tx_reclaim(qep);

	len = skb->len;
	entry = qep->tx_new;

	txbuf = &qbufs->tx_buf[entry & (TX_RING_SIZE - 1)][0];
	txbuf_dvma = qbufs_dvma +
		qebuf_offset(tx_buf, (entry & (TX_RING_SIZE - 1)));

	/* Avoid a race... */
	qep->qe_block->qe_txd[entry].tx_flags = TXD_UPDATE;

	skb_copy_from_linear_data(skb, txbuf, len);

	qep->qe_block->qe_txd[entry].tx_addr = txbuf_dvma;
	qep->qe_block->qe_txd[entry].tx_flags =
		(TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
	qep->tx_new = NEXT_TX(entry);

	/* Get it going. */
	dev->trans_start = jiffies;
	sbus_writel(CREG_CTRL_TWAKEUP, qep->qcregs + CREG_CTRL);

	dev->stats.tx_packets++;
	dev->stats.tx_bytes += len;

	if (TX_BUFFS_AVAIL(qep) <= 0) {
		/* Halt the net queue and enable tx interrupts.
		 * When the tx queue empties the tx irq handler
		 * will wake up the queue and return us back to
		 * the lazy tx reclaim scheme.
		 */
		netif_stop_queue(dev);
		sbus_writel(0, qep->qcregs + CREG_TIMASK);
	}
	spin_unlock_irq(&qep->lock);

	dev_kfree_skb(skb);

	return 0;
}

static void qe_set_multicast(struct net_device *dev)
{
	struct sunqe *qep = (struct sunqe *) dev->priv;
	struct dev_mc_list *dmi = dev->mc_list;
	u8 new_mconfig = qep->mconfig;
	char *addrs;
	int i;
	u32 crc;

	/* Lock out others. */
	netif_stop_queue(dev);

	if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
		sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
			    qep->mregs + MREGS_IACONFIG);
		while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
			barrier();
		for (i = 0; i < 8; i++)
			sbus_writeb(0xff, qep->mregs + MREGS_FILTER);
		sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
	} else if (dev->flags & IFF_PROMISC) {
		new_mconfig |= MREGS_MCONFIG_PROMISC;
	} else {
		u16 hash_table[4];
		u8 *hbytes = (unsigned char *) &hash_table[0];

		for (i = 0; i < 4; i++)
			hash_table[i] = 0;

		for (i = 0; i < dev->mc_count; i++) {
			addrs = dmi->dmi_addr;
			dmi = dmi->next;

			if (!(*addrs & 1))
				continue;
			crc = ether_crc_le(6, addrs);
			crc >>= 26;
			hash_table[crc >> 4] |= 1 << (crc & 0xf);
		}
		/* Program the qe with the new filter value. */
		sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
			    qep->mregs + MREGS_IACONFIG);
		while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
			barrier();
		for (i = 0; i < 8; i++) {
			u8 tmp = *hbytes++;
			sbus_writeb(tmp, qep->mregs + MREGS_FILTER);
		}
		sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
	}

	/* Any change of the logical address filter, the physical address,
	 * or enabling/disabling promiscuous mode causes the MACE to disable
	 * the receiver.  So we must re-enable them here or else the MACE
	 * refuses to listen to anything on the network.  Sheesh, took
	 * me a day or two to find this bug.
	 */
	qep->mconfig = new_mconfig;
	sbus_writeb(qep->mconfig, qep->mregs + MREGS_MCONFIG);

	/* Let us get going again. */
	netif_wake_queue(dev);
}

/* Ethtool support... */
static void qe_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
	struct sunqe *qep = dev->priv;

	strcpy(info->driver, "sunqe");
	strcpy(info->version, "3.0");
	sprintf(info->bus_info, "SBUS:%d",
		qep->qe_sdev->slot);
}

static u32 qe_get_link(struct net_device *dev)
{
	struct sunqe *qep = dev->priv;
	void __iomem *mregs = qep->mregs;
	u8 phyconfig;

	spin_lock_irq(&qep->lock);
	phyconfig = sbus_readb(mregs + MREGS_PHYCONFIG);
	spin_unlock_irq(&qep->lock);

	return (phyconfig & MREGS_PHYCONFIG_LSTAT);
}

static const struct ethtool_ops qe_ethtool_ops = {
	.get_drvinfo		= qe_get_drvinfo,
	.get_link		= qe_get_link,
};

/* This is only called once at boot time for each card probed. */
static inline void qec_init_once(struct sunqec *qecp, struct sbus_dev *qsdev)
{
	u8 bsizes = qecp->qec_bursts;

	if (sbus_can_burst64(qsdev) && (bsizes & DMA_BURST64)) {
		sbus_writel(GLOB_CTRL_B64, qecp->gregs + GLOB_CTRL);
	} else if (bsizes & DMA_BURST32) {
		sbus_writel(GLOB_CTRL_B32, qecp->gregs + GLOB_CTRL);
	} else {
		sbus_writel(GLOB_CTRL_B16, qecp->gregs + GLOB_CTRL);
	}

	/* Packetsize only used in 100baseT BigMAC configurations,
	 * set it to zero just to be on the safe side.
	 */
	sbus_writel(GLOB_PSIZE_2048, qecp->gregs + GLOB_PSIZE);

	/* Set the local memsize register, divided up to one piece per QE channel. */
	sbus_writel((qsdev->reg_addrs[1].reg_size >> 2),
		    qecp->gregs + GLOB_MSIZE);

	/* Divide up the local QEC memory amongst the 4 QE receiver and
	 * transmitter FIFOs.  Basically it is (total / 2 / num_channels).
	 */
	sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1,
		    qecp->gregs + GLOB_TSIZE);
	sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1,
		    qecp->gregs + GLOB_RSIZE);
}

static u8 __init qec_get_burst(struct device_node *dp)
{
	u8 bsizes, bsizes_more;

	/* Find and set the burst sizes for the QEC, since it
	 * does the actual dma for all 4 channels.
	 */
	bsizes = of_getintprop_default(dp, "burst-sizes", 0xff);
	bsizes &= 0xff;
	bsizes_more = of_getintprop_default(dp->parent, "burst-sizes", 0xff);

	if (bsizes_more != 0xff)
		bsizes &= bsizes_more;
	if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
	    (bsizes & DMA_BURST32)==0)
		bsizes = (DMA_BURST32 - 1);

	return bsizes;
}

static struct sunqec * __init get_qec(struct sbus_dev *child_sdev)
{
	struct sbus_dev *qec_sdev = child_sdev->parent;
	struct sunqec *qecp;

	for (qecp = root_qec_dev; qecp; qecp = qecp->next_module) {
		if (qecp->qec_sdev == qec_sdev)
			break;
	}
	if (!qecp) {
		qecp = kzalloc(sizeof(struct sunqec), GFP_KERNEL);
		if (qecp) {
			u32 ctrl;

			qecp->qec_sdev = qec_sdev;
			qecp->gregs = sbus_ioremap(&qec_sdev->resource[0], 0,
						   GLOB_REG_SIZE,
						   "QEC Global Registers");
			if (!qecp->gregs)
				goto fail;

			/* Make sure the QEC is in MACE mode. */
			ctrl = sbus_readl(qecp->gregs + GLOB_CTRL);
			ctrl &= 0xf0000000;
			if (ctrl != GLOB_CTRL_MMODE) {
				printk(KERN_ERR "qec: Not in MACE mode!\n");
				goto fail;
			}

			if (qec_global_reset(qecp->gregs))
				goto fail;

			qecp->qec_bursts = qec_get_burst(qec_sdev->ofdev.node);

			qec_init_once(qecp, qec_sdev);

			if (request_irq(qec_sdev->irqs[0], &qec_interrupt,
					IRQF_SHARED, "qec", (void *) qecp)) {
				printk(KERN_ERR "qec: Can't register irq.\n");
				goto fail;
			}

			qecp->next_module = root_qec_dev;
			root_qec_dev = qecp;
		}
	}

	return qecp;

fail:
	if (qecp->gregs)
		sbus_iounmap(qecp->gregs, GLOB_REG_SIZE);
	kfree(qecp);
	return NULL;
}

static int __init qec_ether_init(struct sbus_dev *sdev)
{
	static unsigned version_printed;
	struct net_device *dev;
	struct sunqe *qe;
	struct sunqec *qecp;
	int i, res;

	if (version_printed++ == 0)
		printk(KERN_INFO "%s", version);

	dev = alloc_etherdev(sizeof(struct sunqe));
	if (!dev)
		return -ENOMEM;

	memcpy(dev->dev_addr, idprom->id_ethaddr, 6);

	qe = netdev_priv(dev);

	i = of_getintprop_default(sdev->ofdev.node, "channel#", -1);
	if (i == -1) {
		struct sbus_dev *td = sdev->parent->child;
		i = 0;
		while (td != sdev) {
			td = td->next;
			i++;
		}
	}
	qe->channel = i;
	spin_lock_init(&qe->lock);

	res = -ENODEV;
	qecp = get_qec(sdev);
	if (!qecp)
		goto fail;

	qecp->qes[qe->channel] = qe;
	qe->dev = dev;
	qe->parent = qecp;
	qe->qe_sdev = sdev;

	res = -ENOMEM;
	qe->qcregs = sbus_ioremap(&qe->qe_sdev->resource[0], 0,
				  CREG_REG_SIZE, "QEC Channel Registers");
	if (!qe->qcregs) {
		printk(KERN_ERR "qe: Cannot map channel registers.\n");
		goto fail;
	}

	qe->mregs = sbus_ioremap(&qe->qe_sdev->resource[1], 0,
				 MREGS_REG_SIZE, "QE MACE Registers");
	if (!qe->mregs) {
		printk(KERN_ERR "qe: Cannot map MACE registers.\n");
		goto fail;
	}

	qe->qe_block = sbus_alloc_consistent(qe->qe_sdev,
					     PAGE_SIZE,
					     &qe->qblock_dvma);
	qe->buffers = sbus_alloc_consistent(qe->qe_sdev,
					    sizeof(struct sunqe_buffers),
					    &qe->buffers_dvma);
	if (qe->qe_block == NULL || qe->qblock_dvma == 0 ||
	    qe->buffers == NULL || qe->buffers_dvma == 0)
		goto fail;

	/* Stop this QE. */
	qe_stop(qe);

	SET_NETDEV_DEV(dev, &sdev->ofdev.dev);

	dev->open = qe_open;
	dev->stop = qe_close;
	dev->hard_start_xmit = qe_start_xmit;
	dev->set_multicast_list = qe_set_multicast;
	dev->tx_timeout = qe_tx_timeout;
	dev->watchdog_timeo = 5*HZ;
	dev->irq = sdev->irqs[0];
	dev->dma = 0;
	dev->ethtool_ops = &qe_ethtool_ops;

	res = register_netdev(dev);
	if (res)
		goto fail;

	dev_set_drvdata(&sdev->ofdev.dev, qe);

	printk(KERN_INFO "%s: qe channel[%d] ", dev->name, qe->channel);
	for (i = 0; i < 6; i++)
		printk ("%2.2x%c",
			dev->dev_addr[i],
			i == 5 ? ' ': ':');
	printk("\n");


	return 0;

fail:
	if (qe->qcregs)
		sbus_iounmap(qe->qcregs, CREG_REG_SIZE);
	if (qe->mregs)
		sbus_iounmap(qe->mregs, MREGS_REG_SIZE);
	if (qe->qe_block)
		sbus_free_consistent(qe->qe_sdev,
				     PAGE_SIZE,
				     qe->qe_block,
				     qe->qblock_dvma);
	if (qe->buffers)
		sbus_free_consistent(qe->qe_sdev,
				     sizeof(struct sunqe_buffers),
				     qe->buffers,
				     qe->buffers_dvma);

	free_netdev(dev);

	return res;
}

static int __devinit qec_sbus_probe(struct of_device *dev, const struct of_device_id *match)
{
	struct sbus_dev *sdev = to_sbus_device(&dev->dev);

	return qec_ether_init(sdev);
}

static int __devexit qec_sbus_remove(struct of_device *dev)
{
	struct sunqe *qp = dev_get_drvdata(&dev->dev);
	struct net_device *net_dev = qp->dev;

	unregister_netdev(net_dev);

	sbus_iounmap(qp->qcregs, CREG_REG_SIZE);
	sbus_iounmap(qp->mregs, MREGS_REG_SIZE);
	sbus_free_consistent(qp->qe_sdev,
			     PAGE_SIZE,
			     qp->qe_block,
			     qp->qblock_dvma);
	sbus_free_consistent(qp->qe_sdev,
			     sizeof(struct sunqe_buffers),
			     qp->buffers,
			     qp->buffers_dvma);

	free_netdev(net_dev);

	dev_set_drvdata(&dev->dev, NULL);

	return 0;
}

static struct of_device_id qec_sbus_match[] = {
	{
		.name = "qe",
	},
	{},
};

MODULE_DEVICE_TABLE(of, qec_sbus_match);

static struct of_platform_driver qec_sbus_driver = {
	.name		= "qec",
	.match_table	= qec_sbus_match,
	.probe		= qec_sbus_probe,
	.remove		= __devexit_p(qec_sbus_remove),
};

static int __init qec_init(void)
{
	return of_register_driver(&qec_sbus_driver, &sbus_bus_type);
}

static void __exit qec_exit(void)
{
	of_unregister_driver(&qec_sbus_driver);

	while (root_qec_dev) {
		struct sunqec *next = root_qec_dev->next_module;

		free_irq(root_qec_dev->qec_sdev->irqs[0],
			 (void *) root_qec_dev);
		sbus_iounmap(root_qec_dev->gregs, GLOB_REG_SIZE);

		kfree(root_qec_dev);

		root_qec_dev = next;
	}
}

module_init(qec_init);
module_exit(qec_exit);