bnx2.h

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#define BNX2_L2CTX_TYPE					0x00000000
#define BNX2_L2CTX_TYPE_SIZE_L2				 ((0xc0/0x20)<<16)
#define BNX2_L2CTX_TYPE_TYPE				 (0xf<<28)
#define BNX2_L2CTX_TYPE_TYPE_EMPTY			 (0<<28)
#define BNX2_L2CTX_TYPE_TYPE_L2				 (1<<28)

#define BNX2_L2CTX_TX_HOST_BIDX				0x00000088
#define BNX2_L2CTX_EST_NBD				0x00000088
#define BNX2_L2CTX_CMD_TYPE				0x00000088
#define BNX2_L2CTX_CMD_TYPE_TYPE			 (0xf<<24)
#define BNX2_L2CTX_CMD_TYPE_TYPE_L2			 (0<<24)
#define BNX2_L2CTX_CMD_TYPE_TYPE_TCP			 (1<<24)

#define BNX2_L2CTX_TX_HOST_BSEQ				0x00000090
#define BNX2_L2CTX_TSCH_BSEQ				0x00000094
#define BNX2_L2CTX_TBDR_BSEQ				0x00000098
#define BNX2_L2CTX_TBDR_BOFF				0x0000009c
#define BNX2_L2CTX_TBDR_BIDX				0x0000009c
#define BNX2_L2CTX_TBDR_BHADDR_HI			0x000000a0
#define BNX2_L2CTX_TBDR_BHADDR_LO			0x000000a4
#define BNX2_L2CTX_TXP_BOFF				0x000000a8
#define BNX2_L2CTX_TXP_BIDX				0x000000a8
#define BNX2_L2CTX_TXP_BSEQ				0x000000ac

#define BNX2_L2CTX_TYPE_XI				0x00000080
#define BNX2_L2CTX_CMD_TYPE_XI				0x00000240
#define BNX2_L2CTX_TBDR_BHADDR_HI_XI			0x00000258
#define BNX2_L2CTX_TBDR_BHADDR_LO_XI			0x0000025c

/*
 *  l2_bd_chain_context definition
 */
#define BNX2_L2CTX_BD_PRE_READ				0x00000000
#define BNX2_L2CTX_CTX_SIZE				0x00000000
#define BNX2_L2CTX_CTX_TYPE				0x00000000
#define BNX2_L2CTX_CTX_TYPE_SIZE_L2			 ((0x20/20)<<16)
#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE		 (0xf<<28)
#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED	 (0<<28)
#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE	 (1<<28)

#define BNX2_L2CTX_HOST_BDIDX				0x00000004
#define BNX2_L2CTX_HOST_BSEQ				0x00000008
#define BNX2_L2CTX_NX_BSEQ				0x0000000c
#define BNX2_L2CTX_NX_BDHADDR_HI			0x00000010
#define BNX2_L2CTX_NX_BDHADDR_LO			0x00000014
#define BNX2_L2CTX_NX_BDIDX				0x00000018


/*
 *  pci_config_l definition
 *  offset: 0000
 */
#define BNX2_PCICFG_MISC_CONFIG				0x00000068
#define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP	 (1L<<2)
#define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP	 (1L<<3)
#define BNX2_PCICFG_MISC_CONFIG_RESERVED1		 (1L<<4)
#define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA		 (1L<<5)
#define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP	 (1L<<6)
#define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA		 (1L<<7)
#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ		 (1L<<8)
#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY		 (1L<<9)
#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN	 (1L<<10)
#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN	 (1L<<11)
#define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN	 (1L<<12)
#define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV		 (0xffL<<16)
#define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV		 (0xfL<<24)
#define BNX2_PCICFG_MISC_CONFIG_ASIC_ID			 (0xfL<<28)

#define BNX2_PCICFG_MISC_STATUS				0x0000006c
#define BNX2_PCICFG_MISC_STATUS_INTA_VALUE		 (1L<<0)
#define BNX2_PCICFG_MISC_STATUS_32BIT_DET		 (1L<<1)
#define BNX2_PCICFG_MISC_STATUS_M66EN			 (1L<<2)
#define BNX2_PCICFG_MISC_STATUS_PCIX_DET		 (1L<<3)
#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED		 (0x3L<<4)
#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66		 (0L<<4)
#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100		 (1L<<4)
#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133		 (2L<<4)
#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE	 (3L<<4)
#define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE	 (1L<<8)

#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS		0x00000070
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET	 (0xfL<<0)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW	 (0xfL<<0)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE	 (1L<<6)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT	 (1L<<7)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC	 (0x7L<<8)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12	 (1L<<8)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6	 (2L<<8)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62	 (4L<<8)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER	 (1L<<11)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED	 (0xfL<<12)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80	 (1L<<12)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50	 (2L<<12)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40	 (4L<<12)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25	 (8L<<12)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP	 (1L<<16)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17	 (1L<<17)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18	 (1L<<18)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19	 (1L<<19)
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED	 (0xfffL<<20)

#define BNX2_PCICFG_REG_WINDOW_ADDRESS			0x00000078
#define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL		 (0xfffffL<<2)

#define BNX2_PCICFG_REG_WINDOW				0x00000080
#define BNX2_PCICFG_INT_ACK_CMD				0x00000084
#define BNX2_PCICFG_INT_ACK_CMD_INDEX			 (0xffffL<<0)
#define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID		 (1L<<16)
#define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM	 (1L<<17)
#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT		 (1L<<18)
#define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM		 (0xfL<<24)

#define BNX2_PCICFG_STATUS_BIT_SET_CMD			0x00000088
#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD		0x0000008c
#define BNX2_PCICFG_MAILBOX_QUEUE_ADDR			0x00000090
#define BNX2_PCICFG_MAILBOX_QUEUE_DATA			0x00000094


/*
 *  pci_reg definition
 *  offset: 0x400
 */
#define BNX2_PCI_GRC_WINDOW_ADDR			0x00000400
#define BNX2_PCI_GRC_WINDOW_ADDR_VALUE			 (0x1ffL<<13)
#define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN		 (1L<<31)

#define BNX2_PCI_CONFIG_1				0x00000404
#define BNX2_PCI_CONFIG_1_RESERVED0			 (0xffL<<0)
#define BNX2_PCI_CONFIG_1_READ_BOUNDARY			 (0x7L<<8)
#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF		 (0L<<8)
#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16		 (1L<<8)
#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32		 (2L<<8)
#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64		 (3L<<8)
#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128		 (4L<<8)
#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256		 (5L<<8)
#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512		 (6L<<8)
#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024		 (7L<<8)
#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY		 (0x7L<<11)
#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF		 (0L<<11)
#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16		 (1L<<11)
#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32		 (2L<<11)
#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64		 (3L<<11)
#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128		 (4L<<11)
#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256		 (5L<<11)
#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512		 (6L<<11)
#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024		 (7L<<11)
#define BNX2_PCI_CONFIG_1_RESERVED1			 (0x3ffffL<<14)

#define BNX2_PCI_CONFIG_2				0x00000408
#define BNX2_PCI_CONFIG_2_BAR1_SIZE			 (0xfL<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED		 (0L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K			 (1L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K		 (2L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K		 (3L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K		 (4L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M			 (5L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M			 (6L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M			 (7L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M			 (8L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M			 (9L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M			 (10L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M			 (11L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M		 (12L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M		 (13L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M		 (14L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G			 (15L<<0)
#define BNX2_PCI_CONFIG_2_BAR1_64ENA			 (1L<<4)
#define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY			 (1L<<5)
#define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY		 (1L<<6)
#define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE		 (1L<<7)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE			 (0xffL<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED		 (0L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K		 (1L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K		 (2L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K		 (3L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K		 (4L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K		 (5L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K		 (6L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K		 (7L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K		 (8L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K		 (9L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K		 (10L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M		 (11L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M		 (12L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M		 (13L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M		 (14L<<8)
#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M		 (15L<<8)
#define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT		 (0x1fL<<16)
#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT		 (0x3L<<21)
#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512		 (0L<<21)
#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K		 (1L<<21)
#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K		 (2L<<21)
#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K		 (3L<<21)
#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR		 (1L<<23)
#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT		 (1L<<24)
#define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT		 (1L<<25)
#define BNX2_PCI_CONFIG_2_RESERVED0			 (0x3fL<<26)
#define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI		 (1L<<16)
#define BNX2_PCI_CONFIG_2_RESERVED0_XI			 (0x7fffL<<17)

#define BNX2_PCI_CONFIG_3				0x0000040c
#define BNX2_PCI_CONFIG_3_STICKY_BYTE			 (0xffL<<0)
#define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE		 (0xffL<<8)
#define BNX2_PCI_CONFIG_3_FORCE_PME			 (1L<<24)
#define BNX2_PCI_CONFIG_3_PME_STATUS			 (1L<<25)
#define BNX2_PCI_CONFIG_3_PME_ENABLE			 (1L<<26)
#define BNX2_PCI_CONFIG_3_PM_STATE			 (0x3L<<27)
#define BNX2_PCI_CONFIG_3_VAUX_PRESET			 (1L<<30)
#define BNX2_PCI_CONFIG_3_PCI_POWER			 (1L<<31)

#define BNX2_PCI_PM_DATA_A				0x00000410
#define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG		 (0xffL<<0)
#define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG		 (0xffL<<8)
#define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG		 (0xffL<<16)
#define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG		 (0xffL<<24)

#define BNX2_PCI_PM_DATA_B				0x00000414
#define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG		 (0xffL<<0)
#define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG		 (0xffL<<8)
#define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG		 (0xffL<<16)
#define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG		 (0xffL<<24)

#define BNX2_PCI_SWAP_DIAG0				0x00000418
#define BNX2_PCI_SWAP_DIAG1				0x0000041c
#define BNX2_PCI_EXP_ROM_ADDR				0x00000420
#define BNX2_PCI_EXP_ROM_ADDR_ADDRESS			 (0x3fffffL<<2)
#define BNX2_PCI_EXP_ROM_ADDR_REQ			 (1L<<31)

#define BNX2_PCI_EXP_ROM_DATA				0x00000424
#define BNX2_PCI_VPD_INTF				0x00000428
#define BNX2_PCI_VPD_INTF_INTF_REQ			 (1L<<0)

#define BNX2_PCI_VPD_ADDR_FLAG				0x0000042c
#define BNX2_PCI_VPD_ADDR_FLAG_MSK			0x0000ffff
#define BNX2_PCI_VPD_ADDR_FLAG_SL			0L
#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS			 (0x1fffL<<2)
#define BNX2_PCI_VPD_ADDR_FLAG_WR			 (1L<<15)

#define BNX2_PCI_VPD_DATA				0x00000430
#define BNX2_PCI_ID_VAL1				0x00000434
#define BNX2_PCI_ID_VAL1_DEVICE_ID			 (0xffffL<<0)
#define BNX2_PCI_ID_VAL1_VENDOR_ID			 (0xffffL<<16)

#define BNX2_PCI_ID_VAL2				0x00000438
#define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID		 (0xffffL<<0)
#define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID			 (0xffffL<<16)

#define BNX2_PCI_ID_VAL3				0x0000043c
#define BNX2_PCI_ID_VAL3_CLASS_CODE			 (0xffffffL<<0)
#define BNX2_PCI_ID_VAL3_REVISION_ID			 (0xffL<<24)

#define BNX2_PCI_ID_VAL4				0x00000440
#define BNX2_PCI_ID_VAL4_CAP_ENA			 (0xfL<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_0			 (0L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_1			 (1L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_2			 (2L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_3			 (3L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_4			 (4L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_5			 (5L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_6			 (6L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_7			 (7L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_8			 (8L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_9			 (9L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_10			 (10L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_11			 (11L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_12			 (12L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_13			 (13L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_14			 (14L<<0)
#define BNX2_PCI_ID_VAL4_CAP_ENA_15			 (15L<<0)
#define BNX2_PCI_ID_VAL4_RESERVED0			 (0x3L<<4)
#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG			 (0x3L<<6)
#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0			 (0L<<6)
#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1			 (1L<<6)
#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2			 (2L<<6)
#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3			 (3L<<6)
#define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP		 (1L<<8)
#define BNX2_PCI_ID_VAL4_MSI_LIMIT			 (0x7L<<9)