bnx2.h
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/* bnx2.h: Broadcom NX2 network driver. * * Copyright (c) 2004-2007 Broadcom Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. * * Written by: Michael Chan (mchan@broadcom.com) */#ifndef BNX2_H#define BNX2_H/* Hardware data structures and register definitions automatically * generated from RTL code. Do not modify. *//* * tx_bd definition */struct tx_bd { u32 tx_bd_haddr_hi; u32 tx_bd_haddr_lo; u32 tx_bd_mss_nbytes; #define TX_BD_TCP6_OFF2_SHL (14) u32 tx_bd_vlan_tag_flags; #define TX_BD_FLAGS_CONN_FAULT (1<<0) #define TX_BD_FLAGS_TCP6_OFF0_MSK (3<<1) #define TX_BD_FLAGS_TCP6_OFF0_SHL (1) #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) #define TX_BD_FLAGS_IP_CKSUM (1<<2) #define TX_BD_FLAGS_VLAN_TAG (1<<3) #define TX_BD_FLAGS_COAL_NOW (1<<4) #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) #define TX_BD_FLAGS_END (1<<6) #define TX_BD_FLAGS_START (1<<7) #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) #define TX_BD_FLAGS_TCP6_OFF4_SHL (12) #define TX_BD_FLAGS_SW_FLAGS (1<<13) #define TX_BD_FLAGS_SW_SNAP (1<<14) #define TX_BD_FLAGS_SW_LSO (1<<15)};/* * rx_bd definition */struct rx_bd { u32 rx_bd_haddr_hi; u32 rx_bd_haddr_lo; u32 rx_bd_len; u32 rx_bd_flags; #define RX_BD_FLAGS_NOPUSH (1<<0) #define RX_BD_FLAGS_DUMMY (1<<1) #define RX_BD_FLAGS_END (1<<2) #define RX_BD_FLAGS_START (1<<3)};#define BNX2_RX_ALIGN 16/* * status_block definition */struct status_block { u32 status_attn_bits; #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) #define STATUS_ATTN_BITS_EPB_ERROR (1L<<30) #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) u32 status_attn_bits_ack;#if defined(__BIG_ENDIAN) u16 status_tx_quick_consumer_index0; u16 status_tx_quick_consumer_index1; u16 status_tx_quick_consumer_index2; u16 status_tx_quick_consumer_index3; u16 status_rx_quick_consumer_index0; u16 status_rx_quick_consumer_index1; u16 status_rx_quick_consumer_index2; u16 status_rx_quick_consumer_index3; u16 status_rx_quick_consumer_index4; u16 status_rx_quick_consumer_index5; u16 status_rx_quick_consumer_index6; u16 status_rx_quick_consumer_index7; u16 status_rx_quick_consumer_index8; u16 status_rx_quick_consumer_index9; u16 status_rx_quick_consumer_index10; u16 status_rx_quick_consumer_index11; u16 status_rx_quick_consumer_index12; u16 status_rx_quick_consumer_index13; u16 status_rx_quick_consumer_index14; u16 status_rx_quick_consumer_index15; u16 status_completion_producer_index; u16 status_cmd_consumer_index; u16 status_idx; u8 status_unused; u8 status_blk_num;#elif defined(__LITTLE_ENDIAN) u16 status_tx_quick_consumer_index1; u16 status_tx_quick_consumer_index0; u16 status_tx_quick_consumer_index3; u16 status_tx_quick_consumer_index2; u16 status_rx_quick_consumer_index1; u16 status_rx_quick_consumer_index0; u16 status_rx_quick_consumer_index3; u16 status_rx_quick_consumer_index2; u16 status_rx_quick_consumer_index5; u16 status_rx_quick_consumer_index4; u16 status_rx_quick_consumer_index7; u16 status_rx_quick_consumer_index6; u16 status_rx_quick_consumer_index9; u16 status_rx_quick_consumer_index8; u16 status_rx_quick_consumer_index11; u16 status_rx_quick_consumer_index10; u16 status_rx_quick_consumer_index13; u16 status_rx_quick_consumer_index12; u16 status_rx_quick_consumer_index15; u16 status_rx_quick_consumer_index14; u16 status_cmd_consumer_index; u16 status_completion_producer_index; u8 status_blk_num; u8 status_unused; u16 status_idx;#endif};/* * statistics_block definition */struct statistics_block { u32 stat_IfHCInOctets_hi; u32 stat_IfHCInOctets_lo; u32 stat_IfHCInBadOctets_hi; u32 stat_IfHCInBadOctets_lo; u32 stat_IfHCOutOctets_hi; u32 stat_IfHCOutOctets_lo; u32 stat_IfHCOutBadOctets_hi; u32 stat_IfHCOutBadOctets_lo; u32 stat_IfHCInUcastPkts_hi; u32 stat_IfHCInUcastPkts_lo; u32 stat_IfHCInMulticastPkts_hi; u32 stat_IfHCInMulticastPkts_lo; u32 stat_IfHCInBroadcastPkts_hi; u32 stat_IfHCInBroadcastPkts_lo; u32 stat_IfHCOutUcastPkts_hi; u32 stat_IfHCOutUcastPkts_lo; u32 stat_IfHCOutMulticastPkts_hi; u32 stat_IfHCOutMulticastPkts_lo; u32 stat_IfHCOutBroadcastPkts_hi; u32 stat_IfHCOutBroadcastPkts_lo; u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; u32 stat_Dot3StatsCarrierSenseErrors; u32 stat_Dot3StatsFCSErrors; u32 stat_Dot3StatsAlignmentErrors; u32 stat_Dot3StatsSingleCollisionFrames; u32 stat_Dot3StatsMultipleCollisionFrames; u32 stat_Dot3StatsDeferredTransmissions; u32 stat_Dot3StatsExcessiveCollisions; u32 stat_Dot3StatsLateCollisions; u32 stat_EtherStatsCollisions; u32 stat_EtherStatsFragments; u32 stat_EtherStatsJabbers; u32 stat_EtherStatsUndersizePkts; u32 stat_EtherStatsOverrsizePkts; u32 stat_EtherStatsPktsRx64Octets; u32 stat_EtherStatsPktsRx65Octetsto127Octets; u32 stat_EtherStatsPktsRx128Octetsto255Octets; u32 stat_EtherStatsPktsRx256Octetsto511Octets; u32 stat_EtherStatsPktsRx512Octetsto1023Octets; u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; u32 stat_EtherStatsPktsTx64Octets; u32 stat_EtherStatsPktsTx65Octetsto127Octets; u32 stat_EtherStatsPktsTx128Octetsto255Octets; u32 stat_EtherStatsPktsTx256Octetsto511Octets; u32 stat_EtherStatsPktsTx512Octetsto1023Octets; u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; u32 stat_XonPauseFramesReceived; u32 stat_XoffPauseFramesReceived; u32 stat_OutXonSent; u32 stat_OutXoffSent; u32 stat_FlowControlDone; u32 stat_MacControlFramesReceived; u32 stat_XoffStateEntered; u32 stat_IfInFramesL2FilterDiscards; u32 stat_IfInRuleCheckerDiscards; u32 stat_IfInFTQDiscards; u32 stat_IfInMBUFDiscards; u32 stat_IfInRuleCheckerP4Hit; u32 stat_CatchupInRuleCheckerDiscards; u32 stat_CatchupInFTQDiscards; u32 stat_CatchupInMBUFDiscards; u32 stat_CatchupInRuleCheckerP4Hit; u32 stat_GenStat00; u32 stat_GenStat01; u32 stat_GenStat02; u32 stat_GenStat03; u32 stat_GenStat04; u32 stat_GenStat05; u32 stat_GenStat06; u32 stat_GenStat07; u32 stat_GenStat08; u32 stat_GenStat09; u32 stat_GenStat10; u32 stat_GenStat11; u32 stat_GenStat12; u32 stat_GenStat13; u32 stat_GenStat14; u32 stat_GenStat15; u32 stat_FwRxDrop;};/* * l2_fhdr definition */struct l2_fhdr { u32 l2_fhdr_status; #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) #define L2_FHDR_STATUS_RULE_P2 (1<<3) #define L2_FHDR_STATUS_RULE_P3 (1<<4) #define L2_FHDR_STATUS_RULE_P4 (1<<5) #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) #define L2_FHDR_STATUS_RSS_HASH (1<<8) #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) #define L2_FHDR_ERRORS_BAD_CRC (1<<17) #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) u32 l2_fhdr_hash;#if defined(__BIG_ENDIAN) u16 l2_fhdr_pkt_len; u16 l2_fhdr_vlan_tag; u16 l2_fhdr_ip_xsum; u16 l2_fhdr_tcp_udp_xsum;#elif defined(__LITTLE_ENDIAN) u16 l2_fhdr_vlan_tag; u16 l2_fhdr_pkt_len; u16 l2_fhdr_tcp_udp_xsum; u16 l2_fhdr_ip_xsum;#endif};/* * l2_context definition */⌨️ 快捷键说明
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