ns83820.c

linux 内核源代码

static const struct ethtool_ops ops = {
	.get_settings    = ns83820_get_settings,
	.set_settings    = ns83820_set_settings,
	.get_drvinfo     = ns83820_get_drvinfo,
	.get_link        = ns83820_get_link
};

/* this function is called in irq context from the ISR */
static void ns83820_mib_isr(struct ns83820 *dev)
{
	unsigned long flags;
	spin_lock_irqsave(&dev->misc_lock, flags);
	ns83820_update_stats(dev);
	spin_unlock_irqrestore(&dev->misc_lock, flags);
}

static void ns83820_do_isr(struct net_device *ndev, u32 isr);
static irqreturn_t ns83820_irq(int foo, void *data)
{
	struct net_device *ndev = data;
	struct ns83820 *dev = PRIV(ndev);
	u32 isr;
	dprintk("ns83820_irq(%p)\n", ndev);

	dev->ihr = 0;

	isr = readl(dev->base + ISR);
	dprintk("irq: %08x\n", isr);
	ns83820_do_isr(ndev, isr);
	return IRQ_HANDLED;
}

static void ns83820_do_isr(struct net_device *ndev, u32 isr)
{
	struct ns83820 *dev = PRIV(ndev);
	unsigned long flags;

#ifdef DEBUG
	if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
		Dprintk("odd isr? 0x%08x\n", isr);
#endif

	if (ISR_RXIDLE & isr) {
		dev->rx_info.idle = 1;
		Dprintk("oh dear, we are idle\n");
		ns83820_rx_kick(ndev);
	}

	if ((ISR_RXDESC | ISR_RXOK) & isr) {
		prefetch(dev->rx_info.next_rx_desc);

		spin_lock_irqsave(&dev->misc_lock, flags);
		dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
		writel(dev->IMR_cache, dev->base + IMR);
		spin_unlock_irqrestore(&dev->misc_lock, flags);

		tasklet_schedule(&dev->rx_tasklet);
		//rx_irq(ndev);
		//writel(4, dev->base + IHR);
	}

	if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
		ns83820_rx_kick(ndev);

	if (unlikely(ISR_RXSOVR & isr)) {
		//printk("overrun: rxsovr\n");
		dev->stats.rx_fifo_errors ++;
	}

	if (unlikely(ISR_RXORN & isr)) {
		//printk("overrun: rxorn\n");
		dev->stats.rx_fifo_errors ++;
	}

	if ((ISR_RXRCMP & isr) && dev->rx_info.up)
		writel(CR_RXE, dev->base + CR);

	if (ISR_TXIDLE & isr) {
		u32 txdp;
		txdp = readl(dev->base + TXDP);
		dprintk("txdp: %08x\n", txdp);
		txdp -= dev->tx_phy_descs;
		dev->tx_idx = txdp / (DESC_SIZE * 4);
		if (dev->tx_idx >= NR_TX_DESC) {
			printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
			dev->tx_idx = 0;
		}
		/* The may have been a race between a pci originated read
		 * and the descriptor update from the cpu.  Just in case,
		 * kick the transmitter if the hardware thinks it is on a
		 * different descriptor than we are.
		 */
		if (dev->tx_idx != dev->tx_free_idx)
			kick_tx(dev);
	}

	/* Defer tx ring processing until more than a minimum amount of
	 * work has accumulated
	 */
	if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
		spin_lock_irqsave(&dev->tx_lock, flags);
		do_tx_done(ndev);
		spin_unlock_irqrestore(&dev->tx_lock, flags);

		/* Disable TxOk if there are no outstanding tx packets.
		 */
		if ((dev->tx_done_idx == dev->tx_free_idx) &&
		    (dev->IMR_cache & ISR_TXOK)) {
			spin_lock_irqsave(&dev->misc_lock, flags);
			dev->IMR_cache &= ~ISR_TXOK;
			writel(dev->IMR_cache, dev->base + IMR);
			spin_unlock_irqrestore(&dev->misc_lock, flags);
		}
	}

	/* The TxIdle interrupt can come in before the transmit has
	 * completed.  Normally we reap packets off of the combination
	 * of TxDesc and TxIdle and leave TxOk disabled (since it
	 * occurs on every packet), but when no further irqs of this
	 * nature are expected, we must enable TxOk.
	 */
	if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
		spin_lock_irqsave(&dev->misc_lock, flags);
		dev->IMR_cache |= ISR_TXOK;
		writel(dev->IMR_cache, dev->base + IMR);
		spin_unlock_irqrestore(&dev->misc_lock, flags);
	}

	/* MIB interrupt: one of the statistics counters is about to overflow */
	if (unlikely(ISR_MIB & isr))
		ns83820_mib_isr(dev);

	/* PHY: Link up/down/negotiation state change */
	if (unlikely(ISR_PHY & isr))
		phy_intr(ndev);

#if 0	/* Still working on the interrupt mitigation strategy */
	if (dev->ihr)
		writel(dev->ihr, dev->base + IHR);
#endif
}

static void ns83820_do_reset(struct ns83820 *dev, u32 which)
{
	Dprintk("resetting chip...\n");
	writel(which, dev->base + CR);
	do {
		schedule();
	} while (readl(dev->base + CR) & which);
	Dprintk("okay!\n");
}

static int ns83820_stop(struct net_device *ndev)
{
	struct ns83820 *dev = PRIV(ndev);

	/* FIXME: protect against interrupt handler? */
	del_timer_sync(&dev->tx_watchdog);

	/* disable interrupts */
	writel(0, dev->base + IMR);
	writel(0, dev->base + IER);
	readl(dev->base + IER);

	dev->rx_info.up = 0;
	synchronize_irq(dev->pci_dev->irq);

	ns83820_do_reset(dev, CR_RST);

	synchronize_irq(dev->pci_dev->irq);

	spin_lock_irq(&dev->misc_lock);
	dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
	spin_unlock_irq(&dev->misc_lock);

	ns83820_cleanup_rx(dev);
	ns83820_cleanup_tx(dev);

	return 0;
}

static void ns83820_tx_timeout(struct net_device *ndev)
{
	struct ns83820 *dev = PRIV(ndev);
        u32 tx_done_idx;
	__le32 *desc;
	unsigned long flags;

	spin_lock_irqsave(&dev->tx_lock, flags);

	tx_done_idx = dev->tx_done_idx;
	desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);

	printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
		ndev->name,
		tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));

#if defined(DEBUG)
	{
		u32 isr;
		isr = readl(dev->base + ISR);
		printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
		ns83820_do_isr(ndev, isr);
	}
#endif

	do_tx_done(ndev);

	tx_done_idx = dev->tx_done_idx;
	desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);

	printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
		ndev->name,
		tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));

	spin_unlock_irqrestore(&dev->tx_lock, flags);
}

static void ns83820_tx_watch(unsigned long data)
{
	struct net_device *ndev = (void *)data;
	struct ns83820 *dev = PRIV(ndev);

#if defined(DEBUG)
	printk("ns83820_tx_watch: %u %u %d\n",
		dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
		);
#endif

	if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
	    dev->tx_done_idx != dev->tx_free_idx) {
		printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
			ndev->name,
			dev->tx_done_idx, dev->tx_free_idx,
			atomic_read(&dev->nr_tx_skbs));
		ns83820_tx_timeout(ndev);
	}

	mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
}

static int ns83820_open(struct net_device *ndev)
{
	struct ns83820 *dev = PRIV(ndev);
	unsigned i;
	u32 desc;
	int ret;

	dprintk("ns83820_open\n");

	writel(0, dev->base + PQCR);

	ret = ns83820_setup_rx(ndev);
	if (ret)
		goto failed;

	memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
	for (i=0; i<NR_TX_DESC; i++) {
		dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
				= cpu_to_le32(
				  dev->tx_phy_descs
				  + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
	}

	dev->tx_idx = 0;
	dev->tx_done_idx = 0;
	desc = dev->tx_phy_descs;
	writel(0, dev->base + TXDP_HI);
	writel(desc, dev->base + TXDP);

	init_timer(&dev->tx_watchdog);
	dev->tx_watchdog.data = (unsigned long)ndev;
	dev->tx_watchdog.function = ns83820_tx_watch;
	mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);

	netif_start_queue(ndev);	/* FIXME: wait for phy to come up */

	return 0;

failed:
	ns83820_stop(ndev);
	return ret;
}

static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
{
	unsigned i;
	for (i=0; i<3; i++) {
		u32 data;

		/* Read from the perfect match memory: this is loaded by
		 * the chip from the EEPROM via the EELOAD self test.
		 */
		writel(i*2, dev->base + RFCR);
		data = readl(dev->base + RFDR);

		*mac++ = data;
		*mac++ = data >> 8;
	}
}

static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
{
	if (new_mtu > RX_BUF_SIZE)
		return -EINVAL;
	ndev->mtu = new_mtu;
	return 0;
}

static void ns83820_set_multicast(struct net_device *ndev)
{
	struct ns83820 *dev = PRIV(ndev);
	u8 __iomem *rfcr = dev->base + RFCR;
	u32 and_mask = 0xffffffff;
	u32 or_mask = 0;
	u32 val;

	if (ndev->flags & IFF_PROMISC)
		or_mask |= RFCR_AAU | RFCR_AAM;
	else
		and_mask &= ~(RFCR_AAU | RFCR_AAM);

	if (ndev->flags & IFF_ALLMULTI || ndev->mc_count)
		or_mask |= RFCR_AAM;
	else
		and_mask &= ~RFCR_AAM;

	spin_lock_irq(&dev->misc_lock);
	val = (readl(rfcr) & and_mask) | or_mask;
	/* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
	writel(val & ~RFCR_RFEN, rfcr);
	writel(val, rfcr);
	spin_unlock_irq(&dev->misc_lock);
}

static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
{
	struct ns83820 *dev = PRIV(ndev);
	int timed_out = 0;
	unsigned long start;
	u32 status;
	int loops = 0;

	dprintk("%s: start %s\n", ndev->name, name);

	start = jiffies;

	writel(enable, dev->base + PTSCR);
	for (;;) {
		loops++;
		status = readl(dev->base + PTSCR);
		if (!(status & enable))
			break;
		if (status & done)
			break;
		if (status & fail)
			break;
		if (time_after_eq(jiffies, start + HZ)) {
			timed_out = 1;
			break;
		}
		schedule_timeout_uninterruptible(1);
	}

	if (status & fail)
		printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
			ndev->name, name, status, fail);
	else if (timed_out)
		printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
			ndev->name, name, status);

	dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
}

#ifdef PHY_CODE_IS_FINISHED
static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
{
	/* drive MDC low */
	dev->MEAR_cache &= ~MEAR_MDC;
	writel(dev->MEAR_cache, dev->base + MEAR);
	readl(dev->base + MEAR);

	/* enable output, set bit */
	dev->MEAR_cache |= MEAR_MDDIR;
	if (bit)
		dev->MEAR_cache |= MEAR_MDIO;
	else
		dev->MEAR_cache &= ~MEAR_MDIO;

	/* set the output bit */
	writel(dev->MEAR_cache, dev->base + MEAR);
	readl(dev->base + MEAR);

	/* Wait.  Max clock rate is 2.5MHz, this way we come in under 1MHz */
	udelay(1);

	/* drive MDC high causing the data bit to be latched */
	dev->MEAR_cache |= MEAR_MDC;
	writel(dev->MEAR_cache, dev->base + MEAR);
	readl(dev->base + MEAR);

	/* Wait again... */
	udelay(1);
}

static int ns83820_mii_read_bit(struct ns83820 *dev)
{
	int bit;

	/* drive MDC low, disable output */
	dev->MEAR_cache &= ~MEAR_MDC;
	dev->MEAR_cache &= ~MEAR_MDDIR;
	writel(dev->MEAR_cache, dev->base + MEAR);
	readl(dev->base + MEAR);

	/* Wait.  Max clock rate is 2.5MHz, this way we come in under 1MHz */
	udelay(1);

	/* drive MDC high causing the data bit to be latched */
	bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
	dev->MEAR_cache |= MEAR_MDC;
	writel(dev->MEAR_cache, dev->base + MEAR);

	/* Wait again... */
	udelay(1);

	return bit;
}

static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
{
	unsigned data = 0;
	int i;

	/* read some garbage so that we eventually sync up */
	for (i=0; i<64; i++)
		ns83820_mii_read_bit(dev);

	ns83820_mii_write_bit(dev, 0);	/* start */
	ns83820_mii_write_bit(dev, 1);
	ns83820_mii_write_bit(dev, 1);	/* opcode read */
	ns83820_mii_write_bit(dev, 0);

	/* write out the phy address: 5 bits, msb first */
	for (i=0; i<5; i++)
		ns83820_mii_write_bit(dev, phy & (0x10 >> i));

	/* write out the register address, 5 bits, msb first */
	for (i=0; i<5; i++)
		ns83820_mii_write_bit(dev, reg & (0x10 >> i));

	ns83820_mii_read_bit(dev);	/* turn around cycles */
	ns83820_mii_read_bit(dev);

	/* read in the register data, 16 bits msb first */
	for (i=0; i<16; i++) {
		data <<= 1;
		data |= ns83820_mii_read_bit(dev);
	}

	return data;
}

static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
{
	int i;

	/* read some garbage so that we eventually sync up */
	for (i=0; i<64; i++)