niu.h

linux 内核源代码

/* IPV4 TCAM format */
#define TCAM_V4KEY0_RESV1		0xffffffffffffff00ULL
#define TCAM_V4KEY0_CLASS_CODE		0x00000000000000f8ULL
#define TCAM_V4KEY0_CLASS_CODE_SHIFT	3
#define TCAM_V4KEY0_RESV2		0x0000000000000007ULL
#define TCAM_V4KEY1_L2RDCNUM		0xf800000000000000ULL
#define TCAM_V4KEY1_L2RDCNUM_SHIFT	59
#define TCAM_V4KEY1_NOPORT		0x0400000000000000ULL
#define TCAM_V4KEY1_RESV		0x03ffffffffffffffULL
#define TCAM_V4KEY2_RESV		0xffff000000000000ULL
#define TCAM_V4KEY2_TOS			0x0000ff0000000000ULL
#define TCAM_V4KEY2_TOS_SHIFT		40
#define TCAM_V4KEY2_PROTO		0x000000ff00000000ULL
#define TCAM_V4KEY2_PROTO_SHIFT		32
#define TCAM_V4KEY2_PORT_SPI		0x00000000ffffffffULL
#define TCAM_V4KEY2_PORT_SPI_SHIFT	0
#define TCAM_V4KEY3_SADDR		0xffffffff00000000ULL
#define TCAM_V4KEY3_SADDR_SHIFT		32
#define TCAM_V4KEY3_DADDR		0x00000000ffffffffULL
#define TCAM_V4KEY3_DADDR_SHIFT		0

/* IPV6 TCAM format */
#define TCAM_V6KEY0_RESV1		0xffffffffffffff00ULL
#define TCAM_V6KEY0_CLASS_CODE		0x00000000000000f8ULL
#define TCAM_V6KEY0_CLASS_CODE_SHIFT	3
#define TCAM_V6KEY0_RESV2		0x0000000000000007ULL
#define TCAM_V6KEY1_L2RDCNUM		0xf800000000000000ULL
#define TCAM_V6KEY1_L2RDCNUM_SHIFT	59
#define TCAM_V6KEY1_NOPORT		0x0400000000000000ULL
#define TCAM_V6KEY1_RESV		0x03ff000000000000ULL
#define TCAM_V6KEY1_TOS			0x0000ff0000000000ULL
#define TCAM_V6KEY1_TOS_SHIFT		40
#define TCAM_V6KEY1_NEXT_HDR		0x000000ff00000000ULL
#define TCAM_V6KEY1_NEXT_HDR_SHIFT	32
#define TCAM_V6KEY1_PORT_SPI		0x00000000ffffffffULL
#define TCAM_V6KEY1_PORT_SPI_SHIFT	0
#define TCAM_V6KEY2_ADDR_HIGH		0xffffffffffffffffULL
#define TCAM_V6KEY3_ADDR_LOW		0xffffffffffffffffULL

#define TCAM_ASSOCDATA_SYNDROME		0x000003fffc000000ULL
#define TCAM_ASSOCDATA_SYNDROME_SHIFT	26
#define TCAM_ASSOCDATA_ZFID		0x0000000003ffc000ULL
#define TCAM_ASSOCDATA_ZFID_SHIFT	14
#define TCAM_ASSOCDATA_V4_ECC_OK	0x0000000000002000ULL
#define TCAM_ASSOCDATA_DISC		0x0000000000001000ULL
#define TCAM_ASSOCDATA_TRES_MASK	0x0000000000000c00ULL
#define TCAM_ASSOCDATA_TRES_USE_L2RDC	0x0000000000000000ULL
#define TCAM_ASSOCDATA_TRES_USE_OFFSET	0x0000000000000400ULL
#define TCAM_ASSOCDATA_TRES_OVR_RDC	0x0000000000000800ULL
#define TCAM_ASSOCDATA_TRES_OVR_RDC_OFF	0x0000000000000c00ULL
#define TCAM_ASSOCDATA_RDCTBL		0x0000000000000380ULL
#define TCAM_ASSOCDATA_RDCTBL_SHIFT	7
#define TCAM_ASSOCDATA_OFFSET		0x000000000000007cULL
#define TCAM_ASSOCDATA_OFFSET_SHIFT	2
#define TCAM_ASSOCDATA_ZFVLD		0x0000000000000002ULL
#define TCAM_ASSOCDATA_AGE		0x0000000000000001ULL

#define FLOW_KEY(IDX)			(FZC_FFLP + 0x40000UL + (IDX) * 8UL)
#define  FLOW_KEY_PORT			0x0000000000000200ULL
#define  FLOW_KEY_L2DA			0x0000000000000100ULL
#define  FLOW_KEY_VLAN			0x0000000000000080ULL
#define  FLOW_KEY_IPSA			0x0000000000000040ULL
#define  FLOW_KEY_IPDA			0x0000000000000020ULL
#define  FLOW_KEY_PROTO			0x0000000000000010ULL
#define  FLOW_KEY_L4_0			0x000000000000000cULL
#define  FLOW_KEY_L4_0_SHIFT		2
#define  FLOW_KEY_L4_1			0x0000000000000003ULL
#define  FLOW_KEY_L4_1_SHIFT		0

#define  FLOW_KEY_L4_NONE		0x0
#define  FLOW_KEY_L4_RESV		0x1
#define  FLOW_KEY_L4_BYTE12		0x2
#define  FLOW_KEY_L4_BYTE56		0x3

#define H1POLY				(FZC_FFLP + 0x40060UL)
#define  H1POLY_INITVAL			0x00000000ffffffffULL

#define H2POLY				(FZC_FFLP + 0x40068UL)
#define  H2POLY_INITVAL			0x000000000000ffffULL

#define FLW_PRT_SEL(IDX)		(FZC_FFLP + 0x40070UL + (IDX) * 8UL)
#define  FLW_PRT_SEL_EXT		0x0000000000010000ULL
#define  FLW_PRT_SEL_MASK		0x0000000000001f00ULL
#define  FLW_PRT_SEL_MASK_SHIFT		8
#define  FLW_PRT_SEL_BASE		0x000000000000001fULL
#define  FLW_PRT_SEL_BASE_SHIFT		0

#define HASH_TBL_ADDR(IDX)		(FFLP + 0x00000UL + (IDX) * 8192UL)
#define  HASH_TBL_ADDR_AUTOINC		0x0000000000800000ULL
#define  HASH_TBL_ADDR_ADDR		0x00000000007fffffULL

#define HASH_TBL_DATA(IDX)		(FFLP + 0x00008UL + (IDX) * 8192UL)
#define  HASH_TBL_DATA_DATA		0xffffffffffffffffULL

/* FCRAM hash table entries are up to 8 64-bit words in size.
 * The layout of each entry is determined by the settings in the
 * first word, which is the header.
 *
 * The indexing is controllable per partition (there is one partition
 * per RDC group, thus a total of eight) using the BASE and MASK fields
 * of FLW_PRT_SEL above.
 */
#define FCRAM_SIZE			0x800000
#define FCRAM_NUM_PARTITIONS		8

/* Generic HASH entry header, used for all non-optimized formats.  */
#define HASH_HEADER_FMT			0x8000000000000000ULL
#define HASH_HEADER_EXT			0x4000000000000000ULL
#define HASH_HEADER_VALID		0x2000000000000000ULL
#define HASH_HEADER_RESVD		0x1000000000000000ULL
#define HASH_HEADER_L2_DADDR		0x0ffffffffffff000ULL
#define HASH_HEADER_L2_DADDR_SHIFT	12
#define HASH_HEADER_VLAN		0x0000000000000fffULL
#define HASH_HEADER_VLAN_SHIFT		0

/* Optimized format, just a header with a special layout defined below.
 * Set FMT and EXT both to zero to indicate this layout is being used.
 */
#define HASH_OPT_HEADER_FMT		0x8000000000000000ULL
#define HASH_OPT_HEADER_EXT		0x4000000000000000ULL
#define HASH_OPT_HEADER_VALID		0x2000000000000000ULL
#define HASH_OPT_HEADER_RDCOFF		0x1f00000000000000ULL
#define HASH_OPT_HEADER_RDCOFF_SHIFT	56
#define HASH_OPT_HEADER_HASH2		0x00ffff0000000000ULL
#define HASH_OPT_HEADER_HASH2_SHIFT	40
#define HASH_OPT_HEADER_RESVD		0x000000ff00000000ULL
#define HASH_OPT_HEADER_USERINFO	0x00000000ffffffffULL
#define HASH_OPT_HEADER_USERINFO_SHIFT	0

/* Port and protocol word used for ipv4 and ipv6 layouts.  */
#define HASH_PORT_DPORT			0xffff000000000000ULL
#define HASH_PORT_DPORT_SHIFT		48
#define HASH_PORT_SPORT			0x0000ffff00000000ULL
#define HASH_PORT_SPORT_SHIFT		32
#define HASH_PORT_PROTO			0x00000000ff000000ULL
#define HASH_PORT_PROTO_SHIFT		24
#define HASH_PORT_PORT_OFF		0x0000000000c00000ULL
#define HASH_PORT_PORT_OFF_SHIFT	22
#define HASH_PORT_PORT_RESV		0x00000000003fffffULL

/* Action word used for ipv4 and ipv6 layouts.  */
#define HASH_ACTION_RESV1		0xe000000000000000ULL
#define HASH_ACTION_RDCOFF		0x1f00000000000000ULL
#define HASH_ACTION_RDCOFF_SHIFT	56
#define HASH_ACTION_ZFVALID		0x0080000000000000ULL
#define HASH_ACTION_RESV2		0x0070000000000000ULL
#define HASH_ACTION_ZFID		0x000fff0000000000ULL
#define HASH_ACTION_ZFID_SHIFT		40
#define HASH_ACTION_RESV3		0x000000ff00000000ULL
#define HASH_ACTION_USERINFO		0x00000000ffffffffULL
#define HASH_ACTION_USERINFO_SHIFT	0

/* IPV4 address word.  Addresses are in network endian. */
#define HASH_IP4ADDR_SADDR		0xffffffff00000000ULL
#define HASH_IP4ADDR_SADDR_SHIFT	32
#define HASH_IP4ADDR_DADDR		0x00000000ffffffffULL
#define HASH_IP4ADDR_DADDR_SHIFT	0

/* IPV6 address layout is 4 words, first two are saddr, next two
 * are daddr.  Addresses are in network endian.
 */

struct fcram_hash_opt {
	u64	header;
};

/* EXT=1, FMT=0 */
struct fcram_hash_ipv4 {
	u64	header;
	u64	addrs;
	u64	ports;
	u64	action;
};

/* EXT=1, FMT=1 */
struct fcram_hash_ipv6 {
	u64	header;
	u64	addrs[4];
	u64	ports;
	u64	action;
};

#define HASH_TBL_DATA_LOG(IDX)		(FFLP + 0x00010UL + (IDX) * 8192UL)
#define  HASH_TBL_DATA_LOG_ERR		0x0000000080000000ULL
#define  HASH_TBL_DATA_LOG_ADDR		0x000000007fffff00ULL
#define  HASH_TBL_DATA_LOG_SYNDROME	0x00000000000000ffULL

#define RX_DMA_CK_DIV			(FZC_DMC + 0x00000UL)
#define  RX_DMA_CK_DIV_CNT		0x000000000000ffffULL

#define DEF_RDC(IDX)			(FZC_DMC + 0x00008UL + (IDX) * 0x8UL)
#define  DEF_RDC_VAL			0x000000000000001fULL

#define PT_DRR_WT(IDX)			(FZC_DMC + 0x00028UL + (IDX) * 0x8UL)
#define  PT_DRR_WT_VAL			0x000000000000ffffULL

#define PT_DRR_WEIGHT_DEFAULT_10G	0x0400
#define PT_DRR_WEIGHT_DEFAULT_1G	0x0066

#define PT_USE(IDX)			(FZC_DMC + 0x00048UL + (IDX) * 0x8UL)
#define  PT_USE_CNT			0x00000000000fffffULL

#define RED_RAN_INIT			(FZC_DMC + 0x00068UL)
#define  RED_RAN_INIT_OPMODE		0x0000000000010000ULL
#define  RED_RAN_INIT_VAL		0x000000000000ffffULL

#define RX_ADDR_MD			(FZC_DMC + 0x00070UL)
#define  RX_ADDR_MD_DBG_PT_MUX_SEL	0x000000000000000cULL
#define  RX_ADDR_MD_RAM_ACC		0x0000000000000002ULL
#define  RX_ADDR_MD_MODE32		0x0000000000000001ULL

#define RDMC_PRE_PAR_ERR		(FZC_DMC + 0x00078UL)
#define  RDMC_PRE_PAR_ERR_ERR		0x0000000000008000ULL
#define  RDMC_PRE_PAR_ERR_MERR		0x0000000000004000ULL
#define  RDMC_PRE_PAR_ERR_ADDR		0x00000000000000ffULL

#define RDMC_SHA_PAR_ERR		(FZC_DMC + 0x00080UL)
#define  RDMC_SHA_PAR_ERR_ERR		0x0000000000008000ULL
#define  RDMC_SHA_PAR_ERR_MERR		0x0000000000004000ULL
#define  RDMC_SHA_PAR_ERR_ADDR		0x00000000000000ffULL

#define RDMC_MEM_ADDR			(FZC_DMC + 0x00088UL)
#define  RDMC_MEM_ADDR_PRE_SHAD		0x0000000000000100ULL
#define  RDMC_MEM_ADDR_ADDR		0x00000000000000ffULL

#define RDMC_MEM_DAT0			(FZC_DMC + 0x00090UL)
#define  RDMC_MEM_DAT0_DATA		0x00000000ffffffffULL /* bits 31:0 */

#define RDMC_MEM_DAT1			(FZC_DMC + 0x00098UL)
#define  RDMC_MEM_DAT1_DATA		0x00000000ffffffffULL /* bits 63:32 */

#define RDMC_MEM_DAT2			(FZC_DMC + 0x000a0UL)
#define  RDMC_MEM_DAT2_DATA		0x00000000ffffffffULL /* bits 95:64 */

#define RDMC_MEM_DAT3			(FZC_DMC + 0x000a8UL)
#define  RDMC_MEM_DAT3_DATA		0x00000000ffffffffULL /* bits 127:96 */

#define RDMC_MEM_DAT4			(FZC_DMC + 0x000b0UL)
#define  RDMC_MEM_DAT4_DATA		0x00000000000fffffULL /* bits 147:128 */

#define RX_CTL_DAT_FIFO_STAT			(FZC_DMC + 0x000b8UL)
#define  RX_CTL_DAT_FIFO_STAT_ID_MISMATCH	0x0000000000000100ULL
#define  RX_CTL_DAT_FIFO_STAT_ZCP_EOP_ERR	0x00000000000000f0ULL
#define  RX_CTL_DAT_FIFO_STAT_IPP_EOP_ERR	0x000000000000000fULL

#define RX_CTL_DAT_FIFO_MASK			(FZC_DMC + 0x000c0UL)
#define  RX_CTL_DAT_FIFO_MASK_ID_MISMATCH	0x0000000000000100ULL
#define  RX_CTL_DAT_FIFO_MASK_ZCP_EOP_ERR	0x00000000000000f0ULL
#define  RX_CTL_DAT_FIFO_MASK_IPP_EOP_ERR	0x000000000000000fULL

#define RDMC_TRAINING_VECTOR			(FZC_DMC + 0x000c8UL)
#define  RDMC_TRAINING_VECTOR_TRAINING_VECTOR	0x00000000ffffffffULL

#define RX_CTL_DAT_FIFO_STAT_DBG		(FZC_DMC + 0x000d0UL)
#define  RX_CTL_DAT_FIFO_STAT_DBG_ID_MISMATCH	0x0000000000000100ULL
#define  RX_CTL_DAT_FIFO_STAT_DBG_ZCP_EOP_ERR	0x00000000000000f0ULL
#define  RX_CTL_DAT_FIFO_STAT_DBG_IPP_EOP_ERR	0x000000000000000fULL

#define RDC_TBL(TBL,SLOT)		(FZC_ZCP + 0x10000UL + \
					 (TBL) * (8UL * 16UL) + \
					 (SLOT) * 8UL)
#define  RDC_TBL_RDC			0x000000000000000fULL

#define RX_LOG_PAGE_VLD(IDX)		(FZC_DMC + 0x20000UL + (IDX) * 0x40UL)
#define  RX_LOG_PAGE_VLD_FUNC		0x000000000000000cULL
#define  RX_LOG_PAGE_VLD_FUNC_SHIFT	2
#define  RX_LOG_PAGE_VLD_PAGE1		0x0000000000000002ULL
#define  RX_LOG_PAGE_VLD_PAGE0		0x0000000000000001ULL

#define RX_LOG_MASK1(IDX)		(FZC_DMC + 0x20008UL + (IDX) * 0x40UL)
#define  RX_LOG_MASK1_MASK		0x00000000ffffffffULL

#define RX_LOG_VAL1(IDX)		(FZC_DMC + 0x20010UL + (IDX) * 0x40UL)
#define  RX_LOG_VAL1_VALUE		0x00000000ffffffffULL

#define RX_LOG_MASK2(IDX)		(FZC_DMC + 0x20018UL + (IDX) * 0x40UL)
#define  RX_LOG_MASK2_MASK		0x00000000ffffffffULL

#define RX_LOG_VAL2(IDX)		(FZC_DMC + 0x20020UL + (IDX) * 0x40UL)
#define  RX_LOG_VAL2_VALUE		0x00000000ffffffffULL

#define RX_LOG_PAGE_RELO1(IDX)		(FZC_DMC + 0x20028UL + (IDX) * 0x40UL)
#define  RX_LOG_PAGE_RELO1_RELO		0x00000000ffffffffULL

#define RX_LOG_PAGE_RELO2(IDX)		(FZC_DMC + 0x20030UL + (IDX) * 0x40UL)
#define  RX_LOG_PAGE_RELO2_RELO		0x00000000ffffffffULL

#define RX_LOG_PAGE_HDL(IDX)		(FZC_DMC + 0x20038UL + (IDX) * 0x40UL)
#define  RX_LOG_PAGE_HDL_HANDLE		0x00000000000fffffULL

#define TX_LOG_PAGE_VLD(IDX)		(FZC_DMC + 0x40000UL + (IDX) * 0x200UL)
#define  TX_LOG_PAGE_VLD_FUNC		0x000000000000000cULL
#define  TX_LOG_PAGE_VLD_FUNC_SHIFT	2
#define  TX_LOG_PAGE_VLD_PAGE1		0x0000000000000002ULL
#define  TX_LOG_PAGE_VLD_PAGE0		0x0000000000000001ULL

#define TX_LOG_MASK1(IDX)		(FZC_DMC + 0x40008UL + (IDX) * 0x200UL)
#define  TX_LOG_MASK1_MASK		0x00000000ffffffffULL

#define TX_LOG_VAL1(IDX)		(FZC_DMC + 0x40010UL + (IDX) * 0x200UL)
#define  TX_LOG_VAL1_VALUE		0x00000000ffffffffULL

#define TX_LOG_MASK2(IDX)		(FZC_DMC + 0x40018UL + (IDX) * 0x200UL)
#define  TX_LOG_MASK2_MASK		0x00000000ffffffffULL

#define TX_LOG_VAL2(IDX)		(FZC_DMC + 0x40020UL + (IDX) * 0x200UL)
#define  TX_LOG_VAL2_VALUE		0x00000000ffffffffULL

#define TX_LOG_PAGE_RELO1(IDX)		(FZC_DMC + 0x40028UL + (IDX) * 0x200UL)
#define  TX_LOG_PAGE_RELO1_RELO		0x00000000ffffffffULL

#define TX_LOG_PAGE_RELO2(IDX)		(FZC_DMC + 0x40030UL + (IDX) * 0x200UL)
#define  TX_LOG_PAGE_RELO2_RELO		0x00000000ffffffffULL

#define TX_LOG_PAGE_HDL(IDX)		(FZC_DMC + 0x40038UL + (IDX) * 0x200UL)
#define  TX_LOG_PAGE_HDL_HANDLE		0x00000000000fffffULL

#define TX_ADDR_MD			(FZC_DMC + 0x45000UL)
#define  TX_ADDR_MD_MODE32		0x0000000000000001ULL

#define RDC_RED_PARA(IDX)		(FZC_DMC + 0x30000UL + (IDX) * 0x40UL)
#define  RDC_RED_PARA_THRE_SYN		0x00000000fff00000ULL
#define  RDC_RED_PARA_THRE_SYN_SHIFT	20
#define  RDC_RED_PARA_WIN_SYN		0x00000000000f