niu.h

linux 内核源代码

#define  ESR_RXTX_CTRL_RESV2		0x000f0000
#define  ESR_RXTX_CTRL_RESV3		0x0000c000
#define  ESR_RXTX_CTRL_RXPRESWIN	0x00003000
#define  ESR_RXTX_CTRL_RXPRESWIN_SHIFT	12
#define  ESR_RXTX_CTRL_RESV4		0x00000800
#define  ESR_RXTX_CTRL_RISEFALL		0x00000700
#define  ESR_RXTX_CTRL_RISEFALL_SHIFT	8
#define  ESR_RXTX_CTRL_RESV5		0x000000fe
#define  ESR_RXTX_CTRL_ENSTRETCH	0x00000001

#define ESR_RXTX_TUNING_L(CHAN)		(ESR_BASE + 0x0082 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING_H(CHAN)		(ESR_BASE + 0x0083 + (CHAN) * 0x10)

#define ESR_RX_SYNCCHAR_L(CHAN)		(ESR_BASE + 0x0084 + (CHAN) * 0x10)
#define ESR_RX_SYNCCHAR_H(CHAN)		(ESR_BASE + 0x0085 + (CHAN) * 0x10)

#define ESR_RXTX_TEST_L(CHAN)		(ESR_BASE + 0x0086 + (CHAN) * 0x10)
#define ESR_RXTX_TEST_H(CHAN)		(ESR_BASE + 0x0087 + (CHAN) * 0x10)

#define ESR_GLUE_CTRL0_L(CHAN)		(ESR_BASE + 0x0088 + (CHAN) * 0x10)
#define ESR_GLUE_CTRL0_H(CHAN)		(ESR_BASE + 0x0089 + (CHAN) * 0x10)
#define  ESR_GLUE_CTRL0_RESV1		0xf8000000
#define  ESR_GLUE_CTRL0_BLTIME		0x07000000
#define  ESR_GLUE_CTRL0_BLTIME_SHIFT	24
#define  ESR_GLUE_CTRL0_RESV2		0x00ff0000
#define  ESR_GLUE_CTRL0_RXLOS_TEST	0x00008000
#define  ESR_GLUE_CTRL0_RESV3		0x00004000
#define  ESR_GLUE_CTRL0_RXLOSENAB	0x00002000
#define  ESR_GLUE_CTRL0_FASTRESYNC	0x00001000
#define  ESR_GLUE_CTRL0_SRATE		0x00000f00
#define  ESR_GLUE_CTRL0_SRATE_SHIFT	8
#define  ESR_GLUE_CTRL0_THCNT		0x000000ff
#define  ESR_GLUE_CTRL0_THCNT_SHIFT	0

#define BLTIME_64_CYCLES		0
#define BLTIME_128_CYCLES		1
#define BLTIME_256_CYCLES		2
#define BLTIME_300_CYCLES		3
#define BLTIME_384_CYCLES		4
#define BLTIME_512_CYCLES		5
#define BLTIME_1024_CYCLES		6
#define BLTIME_2048_CYCLES		7

#define ESR_GLUE_CTRL1_L(CHAN)		(ESR_BASE + 0x008a + (CHAN) * 0x10)
#define ESR_GLUE_CTRL1_H(CHAN)		(ESR_BASE + 0x008b + (CHAN) * 0x10)
#define ESR_RXTX_TUNING1_L(CHAN)	(ESR_BASE + 0x00c2 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING1_H(CHAN)	(ESR_BASE + 0x00c2 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING2_L(CHAN)	(ESR_BASE + 0x0102 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING2_H(CHAN)	(ESR_BASE + 0x0102 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING3_L(CHAN)	(ESR_BASE + 0x0142 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING3_H(CHAN)	(ESR_BASE + 0x0142 + (CHAN) * 0x10)

#define NIU_ESR2_DEV_ADDR		0x1e
#define ESR2_BASE			0x8000

#define ESR2_TI_PLL_CFG_L		(ESR2_BASE + 0x000)
#define ESR2_TI_PLL_CFG_H		(ESR2_BASE + 0x001)
#define  PLL_CFG_STD			0x00000c00
#define  PLL_CFG_STD_SHIFT		10
#define  PLL_CFG_LD			0x00000300
#define  PLL_CFG_LD_SHIFT		8
#define  PLL_CFG_MPY			0x0000001e
#define  PLL_CFG_MPY_SHIFT		1
#define  PLL_CFG_ENPLL			0x00000001

#define ESR2_TI_PLL_STS_L		(ESR2_BASE + 0x002)
#define ESR2_TI_PLL_STS_H		(ESR2_BASE + 0x003)
#define  PLL_STS_LOCK			0x00000001

#define ESR2_TI_PLL_TEST_CFG_L		(ESR2_BASE + 0x004)
#define ESR2_TI_PLL_TEST_CFG_H		(ESR2_BASE + 0x005)
#define  PLL_TEST_INVPATT		0x00004000
#define  PLL_TEST_RATE			0x00003000
#define  PLL_TEST_RATE_SHIFT		12
#define  PLL_TEST_CFG_ENBSAC		0x00000400
#define  PLL_TEST_CFG_ENBSRX		0x00000200
#define  PLL_TEST_CFG_ENBSTX		0x00000100
#define  PLL_TEST_CFG_LOOPBACK_PAD	0x00000040
#define  PLL_TEST_CFG_LOOPBACK_CML_DIS	0x00000080
#define  PLL_TEST_CFG_LOOPBACK_CML_EN	0x000000c0
#define  PLL_TEST_CFG_CLKBYP		0x00000030
#define  PLL_TEST_CFG_CLKBYP_SHIFT	4
#define  PLL_TEST_CFG_EN_RXPATT		0x00000008
#define  PLL_TEST_CFG_EN_TXPATT		0x00000004
#define  PLL_TEST_CFG_TPATT		0x00000003
#define  PLL_TEST_CFG_TPATT_SHIFT	0

#define ESR2_TI_PLL_TX_CFG_L(CHAN)	(ESR2_BASE + 0x100 + (CHAN) * 4)
#define ESR2_TI_PLL_TX_CFG_H(CHAN)	(ESR2_BASE + 0x101 + (CHAN) * 4)
#define  PLL_TX_CFG_RDTCT		0x00600000
#define  PLL_TX_CFG_RDTCT_SHIFT		21
#define  PLL_TX_CFG_ENIDL		0x00100000
#define  PLL_TX_CFG_BSTX		0x00020000
#define  PLL_TX_CFG_ENFTP		0x00010000
#define  PLL_TX_CFG_DE			0x0000f000
#define  PLL_TX_CFG_DE_SHIFT		12
#define  PLL_TX_CFG_SWING_125MV		0x00000000
#define  PLL_TX_CFG_SWING_250MV		0x00000200
#define  PLL_TX_CFG_SWING_500MV		0x00000400
#define  PLL_TX_CFG_SWING_625MV		0x00000600
#define  PLL_TX_CFG_SWING_750MV		0x00000800
#define  PLL_TX_CFG_SWING_1000MV	0x00000a00
#define  PLL_TX_CFG_SWING_1250MV	0x00000c00
#define  PLL_TX_CFG_SWING_1375MV	0x00000e00
#define  PLL_TX_CFG_CM			0x00000100
#define  PLL_TX_CFG_INVPAIR		0x00000080
#define  PLL_TX_CFG_RATE		0x00000060
#define  PLL_TX_CFG_RATE_SHIFT		5
#define  PLL_TX_CFG_BUSWIDTH		0x0000001c
#define  PLL_TX_CFG_BUSWIDTH_SHIFT	2
#define  PLL_TX_CFG_ENTEST		0x00000002
#define  PLL_TX_CFG_ENTX		0x00000001

#define ESR2_TI_PLL_TX_STS_L(CHAN)	(ESR2_BASE + 0x102 + (CHAN) * 4)
#define ESR2_TI_PLL_TX_STS_H(CHAN)	(ESR2_BASE + 0x103 + (CHAN) * 4)
#define  PLL_TX_STS_RDTCTIP		0x00000002
#define  PLL_TX_STS_TESTFAIL		0x00000001

#define ESR2_TI_PLL_RX_CFG_L(CHAN)	(ESR2_BASE + 0x120 + (CHAN) * 4)
#define ESR2_TI_PLL_RX_CFG_H(CHAN)	(ESR2_BASE + 0x121 + (CHAN) * 4)
#define  PLL_RX_CFG_BSINRXN		0x02000000
#define  PLL_RX_CFG_BSINRXP		0x01000000
#define  PLL_RX_CFG_EQ_MAX_LF		0x00000000
#define  PLL_RX_CFG_EQ_LP_ADAPTIVE	0x00080000
#define  PLL_RX_CFG_EQ_LP_1084MHZ	0x00400000
#define  PLL_RX_CFG_EQ_LP_805MHZ	0x00480000
#define  PLL_RX_CFG_EQ_LP_573MHZ	0x00500000
#define  PLL_RX_CFG_EQ_LP_402MHZ	0x00580000
#define  PLL_RX_CFG_EQ_LP_304MHZ	0x00600000
#define  PLL_RX_CFG_EQ_LP_216MHZ	0x00680000
#define  PLL_RX_CFG_EQ_LP_156MHZ	0x00700000
#define  PLL_RX_CFG_EQ_LP_135MHZ	0x00780000
#define  PLL_RX_CFG_EQ_SHIFT		19
#define  PLL_RX_CFG_CDR			0x00070000
#define  PLL_RX_CFG_CDR_SHIFT		16
#define  PLL_RX_CFG_LOS_DIS		0x00000000
#define  PLL_RX_CFG_LOS_HTHRESH		0x00004000
#define  PLL_RX_CFG_LOS_LTHRESH		0x00008000
#define  PLL_RX_CFG_ALIGN_DIS		0x00000000
#define  PLL_RX_CFG_ALIGN_ENA		0x00001000
#define  PLL_RX_CFG_ALIGN_JOG		0x00002000
#define  PLL_RX_CFG_TERM_VDDT		0x00000000
#define  PLL_RX_CFG_TERM_0P8VDDT	0x00000100
#define  PLL_RX_CFG_TERM_FLOAT		0x00000300
#define  PLL_RX_CFG_INVPAIR		0x00000080
#define  PLL_RX_CFG_RATE		0x00000060
#define  PLL_RX_CFG_RATE_SHIFT		5
#define  PLL_RX_CFG_BUSWIDTH		0x0000001c
#define  PLL_RX_CFG_BUSWIDTH_SHIFT	2
#define  PLL_RX_CFG_ENTEST		0x00000002
#define  PLL_RX_CFG_ENRX		0x00000001

#define ESR2_TI_PLL_RX_STS_L(CHAN)	(ESR2_BASE + 0x122 + (CHAN) * 4)
#define ESR2_TI_PLL_RX_STS_H(CHAN)	(ESR2_BASE + 0x123 + (CHAN) * 4)
#define  PLL_RX_STS_CRCIDTCT		0x00000200
#define  PLL_RX_STS_CWDTCT		0x00000100
#define  PLL_RX_STS_BSRXN		0x00000020
#define  PLL_RX_STS_BSRXP		0x00000010
#define  PLL_RX_STS_LOSDTCT		0x00000008
#define  PLL_RX_STS_ODDCG		0x00000004
#define  PLL_RX_STS_SYNC		0x00000002
#define  PLL_RX_STS_TESTFAIL		0x00000001

#define ENET_VLAN_TBL(IDX)		(FZC_FFLP + 0x00000UL + (IDX) * 8UL)
#define  ENET_VLAN_TBL_PARITY1		0x0000000000020000ULL
#define  ENET_VLAN_TBL_PARITY0		0x0000000000010000ULL
#define  ENET_VLAN_TBL_VPR		0x0000000000000008ULL
#define  ENET_VLAN_TBL_VLANRDCTBLN	0x0000000000000007ULL
#define  ENET_VLAN_TBL_SHIFT(PORT)	((PORT) * 4)

#define ENET_VLAN_TBL_NUM_ENTRIES	4096

#define FFLP_VLAN_PAR_ERR		(FZC_FFLP + 0x0800UL)
#define  FFLP_VLAN_PAR_ERR_ERR		0x0000000080000000ULL
#define  FFLP_VLAN_PAR_ERR_M_ERR	0x0000000040000000ULL
#define  FFLP_VLAN_PAR_ERR_ADDR		0x000000003ffc0000ULL
#define  FFLP_VLAN_PAR_ERR_DATA		0x000000000003ffffULL

#define L2_CLS(IDX)			(FZC_FFLP + 0x20000UL + (IDX) * 8UL)
#define  L2_CLS_VLD			0x0000000000010000ULL
#define  L2_CLS_ETYPE			0x000000000000ffffULL
#define  L2_CLS_ETYPE_SHIFT		0

#define L3_CLS(IDX)			(FZC_FFLP + 0x20010UL + (IDX) * 8UL)
#define  L3_CLS_VALID			0x0000000002000000ULL
#define  L3_CLS_IPVER			0x0000000001000000ULL
#define  L3_CLS_PID			0x0000000000ff0000ULL
#define  L3_CLS_PID_SHIFT		16
#define  L3_CLS_TOSMASK			0x000000000000ff00ULL
#define  L3_CLS_TOSMASK_SHIFT		8
#define  L3_CLS_TOS			0x00000000000000ffULL
#define  L3_CLS_TOS_SHIFT		0

#define TCAM_KEY(IDX)			(FZC_FFLP + 0x20030UL + (IDX) * 8UL)
#define  TCAM_KEY_DISC			0x0000000000000008ULL
#define  TCAM_KEY_TSEL			0x0000000000000004ULL
#define  TCAM_KEY_IPADDR		0x0000000000000001ULL

#define TCAM_KEY_0			(FZC_FFLP + 0x20090UL)
#define  TCAM_KEY_0_KEY			0x00000000000000ffULL /* bits 192-199 */

#define TCAM_KEY_1			(FZC_FFLP + 0x20098UL)
#define  TCAM_KEY_1_KEY			0xffffffffffffffffULL /* bits 128-191 */

#define TCAM_KEY_2			(FZC_FFLP + 0x200a0UL)
#define  TCAM_KEY_2_KEY			0xffffffffffffffffULL /* bits 64-127 */

#define TCAM_KEY_3			(FZC_FFLP + 0x200a8UL)
#define  TCAM_KEY_3_KEY			0xffffffffffffffffULL /* bits 0-63 */

#define TCAM_KEY_MASK_0			(FZC_FFLP + 0x200b0UL)
#define  TCAM_KEY_MASK_0_KEY_SEL	0x00000000000000ffULL /* bits 192-199 */

#define TCAM_KEY_MASK_1			(FZC_FFLP + 0x200b8UL)
#define  TCAM_KEY_MASK_1_KEY_SEL	0xffffffffffffffffULL /* bits 128-191 */

#define TCAM_KEY_MASK_2			(FZC_FFLP + 0x200c0UL)
#define  TCAM_KEY_MASK_2_KEY_SEL	0xffffffffffffffffULL /* bits 64-127 */

#define TCAM_KEY_MASK_3			(FZC_FFLP + 0x200c8UL)
#define  TCAM_KEY_MASK_3_KEY_SEL	0xffffffffffffffffULL /* bits 0-63 */

#define TCAM_CTL			(FZC_FFLP + 0x200d0UL)
#define  TCAM_CTL_RWC			0x00000000001c0000ULL
#define  TCAM_CTL_RWC_TCAM_WRITE	0x0000000000000000ULL
#define  TCAM_CTL_RWC_TCAM_READ		0x0000000000040000ULL
#define  TCAM_CTL_RWC_TCAM_COMPARE	0x0000000000080000ULL
#define  TCAM_CTL_RWC_RAM_WRITE		0x0000000000100000ULL
#define  TCAM_CTL_RWC_RAM_READ		0x0000000000140000ULL
#define  TCAM_CTL_STAT			0x0000000000020000ULL
#define  TCAM_CTL_MATCH			0x0000000000010000ULL
#define  TCAM_CTL_LOC			0x00000000000003ffULL

#define TCAM_ERR			(FZC_FFLP + 0x200d8UL)
#define  TCAM_ERR_ERR			0x0000000080000000ULL
#define  TCAM_ERR_P_ECC			0x0000000040000000ULL
#define  TCAM_ERR_MULT			0x0000000020000000ULL
#define  TCAM_ERR_ADDR			0x0000000000ff0000ULL
#define  TCAM_ERR_SYNDROME		0x000000000000ffffULL

#define HASH_LOOKUP_ERR_LOG1		(FZC_FFLP + 0x200e0UL)
#define  HASH_LOOKUP_ERR_LOG1_ERR	0x0000000000000008ULL
#define  HASH_LOOKUP_ERR_LOG1_MULT_LK	0x0000000000000004ULL
#define  HASH_LOOKUP_ERR_LOG1_CU	0x0000000000000002ULL
#define  HASH_LOOKUP_ERR_LOG1_MULT_BIT	0x0000000000000001ULL

#define HASH_LOOKUP_ERR_LOG2		(FZC_FFLP + 0x200e8UL)
#define  HASH_LOOKUP_ERR_LOG2_H1	0x000000007ffff800ULL
#define  HASH_LOOKUP_ERR_LOG2_SUBAREA	0x0000000000000700ULL
#define  HASH_LOOKUP_ERR_LOG2_SYNDROME	0x00000000000000ffULL

#define FFLP_CFG_1			(FZC_FFLP + 0x20100UL)
#define  FFLP_CFG_1_TCAM_DIS		0x0000000004000000ULL
#define  FFLP_CFG_1_PIO_DBG_SEL		0x0000000003800000ULL
#define  FFLP_CFG_1_PIO_FIO_RST		0x0000000000400000ULL
#define  FFLP_CFG_1_PIO_FIO_LAT		0x0000000000300000ULL
#define  FFLP_CFG_1_CAMLAT		0x00000000000f0000ULL
#define  FFLP_CFG_1_CAMLAT_SHIFT	16
#define  FFLP_CFG_1_CAMRATIO		0x000000000000f000ULL
#define  FFLP_CFG_1_CAMRATIO_SHIFT	12
#define  FFLP_CFG_1_FCRAMRATIO		0x0000000000000f00ULL
#define  FFLP_CFG_1_FCRAMRATIO_SHIFT	8
#define  FFLP_CFG_1_FCRAMOUTDR_MASK	0x00000000000000f0ULL
#define  FFLP_CFG_1_FCRAMOUTDR_NORMAL	0x0000000000000000ULL
#define  FFLP_CFG_1_FCRAMOUTDR_STRONG	0x0000000000000050ULL
#define  FFLP_CFG_1_FCRAMOUTDR_WEAK	0x00000000000000a0ULL
#define  FFLP_CFG_1_FCRAMQS		0x0000000000000008ULL
#define  FFLP_CFG_1_ERRORDIS		0x0000000000000004ULL
#define  FFLP_CFG_1_FFLPINITDONE	0x0000000000000002ULL
#define  FFLP_CFG_1_LLCSNAP		0x0000000000000001ULL

#define DEFAULT_FCRAMRATIO		10

#define DEFAULT_TCAM_LATENCY		4
#define DEFAULT_TCAM_ACCESS_RATIO	10

#define TCP_CFLAG_MSK			(FZC_FFLP + 0x20108UL)
#define  TCP_CFLAG_MSK_MASK		0x0000000000000fffULL

#define FCRAM_REF_TMR			(FZC_FFLP + 0x20110UL)
#define  FCRAM_REF_TMR_MAX		0x00000000ffff0000ULL
#define  FCRAM_REF_TMR_MAX_SHIFT	16
#define  FCRAM_REF_TMR_MIN		0x000000000000ffffULL
#define  FCRAM_REF_TMR_MIN_SHIFT	0

#define DEFAULT_FCRAM_REFRESH_MAX	512
#define DEFAULT_FCRAM_REFRESH_MIN	512

#define FCRAM_FIO_ADDR			(FZC_FFLP + 0x20118UL)
#define  FCRAM_FIO_ADDR_ADDR		0x00000000000000ffULL

#define FCRAM_FIO_DAT			(FZC_FFLP + 0x20120UL)
#define  FCRAM_FIO_DAT_DATA		0x000000000000ffffULL

#define FCRAM_ERR_TST0			(FZC_FFLP + 0x20128UL)
#define  FCRAM_ERR_TST0_SYND		0x00000000000000ffULL

#define FCRAM_ERR_TST1			(FZC_FFLP + 0x20130UL)
#define  FCRAM_ERR_TST1_DAT		0x00000000ffffffffULL

#define FCRAM_ERR_TST2			(FZC_FFLP + 0x20138UL)
#define  FCRAM_ERR_TST2_DAT		0x00000000ffffffffULL

#define FFLP_ERR_MASK			(FZC_FFLP + 0x20140UL)
#define  FFLP_ERR_MASK_HSH_TBL_DAT	0x00000000000007f8ULL
#define  FFLP_ERR_MASK_HSH_TBL_LKUP	0x0000000000000004ULL
#define  FFLP_ERR_MASK_TCAM		0x0000000000000002ULL
#define  FFLP_ERR_MASK_VLAN		0x0000000000000001ULL

#define FFLP_DBG_TRAIN_VCT		(FZC_FFLP + 0x20148UL)
#define  FFLP_DBG_TRAIN_VCT_VECTOR	0x00000000ffffffffULL

#define FCRAM_PHY_RD_LAT		(FZC_FFLP + 0x20150UL)
#define  FCRAM_PHY_RD_LAT_LAT		0x00000000000000ffULL

/* Ethernet TCAM format */
#define TCAM_ETHKEY0_RESV1		0xffffffffffffff00ULL
#define TCAM_ETHKEY0_CLASS_CODE		0x00000000000000f8ULL
#define TCAM_ETHKEY0_CLASS_CODE_SHIFT	3
#define TCAM_ETHKEY0_RESV2		0x0000000000000007ULL
#define TCAM_ETHKEY1_FRAME_BYTE0_7(NUM)	(0xff << ((7 - NUM) * 8))
#define TCAM_ETHKEY2_FRAME_BYTE8	0xff00000000000000ULL
#define TCAM_ETHKEY2_FRAME_BYTE8_SHIFT	56
#define TCAM_ETHKEY2_FRAME_BYTE9	0x00ff000000000000ULL
#define TCAM_ETHKEY2_FRAME_BYTE9_SHIFT	48
#define TCAM_ETHKEY2_FRAME_BYTE10	0x0000ff0000000000ULL
#define TCAM_ETHKEY2_FRAME_BYTE10_SHIFT	40
#define TCAM_ETHKEY2_FRAME_RESV		0x000000ffffffffffULL
#define TCAM_ETHKEY3_FRAME_RESV		0xffffffffffffffffULL