niu.h

linux 内核源代码

#define  XPCS_DIAG_VENDOR2_EBUF_SM	0x00000000000001feULL
#define  XPCS_DIAG_VENDOR2_RCV_SM	0x0000000000000001ULL

#define XPCS_MASK1			(FZC_MAC + 0x00060UL)
#define  XPCS_MASK1_FAULT_MASK		0x0000000000000080ULL
#define  XPCS_MASK1_RXALIGN_STAT_MSK	0x0000000000000004ULL

#define XPCS_PKT_COUNT			(FZC_MAC + 0x00068UL)
#define  XPCS_PKT_COUNT_TX		0x00000000ffff0000ULL
#define  XPCS_PKT_COUNT_RX		0x000000000000ffffULL

#define XPCS_TX_SM			(FZC_MAC + 0x00070UL)
#define  XPCS_TX_SM_VAL			0x000000000000000fULL

#define XPCS_DESKEW_ERR_CNT		(FZC_MAC + 0x00078UL)
#define  XPCS_DESKEW_ERR_CNT_VAL	0x00000000000000ffULL

#define XPCS_SYMERR_CNT01		(FZC_MAC + 0x00080UL)
#define  XPCS_SYMERR_CNT01_LANE1	0x00000000ffff0000ULL
#define  XPCS_SYMERR_CNT01_LANE0	0x000000000000ffffULL

#define XPCS_SYMERR_CNT23		(FZC_MAC + 0x00088UL)
#define  XPCS_SYMERR_CNT23_LANE3	0x00000000ffff0000ULL
#define  XPCS_SYMERR_CNT23_LANE2	0x000000000000ffffULL

#define XPCS_TRAINING_VECTOR		(FZC_MAC + 0x00090UL)
#define  XPCS_TRAINING_VECTOR_VAL	0x00000000ffffffffULL

/* PCS registers, offset from np->regs + np->pcs_off  */

#define PCS_MII_CTL			(FZC_MAC + 0x00000UL)
#define  PCS_MII_CTL_RST		0x0000000000008000ULL
#define  PCS_MII_CTL_10_100_SPEED	0x0000000000002000ULL
#define  PCS_MII_AUTONEG_EN		0x0000000000001000ULL
#define  PCS_MII_PWR_DOWN		0x0000000000000800ULL
#define  PCS_MII_ISOLATE		0x0000000000000400ULL
#define  PCS_MII_AUTONEG_RESTART	0x0000000000000200ULL
#define  PCS_MII_DUPLEX			0x0000000000000100ULL
#define  PCS_MII_COLL_TEST		0x0000000000000080ULL
#define  PCS_MII_1000MB_SPEED		0x0000000000000040ULL

#define PCS_MII_STAT			(FZC_MAC + 0x00008UL)
#define  PCS_MII_STAT_EXT_STATUS	0x0000000000000100ULL
#define  PCS_MII_STAT_AUTONEG_DONE	0x0000000000000020ULL
#define  PCS_MII_STAT_REMOTE_FAULT	0x0000000000000010ULL
#define  PCS_MII_STAT_AUTONEG_ABLE	0x0000000000000008ULL
#define  PCS_MII_STAT_LINK_STATUS	0x0000000000000004ULL
#define  PCS_MII_STAT_JABBER_DET	0x0000000000000002ULL
#define  PCS_MII_STAT_EXT_CAP		0x0000000000000001ULL

#define PCS_MII_ADV			(FZC_MAC + 0x00010UL)
#define  PCS_MII_ADV_NEXT_PAGE		0x0000000000008000ULL
#define  PCS_MII_ADV_ACK		0x0000000000004000ULL
#define  PCS_MII_ADV_REMOTE_FAULT	0x0000000000003000ULL
#define  PCS_MII_ADV_ASM_DIR		0x0000000000000100ULL
#define  PCS_MII_ADV_PAUSE		0x0000000000000080ULL
#define  PCS_MII_ADV_HALF_DUPLEX	0x0000000000000040ULL
#define  PCS_MII_ADV_FULL_DUPLEX	0x0000000000000020ULL

#define PCS_MII_PARTNER			(FZC_MAC + 0x00018UL)
#define  PCS_MII_PARTNER_NEXT_PAGE	0x0000000000008000ULL
#define  PCS_MII_PARTNER_ACK		0x0000000000004000ULL
#define  PCS_MII_PARTNER_REMOTE_FAULT	0x0000000000002000ULL
#define  PCS_MII_PARTNER_PAUSE		0x0000000000000180ULL
#define  PCS_MII_PARTNER_HALF_DUPLEX	0x0000000000000040ULL
#define  PCS_MII_PARTNER_FULL_DUPLEX	0x0000000000000020ULL

#define PCS_CONF			(FZC_MAC + 0x00020UL)
#define  PCS_CONF_MASK			0x0000000000000040ULL
#define  PCS_CONF_10MS_TMR_OVERRIDE	0x0000000000000020ULL
#define  PCS_CONF_JITTER_STUDY		0x0000000000000018ULL
#define  PCS_CONF_SIGDET_ACTIVE_LOW	0x0000000000000004ULL
#define  PCS_CONF_SIGDET_OVERRIDE	0x0000000000000002ULL
#define  PCS_CONF_ENABLE		0x0000000000000001ULL

#define PCS_STATE			(FZC_MAC + 0x00028UL)
#define  PCS_STATE_D_PARTNER_FAIL	0x0000000020000000ULL
#define  PCS_STATE_D_WAIT_C_CODES_ACK	0x0000000010000000ULL
#define  PCS_STATE_D_SYNC_LOSS		0x0000000008000000ULL
#define  PCS_STATE_D_NO_GOOD_C_CODES	0x0000000004000000ULL
#define  PCS_STATE_D_SERDES		0x0000000002000000ULL
#define  PCS_STATE_D_BREAKLINK_C_CODES	0x0000000001000000ULL
#define  PCS_STATE_L_SIGDET		0x0000000000400000ULL
#define  PCS_STATE_L_SYNC_LOSS		0x0000000000200000ULL
#define  PCS_STATE_L_C_CODES		0x0000000000100000ULL
#define  PCS_STATE_LINK_CFG_STATE	0x000000000001e000ULL
#define  PCS_STATE_SEQ_DET_STATE	0x0000000000001800ULL
#define  PCS_STATE_WORD_SYNC_STATE	0x0000000000000700ULL
#define  PCS_STATE_NO_IDLE		0x000000000000000fULL

#define PCS_INTERRUPT			(FZC_MAC + 0x00030UL)
#define  PCS_INTERRUPT_LSTATUS		0x0000000000000004ULL

#define PCS_DPATH_MODE			(FZC_MAC + 0x000a0UL)
#define  PCS_DPATH_MODE_PCS		0x0000000000000000ULL
#define  PCS_DPATH_MODE_MII		0x0000000000000002ULL
#define  PCS_DPATH_MODE_LINKUP_F_ENAB	0x0000000000000001ULL

#define PCS_PKT_CNT			(FZC_MAC + 0x000c0UL)
#define  PCS_PKT_CNT_RX			0x0000000007ff0000ULL
#define  PCS_PKT_CNT_TX			0x00000000000007ffULL

#define MIF_BB_MDC			(FZC_MAC + 0x16000UL)
#define  MIF_BB_MDC_CLK			0x0000000000000001ULL

#define MIF_BB_MDO			(FZC_MAC + 0x16008UL)
#define  MIF_BB_MDO_DAT			0x0000000000000001ULL

#define MIF_BB_MDO_EN			(FZC_MAC + 0x16010UL)
#define  MIF_BB_MDO_EN_VAL		0x0000000000000001ULL

#define MIF_FRAME_OUTPUT		(FZC_MAC + 0x16018UL)
#define  MIF_FRAME_OUTPUT_ST		0x00000000c0000000ULL
#define  MIF_FRAME_OUTPUT_ST_SHIFT	30
#define  MIF_FRAME_OUTPUT_OP_ADDR	0x0000000000000000ULL
#define  MIF_FRAME_OUTPUT_OP_WRITE	0x0000000010000000ULL
#define  MIF_FRAME_OUTPUT_OP_READ_INC	0x0000000020000000ULL
#define  MIF_FRAME_OUTPUT_OP_READ	0x0000000030000000ULL
#define  MIF_FRAME_OUTPUT_OP_SHIFT	28
#define  MIF_FRAME_OUTPUT_PORT		0x000000000f800000ULL
#define  MIF_FRAME_OUTPUT_PORT_SHIFT	23
#define  MIF_FRAME_OUTPUT_REG		0x00000000007c0000ULL
#define  MIF_FRAME_OUTPUT_REG_SHIFT	18
#define  MIF_FRAME_OUTPUT_TA		0x0000000000030000ULL
#define  MIF_FRAME_OUTPUT_TA_SHIFT	16
#define  MIF_FRAME_OUTPUT_DATA		0x000000000000ffffULL
#define  MIF_FRAME_OUTPUT_DATA_SHIFT	0

#define MDIO_ADDR_OP(port, dev, reg) \
	((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
	 MIF_FRAME_OUTPUT_OP_ADDR | \
	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
	 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
	 (reg << MIF_FRAME_OUTPUT_DATA_SHIFT))

#define MDIO_READ_OP(port, dev) \
	((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
	 MIF_FRAME_OUTPUT_OP_READ | \
	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
	 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))

#define MDIO_WRITE_OP(port, dev, data) \
	((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
	 MIF_FRAME_OUTPUT_OP_WRITE | \
	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
	 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
	 (data << MIF_FRAME_OUTPUT_DATA_SHIFT))

#define MII_READ_OP(port, reg) \
	((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
	 (2 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
	 (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))

#define MII_WRITE_OP(port, reg, data) \
	((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
	 (1 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
	 (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
	 (data << MIF_FRAME_OUTPUT_DATA_SHIFT))

#define MIF_CONFIG			(FZC_MAC + 0x16020UL)
#define  MIF_CONFIG_ATCA_GE		0x0000000000010000ULL
#define  MIF_CONFIG_INDIRECT_MODE	0x0000000000008000ULL
#define  MIF_CONFIG_POLL_PRT_PHYADDR	0x0000000000003c00ULL
#define  MIF_CONFIG_POLL_DEV_REG_ADDR	0x00000000000003e0ULL
#define  MIF_CONFIG_BB_MODE		0x0000000000000010ULL
#define  MIF_CONFIG_POLL_EN		0x0000000000000008ULL
#define  MIF_CONFIG_BB_SER_SEL		0x0000000000000006ULL
#define  MIF_CONFIG_MANUAL_MODE		0x0000000000000001ULL

#define MIF_POLL_STATUS			(FZC_MAC + 0x16028UL)
#define  MIF_POLL_STATUS_DATA		0x00000000ffff0000ULL
#define  MIF_POLL_STATUS_STAT		0x000000000000ffffULL

#define MIF_POLL_MASK			(FZC_MAC + 0x16030UL)
#define  MIF_POLL_MASK_VAL		0x000000000000ffffULL

#define MIF_SM				(FZC_MAC + 0x16038UL)
#define  MIF_SM_PORT_ADDR		0x00000000001f0000ULL
#define  MIF_SM_MDI_1			0x0000000000004000ULL
#define  MIF_SM_MDI_0			0x0000000000002400ULL
#define  MIF_SM_MDCLK			0x0000000000001000ULL
#define  MIF_SM_MDO_EN			0x0000000000000800ULL
#define  MIF_SM_MDO			0x0000000000000400ULL
#define  MIF_SM_MDI			0x0000000000000200ULL
#define  MIF_SM_CTL			0x00000000000001c0ULL
#define  MIF_SM_EX			0x000000000000003fULL

#define MIF_STATUS			(FZC_MAC + 0x16040UL)
#define  MIF_STATUS_MDINT1		0x0000000000000020ULL
#define  MIF_STATUS_MDINT0		0x0000000000000010ULL

#define MIF_MASK			(FZC_MAC + 0x16048UL)
#define  MIF_MASK_MDINT1		0x0000000000000020ULL
#define  MIF_MASK_MDINT0		0x0000000000000010ULL
#define  MIF_MASK_PEU_ERR		0x0000000000000008ULL
#define  MIF_MASK_YC			0x0000000000000004ULL
#define  MIF_MASK_XGE_ERR0		0x0000000000000002ULL
#define  MIF_MASK_MIF_INIT_DONE		0x0000000000000001ULL

#define ENET_SERDES_RESET		(FZC_MAC + 0x14000UL)
#define  ENET_SERDES_RESET_1		0x0000000000000002ULL
#define  ENET_SERDES_RESET_0		0x0000000000000001ULL

#define ENET_SERDES_CFG			(FZC_MAC + 0x14008UL)
#define  ENET_SERDES_BE_LOOPBACK	0x0000000000000002ULL
#define  ENET_SERDES_CFG_FORCE_RDY	0x0000000000000001ULL

#define ENET_SERDES_0_PLL_CFG		(FZC_MAC + 0x14010UL)
#define  ENET_SERDES_PLL_FBDIV0		0x0000000000000001ULL
#define  ENET_SERDES_PLL_FBDIV1		0x0000000000000002ULL
#define  ENET_SERDES_PLL_FBDIV2		0x0000000000000004ULL
#define  ENET_SERDES_PLL_HRATE0		0x0000000000000008ULL
#define  ENET_SERDES_PLL_HRATE1		0x0000000000000010ULL
#define  ENET_SERDES_PLL_HRATE2		0x0000000000000020ULL
#define  ENET_SERDES_PLL_HRATE3		0x0000000000000040ULL

#define ENET_SERDES_0_CTRL_CFG		(FZC_MAC + 0x14018UL)
#define  ENET_SERDES_CTRL_SDET_0	0x0000000000000001ULL
#define  ENET_SERDES_CTRL_SDET_1	0x0000000000000002ULL
#define  ENET_SERDES_CTRL_SDET_2	0x0000000000000004ULL
#define  ENET_SERDES_CTRL_SDET_3	0x0000000000000008ULL
#define  ENET_SERDES_CTRL_EMPH_0	0x0000000000000070ULL
#define  ENET_SERDES_CTRL_EMPH_0_SHIFT	4
#define  ENET_SERDES_CTRL_EMPH_1	0x0000000000000380ULL
#define  ENET_SERDES_CTRL_EMPH_1_SHIFT	7
#define  ENET_SERDES_CTRL_EMPH_2	0x0000000000001c00ULL
#define  ENET_SERDES_CTRL_EMPH_2_SHIFT	10
#define  ENET_SERDES_CTRL_EMPH_3	0x000000000000e000ULL
#define  ENET_SERDES_CTRL_EMPH_3_SHIFT	13
#define  ENET_SERDES_CTRL_LADJ_0	0x0000000000070000ULL
#define  ENET_SERDES_CTRL_LADJ_0_SHIFT	16
#define  ENET_SERDES_CTRL_LADJ_1	0x0000000000380000ULL
#define  ENET_SERDES_CTRL_LADJ_1_SHIFT	19
#define  ENET_SERDES_CTRL_LADJ_2	0x0000000001c00000ULL
#define  ENET_SERDES_CTRL_LADJ_2_SHIFT	22
#define  ENET_SERDES_CTRL_LADJ_3	0x000000000e000000ULL
#define  ENET_SERDES_CTRL_LADJ_3_SHIFT	25
#define  ENET_SERDES_CTRL_RXITERM_0	0x0000000010000000ULL
#define  ENET_SERDES_CTRL_RXITERM_1	0x0000000020000000ULL
#define  ENET_SERDES_CTRL_RXITERM_2	0x0000000040000000ULL
#define  ENET_SERDES_CTRL_RXITERM_3	0x0000000080000000ULL

#define ENET_SERDES_0_TEST_CFG		(FZC_MAC + 0x14020UL)
#define  ENET_SERDES_TEST_MD_0		0x0000000000000003ULL
#define  ENET_SERDES_TEST_MD_0_SHIFT	0
#define  ENET_SERDES_TEST_MD_1		0x000000000000000cULL
#define  ENET_SERDES_TEST_MD_1_SHIFT	2
#define  ENET_SERDES_TEST_MD_2		0x0000000000000030ULL
#define  ENET_SERDES_TEST_MD_2_SHIFT	4
#define  ENET_SERDES_TEST_MD_3		0x00000000000000c0ULL
#define  ENET_SERDES_TEST_MD_3_SHIFT	6

#define ENET_TEST_MD_NO_LOOPBACK	0x0
#define ENET_TEST_MD_EWRAP		0x1
#define ENET_TEST_MD_PAD_LOOPBACK	0x2
#define ENET_TEST_MD_REV_LOOPBACK	0x3

#define ENET_SERDES_1_PLL_CFG		(FZC_MAC + 0x14028UL)
#define ENET_SERDES_1_CTRL_CFG		(FZC_MAC + 0x14030UL)
#define ENET_SERDES_1_TEST_CFG		(FZC_MAC + 0x14038UL)

#define ENET_RGMII_CFG_REG		(FZC_MAC + 0x14040UL)

#define ESR_INT_SIGNALS			(FZC_MAC + 0x14800UL)
#define  ESR_INT_SIGNALS_ALL		0x00000000ffffffffULL
#define  ESR_INT_SIGNALS_P0_BITS	0x0000000033e0000fULL
#define  ESR_INT_SIGNALS_P1_BITS	0x000000000c1f00f0ULL
#define  ESR_INT_SRDY0_P0		0x0000000020000000ULL
#define  ESR_INT_DET0_P0		0x0000000010000000ULL
#define  ESR_INT_SRDY0_P1		0x0000000008000000ULL
#define  ESR_INT_DET0_P1		0x0000000004000000ULL
#define  ESR_INT_XSRDY_P0		0x0000000002000000ULL
#define  ESR_INT_XDP_P0_CH3		0x0000000001000000ULL
#define  ESR_INT_XDP_P0_CH2		0x0000000000800000ULL
#define  ESR_INT_XDP_P0_CH1		0x0000000000400000ULL
#define  ESR_INT_XDP_P0_CH0		0x0000000000200000ULL
#define  ESR_INT_XSRDY_P1		0x0000000000100000ULL
#define  ESR_INT_XDP_P1_CH3		0x0000000000080000ULL
#define  ESR_INT_XDP_P1_CH2		0x0000000000040000ULL
#define  ESR_INT_XDP_P1_CH1		0x0000000000020000ULL
#define  ESR_INT_XDP_P1_CH0		0x0000000000010000ULL
#define  ESR_INT_SLOSS_P1_CH3		0x0000000000000080ULL
#define  ESR_INT_SLOSS_P1_CH2		0x0000000000000040ULL
#define  ESR_INT_SLOSS_P1_CH1		0x0000000000000020ULL
#define  ESR_INT_SLOSS_P1_CH0		0x0000000000000010ULL
#define  ESR_INT_SLOSS_P0_CH3		0x0000000000000008ULL
#define  ESR_INT_SLOSS_P0_CH2		0x0000000000000004ULL
#define  ESR_INT_SLOSS_P0_CH1		0x0000000000000002ULL
#define  ESR_INT_SLOSS_P0_CH0		0x0000000000000001ULL

#define ESR_DEBUG_SEL			(FZC_MAC + 0x14808UL)
#define  ESR_DEBUG_SEL_VAL		0x000000000000003fULL

/* SerDes registers behind MIF */
#define NIU_ESR_DEV_ADDR		0x1e
#define ESR_BASE			0x0000

#define ESR_RXTX_COMM_CTRL_L		(ESR_BASE + 0x0000)
#define ESR_RXTX_COMM_CTRL_H		(ESR_BASE + 0x0001)

#define ESR_RXTX_RESET_CTRL_L		(ESR_BASE + 0x0002)
#define ESR_RXTX_RESET_CTRL_H		(ESR_BASE + 0x0003)

#define ESR_RX_POWER_CTRL_L		(ESR_BASE + 0x0004)
#define ESR_RX_POWER_CTRL_H		(ESR_BASE + 0x0005)

#define ESR_TX_POWER_CTRL_L		(ESR_BASE + 0x0006)
#define ESR_TX_POWER_CTRL_H		(ESR_BASE + 0x0007)

#define ESR_MISC_POWER_CTRL_L		(ESR_BASE + 0x0008)
#define ESR_MISC_POWER_CTRL_H		(ESR_BASE + 0x0009)

#define ESR_RXTX_CTRL_L(CHAN)		(ESR_BASE + 0x0080 + (CHAN) * 0x10)
#define ESR_RXTX_CTRL_H(CHAN)		(ESR_BASE + 0x0081 + (CHAN) * 0x10)
#define  ESR_RXTX_CTRL_BIASCNTL		0x80000000
#define  ESR_RXTX_CTRL_RESV1		0x7c000000
#define  ESR_RXTX_CTRL_TDENFIFO		0x02000000
#define  ESR_RXTX_CTRL_TDWS20		0x01000000
#define  ESR_RXTX_CTRL_VMUXLO		0x00c00000
#define  ESR_RXTX_CTRL_VMUXLO_SHIFT	22
#define  ESR_RXTX_CTRL_VPULSELO		0x00300000
#define  ESR_RXTX_CTRL_VPULSELO_SHIFT	20