niu.h

linux 内核源代码

#define XMAC_HASH_TBL(NUM)		(0x00840UL + (NUM) * 0x8UL)
#define XMAC_HASH_TBL_VAL		0x000000000000ffffULL

#define XMAC_NUM_HOST_INFO		20

#define XMAC_HOST_INFO(NUM)		(0x00900UL + (NUM) * 0x8UL)

#define XMAC_PA_DATA0			0x00b80UL
#define XMAC_PA_DATA0_VAL		0x00000000ffffffffULL

#define XMAC_PA_DATA1			0x00b88UL
#define XMAC_PA_DATA1_VAL		0x00000000ffffffffULL

#define XMAC_DEBUG_SEL			0x00b90UL
#define  XMAC_DEBUG_SEL_XMAC		0x0000000000000078ULL
#define  XMAC_DEBUG_SEL_MAC		0x0000000000000007ULL

#define XMAC_TRAIN_VEC			0x00b98UL
#define  XMAC_TRAIN_VEC_VAL		0x00000000ffffffffULL

#define RXMAC_BT_CNT			0x00100UL
#define  RXMAC_BT_CNT_COUNT		0x00000000ffffffffULL

#define RXMAC_BC_FRM_CNT		0x00108UL
#define  RXMAC_BC_FRM_CNT_COUNT		0x00000000001fffffULL

#define RXMAC_MC_FRM_CNT		0x00110UL
#define  RXMAC_MC_FRM_CNT_COUNT		0x00000000001fffffULL

#define RXMAC_FRAG_CNT			0x00118UL
#define  RXMAC_FRAG_CNT_COUNT		0x00000000001fffffULL

#define RXMAC_HIST_CNT1			0x00120UL
#define  RXMAC_HIST_CNT1_COUNT		0x00000000001fffffULL

#define RXMAC_HIST_CNT2			0x00128UL
#define  RXMAC_HIST_CNT2_COUNT		0x00000000001fffffULL

#define RXMAC_HIST_CNT3			0x00130UL
#define  RXMAC_HIST_CNT3_COUNT		0x00000000000fffffULL

#define RXMAC_HIST_CNT4			0x00138UL
#define  RXMAC_HIST_CNT4_COUNT		0x000000000007ffffULL

#define RXMAC_HIST_CNT5			0x00140UL
#define  RXMAC_HIST_CNT5_COUNT		0x000000000003ffffULL

#define RXMAC_HIST_CNT6			0x00148UL
#define  RXMAC_HIST_CNT6_COUNT		0x000000000000ffffULL

#define RXMAC_MPSZER_CNT		0x00150UL
#define  RXMAC_MPSZER_CNT_COUNT		0x00000000000000ffULL

#define RXMAC_CRC_ER_CNT		0x00158UL
#define  RXMAC_CRC_ER_CNT_COUNT		0x00000000000000ffULL

#define RXMAC_CD_VIO_CNT		0x00160UL
#define  RXMAC_CD_VIO_CNT_COUNT		0x00000000000000ffULL

#define RXMAC_ALIGN_ERR_CNT		0x00168UL
#define  RXMAC_ALIGN_ERR_CNT_COUNT	0x00000000000000ffULL

#define TXMAC_FRM_CNT			0x00170UL
#define  TXMAC_FRM_CNT_COUNT		0x00000000ffffffffULL

#define TXMAC_BYTE_CNT			0x00178UL
#define  TXMAC_BYTE_CNT_COUNT		0x00000000ffffffffULL

#define LINK_FAULT_CNT			0x00180UL
#define  LINK_FAULT_CNT_COUNT		0x00000000000000ffULL

#define RXMAC_HIST_CNT7			0x00188UL
#define  RXMAC_HIST_CNT7_COUNT		0x0000000007ffffffULL

#define XMAC_SM_REG			0x001a8UL
#define  XMAC_SM_REG_STATE		0x00000000ffffffffULL

#define XMAC_INTER1			0x001b0UL
#define  XMAC_INTERN1_SIGNALS1		0x00000000ffffffffULL

#define XMAC_INTER2			0x001b8UL
#define  XMAC_INTERN2_SIGNALS2		0x00000000ffffffffULL

/* BMAC registers, offset from np->mac_regs  */

#define BTXMAC_SW_RST			0x00000UL
#define  BTXMAC_SW_RST_RESET		0x0000000000000001ULL

#define BRXMAC_SW_RST			0x00008UL
#define  BRXMAC_SW_RST_RESET		0x0000000000000001ULL

#define BMAC_SEND_PAUSE			0x00010UL
#define  BMAC_SEND_PAUSE_SEND		0x0000000000010000ULL
#define  BMAC_SEND_PAUSE_TIME		0x000000000000ffffULL

#define BTXMAC_STATUS			0x00020UL
#define  BTXMAC_STATUS_XMIT		0x0000000000000001ULL
#define  BTXMAC_STATUS_UNDERRUN		0x0000000000000002ULL
#define  BTXMAC_STATUS_MAX_PKT_ERR	0x0000000000000004ULL
#define  BTXMAC_STATUS_BYTE_CNT_EXP	0x0000000000000400ULL
#define  BTXMAC_STATUS_FRAME_CNT_EXP	0x0000000000000800ULL

#define BRXMAC_STATUS			0x00028UL
#define  BRXMAC_STATUS_RX_PKT		0x0000000000000001ULL
#define  BRXMAC_STATUS_OVERFLOW		0x0000000000000002ULL
#define  BRXMAC_STATUS_FRAME_CNT_EXP	0x0000000000000004ULL
#define  BRXMAC_STATUS_ALIGN_ERR_EXP	0x0000000000000008ULL
#define  BRXMAC_STATUS_CRC_ERR_EXP	0x0000000000000010ULL
#define  BRXMAC_STATUS_LEN_ERR_EXP	0x0000000000000020ULL

#define BMAC_CTRL_STATUS		0x00030UL
#define  BMAC_CTRL_STATUS_PAUSE_RECV	0x0000000000000001ULL
#define  BMAC_CTRL_STATUS_PAUSE		0x0000000000000002ULL
#define  BMAC_CTRL_STATUS_NOPAUSE	0x0000000000000004ULL
#define  BMAC_CTRL_STATUS_TIME		0x00000000ffff0000ULL
#define  BMAC_CTRL_STATUS_TIME_SHIFT	16

#define BTXMAC_STATUS_MASK		0x00040UL
#define BRXMAC_STATUS_MASK		0x00048UL
#define BMAC_CTRL_STATUS_MASK		0x00050UL

#define BTXMAC_CONFIG			0x00060UL
#define  BTXMAC_CONFIG_ENABLE		0x0000000000000001ULL
#define  BTXMAC_CONFIG_FCS_DISABLE	0x0000000000000002ULL

#define BRXMAC_CONFIG			0x00068UL
#define  BRXMAC_CONFIG_DISCARD_DIS	0x0000000000000080ULL
#define  BRXMAC_CONFIG_ADDR_FILT_EN	0x0000000000000040ULL
#define  BRXMAC_CONFIG_HASH_FILT_EN	0x0000000000000020ULL
#define  BRXMAC_CONFIG_PROMISC_GRP	0x0000000000000010ULL
#define  BRXMAC_CONFIG_PROMISC		0x0000000000000008ULL
#define  BRXMAC_CONFIG_STRIP_FCS	0x0000000000000004ULL
#define  BRXMAC_CONFIG_STRIP_PAD	0x0000000000000002ULL
#define  BRXMAC_CONFIG_ENABLE		0x0000000000000001ULL

#define BMAC_CTRL_CONFIG		0x00070UL
#define  BMAC_CTRL_CONFIG_TX_PAUSE_EN	0x0000000000000001ULL
#define  BMAC_CTRL_CONFIG_RX_PAUSE_EN	0x0000000000000002ULL
#define  BMAC_CTRL_CONFIG_PASS_CTRL	0x0000000000000004ULL

#define BMAC_XIF_CONFIG			0x00078UL
#define  BMAC_XIF_CONFIG_TX_OUTPUT_EN	0x0000000000000001ULL
#define  BMAC_XIF_CONFIG_MII_LOOPBACK	0x0000000000000002ULL
#define  BMAC_XIF_CONFIG_GMII_MODE	0x0000000000000008ULL
#define  BMAC_XIF_CONFIG_LINK_LED	0x0000000000000020ULL
#define  BMAC_XIF_CONFIG_LED_POLARITY	0x0000000000000040ULL
#define  BMAC_XIF_CONFIG_25MHZ_CLOCK	0x0000000000000080ULL

#define BMAC_MIN_FRAME			0x000a0UL
#define  BMAC_MIN_FRAME_VAL		0x00000000000003ffULL

#define BMAC_MAX_FRAME			0x000a8UL
#define  BMAC_MAX_FRAME_MAX_BURST	0x000000003fff0000ULL
#define  BMAC_MAX_FRAME_MAX_BURST_SHIFT	16
#define  BMAC_MAX_FRAME_MAX_FRAME	0x0000000000003fffULL
#define  BMAC_MAX_FRAME_MAX_FRAME_SHIFT	0

#define BMAC_PREAMBLE_SIZE		0x000b0UL
#define  BMAC_PREAMBLE_SIZE_VAL		0x00000000000003ffULL

#define BMAC_CTRL_TYPE			0x000c8UL

#define BMAC_ADDR0			0x00100UL
#define  BMAC_ADDR0_ADDR0		0x000000000000ffffULL

#define BMAC_ADDR1			0x00108UL
#define  BMAC_ADDR1_ADDR1		0x000000000000ffffULL

#define BMAC_ADDR2			0x00110UL
#define  BMAC_ADDR2_ADDR2		0x000000000000ffffULL

#define BMAC_NUM_ALT_ADDR		7

#define BMAC_ALT_ADDR0(NUM)		(0x00118UL + (NUM)*0x18UL)
#define  BMAC_ALT_ADDR0_ADDR0		0x000000000000ffffULL

#define BMAC_ALT_ADDR1(NUM)		(0x00120UL + (NUM)*0x18UL)
#define  BMAC_ALT_ADDR1_ADDR1		0x000000000000ffffULL

#define BMAC_ALT_ADDR2(NUM)		(0x00128UL + (NUM)*0x18UL)
#define  BMAC_ALT_ADDR2_ADDR2		0x000000000000ffffULL

#define BMAC_FC_ADDR0			0x00268UL
#define  BMAC_FC_ADDR0_ADDR0		0x000000000000ffffULL

#define BMAC_FC_ADDR1			0x00270UL
#define  BMAC_FC_ADDR1_ADDR1		0x000000000000ffffULL

#define BMAC_FC_ADDR2			0x00278UL
#define  BMAC_FC_ADDR2_ADDR2		0x000000000000ffffULL

#define BMAC_ADD_FILT0			0x00298UL
#define  BMAC_ADD_FILT0_FILT0		0x000000000000ffffULL

#define BMAC_ADD_FILT1			0x002a0UL
#define  BMAC_ADD_FILT1_FILT1		0x000000000000ffffULL

#define BMAC_ADD_FILT2			0x002a8UL
#define  BMAC_ADD_FILT2_FILT2		0x000000000000ffffULL

#define BMAC_ADD_FILT12_MASK		0x002b0UL
#define  BMAC_ADD_FILT12_MASK_VAL	0x00000000000000ffULL

#define BMAC_ADD_FILT00_MASK		0x002b8UL
#define  BMAC_ADD_FILT00_MASK_VAL	0x000000000000ffffULL

#define BMAC_HASH_TBL(NUM)		(0x002c0UL + (NUM) * 0x8UL)
#define BMAC_HASH_TBL_VAL		0x000000000000ffffULL

#define BRXMAC_FRAME_CNT		0x00370
#define  BRXMAC_FRAME_CNT_COUNT		0x000000000000ffffULL

#define BRXMAC_MAX_LEN_ERR_CNT		0x00378

#define BRXMAC_ALIGN_ERR_CNT		0x00380
#define  BRXMAC_ALIGN_ERR_CNT_COUNT	0x000000000000ffffULL

#define BRXMAC_CRC_ERR_CNT		0x00388
#define  BRXMAC_ALIGN_ERR_CNT_COUNT	0x000000000000ffffULL

#define BRXMAC_CODE_VIOL_ERR_CNT	0x00390
#define  BRXMAC_CODE_VIOL_ERR_CNT_COUNT	0x000000000000ffffULL

#define BMAC_STATE_MACHINE		0x003a0

#define BMAC_ADDR_CMPEN			0x003f8UL
#define  BMAC_ADDR_CMPEN_EN15		0x0000000000008000ULL
#define  BMAC_ADDR_CMPEN_EN14		0x0000000000004000ULL
#define  BMAC_ADDR_CMPEN_EN13		0x0000000000002000ULL
#define  BMAC_ADDR_CMPEN_EN12		0x0000000000001000ULL
#define  BMAC_ADDR_CMPEN_EN11		0x0000000000000800ULL
#define  BMAC_ADDR_CMPEN_EN10		0x0000000000000400ULL
#define  BMAC_ADDR_CMPEN_EN9		0x0000000000000200ULL
#define  BMAC_ADDR_CMPEN_EN8		0x0000000000000100ULL
#define  BMAC_ADDR_CMPEN_EN7		0x0000000000000080ULL
#define  BMAC_ADDR_CMPEN_EN6		0x0000000000000040ULL
#define  BMAC_ADDR_CMPEN_EN5		0x0000000000000020ULL
#define  BMAC_ADDR_CMPEN_EN4		0x0000000000000010ULL
#define  BMAC_ADDR_CMPEN_EN3		0x0000000000000008ULL
#define  BMAC_ADDR_CMPEN_EN2		0x0000000000000004ULL
#define  BMAC_ADDR_CMPEN_EN1		0x0000000000000002ULL
#define  BMAC_ADDR_CMPEN_EN0		0x0000000000000001ULL

#define BMAC_NUM_HOST_INFO		9

#define BMAC_HOST_INFO(NUM)		(0x00400UL + (NUM) * 0x8UL)

#define BTXMAC_BYTE_CNT			0x00448UL
#define  BTXMAC_BYTE_CNT_COUNT		0x00000000ffffffffULL

#define BTXMAC_FRM_CNT			0x00450UL
#define  BTXMAC_FRM_CNT_COUNT		0x00000000ffffffffULL

#define BRXMAC_BYTE_CNT			0x00458UL
#define  BRXMAC_BYTE_CNT_COUNT		0x00000000ffffffffULL

#define HOST_INFO_MPR			0x0000000000000100ULL
#define HOST_INFO_MACRDCTBLN		0x0000000000000007ULL

/* XPCS registers, offset from np->regs + np->xpcs_off  */

#define XPCS_CONTROL1			(FZC_MAC + 0x00000UL)
#define  XPCS_CONTROL1_RESET		0x0000000000008000ULL
#define  XPCS_CONTROL1_LOOPBACK		0x0000000000004000ULL
#define  XPCS_CONTROL1_SPEED_SELECT3	0x0000000000002000ULL
#define  XPCS_CONTROL1_CSR_LOW_PWR	0x0000000000000800ULL
#define  XPCS_CONTROL1_CSR_SPEED1	0x0000000000000040ULL
#define  XPCS_CONTROL1_CSR_SPEED0	0x000000000000003cULL

#define XPCS_STATUS1			(FZC_MAC + 0x00008UL)
#define  XPCS_STATUS1_CSR_FAULT		0x0000000000000080ULL
#define  XPCS_STATUS1_CSR_RXLNK_STAT	0x0000000000000004ULL
#define  XPCS_STATUS1_CSR_LPWR_ABLE	0x0000000000000002ULL

#define XPCS_DEVICE_IDENTIFIER		(FZC_MAC + 0x00010UL)
#define  XPCS_DEVICE_IDENTIFIER_VAL	0x00000000ffffffffULL

#define XPCS_SPEED_ABILITY		(FZC_MAC + 0x00018UL)
#define  XPCS_SPEED_ABILITY_10GIG	0x0000000000000001ULL

#define XPCS_DEV_IN_PKG			(FZC_MAC + 0x00020UL)
#define  XPCS_DEV_IN_PKG_CSR_VEND2	0x0000000080000000ULL
#define  XPCS_DEV_IN_PKG_CSR_VEND1	0x0000000040000000ULL
#define  XPCS_DEV_IN_PKG_DTE_XS		0x0000000000000020ULL
#define  XPCS_DEV_IN_PKG_PHY_XS		0x0000000000000010ULL
#define  XPCS_DEV_IN_PKG_PCS		0x0000000000000008ULL
#define  XPCS_DEV_IN_PKG_WIS		0x0000000000000004ULL
#define  XPCS_DEV_IN_PKG_PMD_PMA	0x0000000000000002ULL
#define  XPCS_DEV_IN_PKG_CLS22		0x0000000000000001ULL

#define XPCS_CONTROL2			(FZC_MAC + 0x00028UL)
#define  XPCS_CONTROL2_CSR_PSC_SEL	0x0000000000000003ULL

#define XPCS_STATUS2			(FZC_MAC + 0x00030UL)
#define  XPCS_STATUS2_CSR_DEV_PRES	0x000000000000c000ULL
#define  XPCS_STATUS2_CSR_TX_FAULT	0x0000000000000800ULL
#define  XPCS_STATUS2_CSR_RCV_FAULT	0x0000000000000400ULL
#define  XPCS_STATUS2_TEN_GBASE_W	0x0000000000000004ULL
#define  XPCS_STATUS2_TEN_GBASE_X	0x0000000000000002ULL
#define  XPCS_STATUS2_TEN_GBASE_R	0x0000000000000001ULL

#define XPCS_PKG_ID			(FZC_MAC + 0x00038UL)
#define  XPCS_PKG_ID_VAL		0x00000000ffffffffULL

#define XPCS_STATUS(IDX)		(FZC_MAC + 0x00040UL)
#define  XPCS_STATUS_CSR_LANE_ALIGN	0x0000000000001000ULL
#define  XPCS_STATUS_CSR_PATTEST_CAP	0x0000000000000800ULL
#define  XPCS_STATUS_CSR_LANE3_SYNC	0x0000000000000008ULL
#define  XPCS_STATUS_CSR_LANE2_SYNC	0x0000000000000004ULL
#define  XPCS_STATUS_CSR_LANE1_SYNC	0x0000000000000002ULL
#define  XPCS_STATUS_CSR_LANE0_SYNC	0x0000000000000001ULL

#define XPCS_TEST_CONTROL		(FZC_MAC + 0x00048UL)
#define  XPCS_TEST_CONTROL_TXTST_EN	0x0000000000000004ULL
#define  XPCS_TEST_CONTROL_TPAT_SEL	0x0000000000000003ULL

#define XPCS_CFG_VENDOR1		(FZC_MAC + 0x00050UL)
#define  XPCS_CFG_VENDOR1_DBG_IOTST	0x0000000000000080ULL
#define  XPCS_CFG_VENDOR1_DBG_SEL	0x0000000000000078ULL
#define  XPCS_CFG_VENDOR1_BYPASS_DET	0x0000000000000004ULL
#define  XPCS_CFG_VENDOR1_TXBUF_EN	0x0000000000000002ULL
#define  XPCS_CFG_VENDOR1_XPCS_EN	0x0000000000000001ULL

#define XPCS_DIAG_VENDOR2		(FZC_MAC + 0x00058UL)
#define  XPCS_DIAG_VENDOR2_SSM_LANE3	0x0000000001e00000ULL
#define  XPCS_DIAG_VENDOR2_SSM_LANE2	0x00000000001e0000ULL
#define  XPCS_DIAG_VENDOR2_SSM_LANE1	0x000000000001e000ULL
#define  XPCS_DIAG_VENDOR2_SSM_LANE0	0x0000000000001e00ULL