niu.h

linux 内核源代码

/* niu.h: Definitions for Neptune ethernet driver.
 *
 * Copyright (C) 2007 David S. Miller ([e-mail])
 */

#ifndef _NIU_H
#define _NIU_H

#define PIO			0x000000UL
#define FZC_PIO			0x080000UL
#define FZC_MAC			0x180000UL
#define FZC_IPP			0x280000UL
#define FFLP			0x300000UL
#define FZC_FFLP		0x380000UL
#define PIO_VADDR		0x400000UL
#define ZCP			0x500000UL
#define FZC_ZCP			0x580000UL
#define DMC			0x600000UL
#define FZC_DMC			0x680000UL
#define TXC			0x700000UL
#define FZC_TXC			0x780000UL
#define PIO_LDSV		0x800000UL
#define PIO_PIO_LDGIM		0x900000UL
#define PIO_IMASK0		0xa00000UL
#define PIO_IMASK1		0xb00000UL
#define FZC_PROM		0xc80000UL
#define FZC_PIM			0xd80000UL

#define LDSV0(LDG)		(PIO_LDSV + 0x00000UL + (LDG) * 0x2000UL)
#define LDSV1(LDG)		(PIO_LDSV + 0x00008UL + (LDG) * 0x2000UL)
#define LDSV2(LDG)		(PIO_LDSV + 0x00010UL + (LDG) * 0x2000UL)

#define LDG_IMGMT(LDG)		(PIO_LDSV + 0x00018UL + (LDG) * 0x2000UL)
#define  LDG_IMGMT_ARM		0x0000000080000000ULL
#define  LDG_IMGMT_TIMER	0x000000000000003fULL

#define LD_IM0(IDX)		(PIO_IMASK0 + 0x00000UL + (IDX) * 0x2000UL)
#define  LD_IM0_MASK		0x0000000000000003ULL

#define LD_IM1(IDX)		(PIO_IMASK1 + 0x00000UL + (IDX) * 0x2000UL)
#define  LD_IM1_MASK		0x0000000000000003ULL

#define LDG_TIMER_RES		(FZC_PIO + 0x00008UL)
#define  LDG_TIMER_RES_VAL	0x00000000000fffffULL

#define DIRTY_TID_CTL		(FZC_PIO + 0x00010UL)
#define  DIRTY_TID_CTL_NPTHRED	0x00000000003f0000ULL
#define  DIRTY_TID_CTL_RDTHRED	0x00000000000003f0ULL
#define  DIRTY_TID_CTL_DTIDCLR	0x0000000000000002ULL
#define  DIRTY_TID_CTL_DTIDENAB	0x0000000000000001ULL

#define DIRTY_TID_STAT		(FZC_PIO + 0x00018UL)
#define  DIRTY_TID_STAT_NPWSTAT	0x0000000000003f00ULL
#define  DIRTY_TID_STAT_RDSTAT	0x000000000000003fULL

#define RST_CTL			(FZC_PIO + 0x00038UL)
#define  RST_CTL_MAC_RST3	0x0000000000400000ULL
#define  RST_CTL_MAC_RST2	0x0000000000200000ULL
#define  RST_CTL_MAC_RST1	0x0000000000100000ULL
#define  RST_CTL_MAC_RST0	0x0000000000080000ULL
#define  RST_CTL_ACK_TO_EN	0x0000000000000800ULL
#define  RST_CTL_ACK_TO_VAL	0x00000000000007feULL

#define SMX_CFIG_DAT		(FZC_PIO + 0x00040UL)
#define  SMX_CFIG_DAT_RAS_DET	0x0000000080000000ULL
#define  SMX_CFIG_DAT_RAS_INJ	0x0000000040000000ULL
#define  SMX_CFIG_DAT_XACT_TO	0x000000000fffffffULL

#define SMX_INT_STAT		(FZC_PIO + 0x00048UL)
#define  SMX_INT_STAT_STAT	0x00000000ffffffffULL

#define SMX_CTL			(FZC_PIO + 0x00050UL)
#define  SMX_CTL_CTL		0x00000000ffffffffULL

#define SMX_DBG_VEC		(FZC_PIO + 0x00058UL)
#define  SMX_DBG_VEC_VEC	0x00000000ffffffffULL

#define PIO_DBG_SEL		(FZC_PIO + 0x00060UL)
#define  PIO_DBG_SEL_SEL	0x000000000000003fULL

#define PIO_TRAIN_VEC		(FZC_PIO + 0x00068UL)
#define  PIO_TRAIN_VEC_VEC	0x00000000ffffffffULL

#define PIO_ARB_CTL		(FZC_PIO + 0x00070UL)
#define  PIO_ARB_CTL_CTL	0x00000000ffffffffULL

#define PIO_ARB_DBG_VEC		(FZC_PIO + 0x00078UL)
#define  PIO_ARB_DBG_VEC_VEC	0x00000000ffffffffULL

#define SYS_ERR_MASK		(FZC_PIO + 0x00090UL)
#define  SYS_ERR_MASK_META2	0x0000000000000400ULL
#define  SYS_ERR_MASK_META1	0x0000000000000200ULL
#define  SYS_ERR_MASK_PEU	0x0000000000000100ULL
#define  SYS_ERR_MASK_TXC	0x0000000000000080ULL
#define  SYS_ERR_MASK_RDMC	0x0000000000000040ULL
#define  SYS_ERR_MASK_TDMC	0x0000000000000020ULL
#define  SYS_ERR_MASK_ZCP	0x0000000000000010ULL
#define  SYS_ERR_MASK_FFLP	0x0000000000000008ULL
#define  SYS_ERR_MASK_IPP	0x0000000000000004ULL
#define  SYS_ERR_MASK_MAC	0x0000000000000002ULL
#define  SYS_ERR_MASK_SMX	0x0000000000000001ULL

#define SYS_ERR_STAT			(FZC_PIO + 0x00098UL)
#define  SYS_ERR_STAT_META2		0x0000000000000400ULL
#define  SYS_ERR_STAT_META1		0x0000000000000200ULL
#define  SYS_ERR_STAT_PEU		0x0000000000000100ULL
#define  SYS_ERR_STAT_TXC		0x0000000000000080ULL
#define  SYS_ERR_STAT_RDMC		0x0000000000000040ULL
#define  SYS_ERR_STAT_TDMC		0x0000000000000020ULL
#define  SYS_ERR_STAT_ZCP		0x0000000000000010ULL
#define  SYS_ERR_STAT_FFLP		0x0000000000000008ULL
#define  SYS_ERR_STAT_IPP		0x0000000000000004ULL
#define  SYS_ERR_STAT_MAC		0x0000000000000002ULL
#define  SYS_ERR_STAT_SMX		0x0000000000000001ULL

#define SID(LDG)			(FZC_PIO + 0x10200UL + (LDG) * 8UL)
#define  SID_FUNC			0x0000000000000060ULL
#define  SID_FUNC_SHIFT			5
#define  SID_VECTOR			0x000000000000001fULL
#define  SID_VECTOR_SHIFT		0

#define LDG_NUM(LDN)			(FZC_PIO + 0x20000UL + (LDN) * 8UL)

#define XMAC_PORT0_OFF			(FZC_MAC + 0x000000)
#define XMAC_PORT1_OFF			(FZC_MAC + 0x006000)
#define BMAC_PORT2_OFF			(FZC_MAC + 0x00c000)
#define BMAC_PORT3_OFF			(FZC_MAC + 0x010000)

/* XMAC registers, offset from np->mac_regs  */

#define XTXMAC_SW_RST			0x00000UL
#define  XTXMAC_SW_RST_REG_RS		0x0000000000000002ULL
#define  XTXMAC_SW_RST_SOFT_RST		0x0000000000000001ULL

#define XRXMAC_SW_RST			0x00008UL
#define  XRXMAC_SW_RST_REG_RS		0x0000000000000002ULL
#define  XRXMAC_SW_RST_SOFT_RST		0x0000000000000001ULL

#define XTXMAC_STATUS			0x00020UL
#define  XTXMAC_STATUS_FRAME_CNT_EXP	0x0000000000000800ULL
#define  XTXMAC_STATUS_BYTE_CNT_EXP	0x0000000000000400ULL
#define  XTXMAC_STATUS_TXFIFO_XFR_ERR	0x0000000000000010ULL
#define  XTXMAC_STATUS_TXMAC_OFLOW	0x0000000000000008ULL
#define  XTXMAC_STATUS_MAX_PSIZE_ERR	0x0000000000000004ULL
#define  XTXMAC_STATUS_TXMAC_UFLOW	0x0000000000000002ULL
#define  XTXMAC_STATUS_FRAME_XMITED	0x0000000000000001ULL

#define XRXMAC_STATUS			0x00028UL
#define  XRXMAC_STATUS_RXHIST7_CNT_EXP	0x0000000000100000ULL
#define  XRXMAC_STATUS_LCL_FLT_STATUS	0x0000000000080000ULL
#define  XRXMAC_STATUS_RFLT_DET		0x0000000000040000ULL
#define  XRXMAC_STATUS_LFLT_CNT_EXP	0x0000000000020000ULL
#define  XRXMAC_STATUS_PHY_MDINT	0x0000000000010000ULL
#define  XRXMAC_STATUS_ALIGNERR_CNT_EXP	0x0000000000010000ULL
#define  XRXMAC_STATUS_RXFRAG_CNT_EXP	0x0000000000008000ULL
#define  XRXMAC_STATUS_RXMULTF_CNT_EXP	0x0000000000004000ULL
#define  XRXMAC_STATUS_RXBCAST_CNT_EXP	0x0000000000002000ULL
#define  XRXMAC_STATUS_RXHIST6_CNT_EXP	0x0000000000001000ULL
#define  XRXMAC_STATUS_RXHIST5_CNT_EXP	0x0000000000000800ULL
#define  XRXMAC_STATUS_RXHIST4_CNT_EXP	0x0000000000000400ULL
#define  XRXMAC_STATUS_RXHIST3_CNT_EXP	0x0000000000000200ULL
#define  XRXMAC_STATUS_RXHIST2_CNT_EXP	0x0000000000000100ULL
#define  XRXMAC_STATUS_RXHIST1_CNT_EXP	0x0000000000000080ULL
#define  XRXMAC_STATUS_RXOCTET_CNT_EXP	0x0000000000000040ULL
#define  XRXMAC_STATUS_CVIOLERR_CNT_EXP	0x0000000000000020ULL
#define  XRXMAC_STATUS_LENERR_CNT_EXP	0x0000000000000010ULL
#define  XRXMAC_STATUS_CRCERR_CNT_EXP	0x0000000000000008ULL
#define  XRXMAC_STATUS_RXUFLOW		0x0000000000000004ULL
#define  XRXMAC_STATUS_RXOFLOW		0x0000000000000002ULL
#define  XRXMAC_STATUS_FRAME_RCVD	0x0000000000000001ULL

#define XMAC_FC_STAT			0x00030UL
#define  XMAC_FC_STAT_RX_RCV_PAUSE_TIME	0x00000000ffff0000ULL
#define  XMAC_FC_STAT_TX_MAC_NPAUSE	0x0000000000000004ULL
#define  XMAC_FC_STAT_TX_MAC_PAUSE	0x0000000000000002ULL
#define  XMAC_FC_STAT_RX_MAC_RPAUSE	0x0000000000000001ULL

#define XTXMAC_STAT_MSK			0x00040UL
#define  XTXMAC_STAT_MSK_FRAME_CNT_EXP	0x0000000000000800ULL
#define  XTXMAC_STAT_MSK_BYTE_CNT_EXP	0x0000000000000400ULL
#define  XTXMAC_STAT_MSK_TXFIFO_XFR_ERR	0x0000000000000010ULL
#define  XTXMAC_STAT_MSK_TXMAC_OFLOW	0x0000000000000008ULL
#define  XTXMAC_STAT_MSK_MAX_PSIZE_ERR	0x0000000000000004ULL
#define  XTXMAC_STAT_MSK_TXMAC_UFLOW	0x0000000000000002ULL
#define  XTXMAC_STAT_MSK_FRAME_XMITED	0x0000000000000001ULL

#define XRXMAC_STAT_MSK				0x00048UL
#define  XRXMAC_STAT_MSK_LCL_FLT_STAT_MSK	0x0000000000080000ULL
#define  XRXMAC_STAT_MSK_RFLT_DET		0x0000000000040000ULL
#define  XRXMAC_STAT_MSK_LFLT_CNT_EXP		0x0000000000020000ULL
#define  XRXMAC_STAT_MSK_PHY_MDINT		0x0000000000010000ULL
#define  XRXMAC_STAT_MSK_RXFRAG_CNT_EXP		0x0000000000008000ULL
#define  XRXMAC_STAT_MSK_RXMULTF_CNT_EXP	0x0000000000004000ULL
#define  XRXMAC_STAT_MSK_RXBCAST_CNT_EXP	0x0000000000002000ULL
#define  XRXMAC_STAT_MSK_RXHIST6_CNT_EXP	0x0000000000001000ULL
#define  XRXMAC_STAT_MSK_RXHIST5_CNT_EXP	0x0000000000000800ULL
#define  XRXMAC_STAT_MSK_RXHIST4_CNT_EXP	0x0000000000000400ULL
#define  XRXMAC_STAT_MSK_RXHIST3_CNT_EXP	0x0000000000000200ULL
#define  XRXMAC_STAT_MSK_RXHIST2_CNT_EXP	0x0000000000000100ULL
#define  XRXMAC_STAT_MSK_RXHIST1_CNT_EXP	0x0000000000000080ULL
#define  XRXMAC_STAT_MSK_RXOCTET_CNT_EXP	0x0000000000000040ULL
#define  XRXMAC_STAT_MSK_CVIOLERR_CNT_EXP	0x0000000000000020ULL
#define  XRXMAC_STAT_MSK_LENERR_CNT_EXP		0x0000000000000010ULL
#define  XRXMAC_STAT_MSK_CRCERR_CNT_EXP		0x0000000000000008ULL
#define  XRXMAC_STAT_MSK_RXUFLOW_CNT_EXP	0x0000000000000004ULL
#define  XRXMAC_STAT_MSK_RXOFLOW_CNT_EXP	0x0000000000000002ULL
#define  XRXMAC_STAT_MSK_FRAME_RCVD		0x0000000000000001ULL

#define XMAC_FC_MSK			0x00050UL
#define  XMAC_FC_MSK_TX_MAC_NPAUSE	0x0000000000000004ULL
#define  XMAC_FC_MSK_TX_MAC_PAUSE	0x0000000000000002ULL
#define  XMAC_FC_MSK_RX_MAC_RPAUSE	0x0000000000000001ULL

#define XMAC_CONFIG			0x00060UL
#define  XMAC_CONFIG_SEL_CLK_25MHZ	0x0000000080000000ULL
#define  XMAC_CONFIG_1G_PCS_BYPASS	0x0000000040000000ULL
#define  XMAC_CONFIG_10G_XPCS_BYPASS	0x0000000020000000ULL
#define  XMAC_CONFIG_MODE_MASK		0x0000000018000000ULL
#define  XMAC_CONFIG_MODE_XGMII		0x0000000000000000ULL
#define  XMAC_CONFIG_MODE_GMII		0x0000000008000000ULL
#define  XMAC_CONFIG_MODE_MII		0x0000000010000000ULL
#define  XMAC_CONFIG_LFS_DISABLE	0x0000000004000000ULL
#define  XMAC_CONFIG_LOOPBACK		0x0000000002000000ULL
#define  XMAC_CONFIG_TX_OUTPUT_EN	0x0000000001000000ULL
#define  XMAC_CONFIG_SEL_POR_CLK_SRC	0x0000000000800000ULL
#define  XMAC_CONFIG_LED_POLARITY	0x0000000000400000ULL
#define  XMAC_CONFIG_FORCE_LED_ON	0x0000000000200000ULL
#define  XMAC_CONFIG_PASS_FLOW_CTRL	0x0000000000100000ULL
#define  XMAC_CONFIG_RCV_PAUSE_ENABLE	0x0000000000080000ULL
#define  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN	0x0000000000040000ULL
#define  XMAC_CONFIG_STRIP_CRC		0x0000000000020000ULL
#define  XMAC_CONFIG_ADDR_FILTER_EN	0x0000000000010000ULL
#define  XMAC_CONFIG_HASH_FILTER_EN	0x0000000000008000ULL
#define  XMAC_CONFIG_RX_CODEV_CHK_DIS	0x0000000000004000ULL
#define  XMAC_CONFIG_RESERVED_MULTICAST	0x0000000000002000ULL
#define  XMAC_CONFIG_RX_CRC_CHK_DIS	0x0000000000001000ULL
#define  XMAC_CONFIG_ERR_CHK_DIS	0x0000000000000800ULL
#define  XMAC_CONFIG_PROMISC_GROUP	0x0000000000000400ULL
#define  XMAC_CONFIG_PROMISCUOUS	0x0000000000000200ULL
#define  XMAC_CONFIG_RX_MAC_ENABLE	0x0000000000000100ULL
#define  XMAC_CONFIG_WARNING_MSG_EN	0x0000000000000080ULL
#define  XMAC_CONFIG_ALWAYS_NO_CRC	0x0000000000000008ULL
#define  XMAC_CONFIG_VAR_MIN_IPG_EN	0x0000000000000004ULL
#define  XMAC_CONFIG_STRETCH_MODE	0x0000000000000002ULL
#define  XMAC_CONFIG_TX_ENABLE		0x0000000000000001ULL

#define XMAC_IPG			0x00080UL
#define  XMAC_IPG_STRETCH_CONST		0x0000000000e00000ULL
#define  XMAC_IPG_STRETCH_CONST_SHIFT	21
#define  XMAC_IPG_STRETCH_RATIO		0x00000000001f0000ULL
#define  XMAC_IPG_STRETCH_RATIO_SHIFT	16
#define  XMAC_IPG_IPG_MII_GMII		0x000000000000ff00ULL
#define  XMAC_IPG_IPG_MII_GMII_SHIFT	8
#define  XMAC_IPG_IPG_XGMII		0x0000000000000007ULL
#define  XMAC_IPG_IPG_XGMII_SHIFT	0

#define IPG_12_15_XGMII			3
#define IPG_16_19_XGMII			4
#define IPG_20_23_XGMII			5
#define IPG_12_MII_GMII			10
#define IPG_13_MII_GMII			11
#define IPG_14_MII_GMII			12
#define IPG_15_MII_GMII			13
#define IPG_16_MII_GMII			14

#define XMAC_MIN			0x00088UL
#define  XMAC_MIN_RX_MIN_PKT_SIZE	0x000000003ff00000ULL
#define  XMAC_MIN_RX_MIN_PKT_SIZE_SHFT	20
#define  XMAC_MIN_SLOT_TIME		0x000000000003fc00ULL
#define  XMAC_MIN_SLOT_TIME_SHFT	10
#define  XMAC_MIN_TX_MIN_PKT_SIZE	0x00000000000003ffULL
#define  XMAC_MIN_TX_MIN_PKT_SIZE_SHFT	0

#define XMAC_MAX			0x00090UL
#define  XMAC_MAX_FRAME_SIZE		0x0000000000003fffULL
#define  XMAC_MAX_FRAME_SIZE_SHFT	0

#define XMAC_ADDR0			0x000a0UL
#define  XMAC_ADDR0_ADDR0		0x000000000000ffffULL

#define XMAC_ADDR1			0x000a8UL
#define  XMAC_ADDR1_ADDR1		0x000000000000ffffULL

#define XMAC_ADDR2			0x000b0UL 
#define  XMAC_ADDR2_ADDR2		0x000000000000ffffULL

#define XMAC_ADDR_CMPEN			0x00208UL
#define  XMAC_ADDR_CMPEN_EN15		0x0000000000008000ULL
#define  XMAC_ADDR_CMPEN_EN14		0x0000000000004000ULL
#define  XMAC_ADDR_CMPEN_EN13		0x0000000000002000ULL
#define  XMAC_ADDR_CMPEN_EN12		0x0000000000001000ULL
#define  XMAC_ADDR_CMPEN_EN11		0x0000000000000800ULL
#define  XMAC_ADDR_CMPEN_EN10		0x0000000000000400ULL
#define  XMAC_ADDR_CMPEN_EN9		0x0000000000000200ULL
#define  XMAC_ADDR_CMPEN_EN8		0x0000000000000100ULL
#define  XMAC_ADDR_CMPEN_EN7		0x0000000000000080ULL
#define  XMAC_ADDR_CMPEN_EN6		0x0000000000000040ULL
#define  XMAC_ADDR_CMPEN_EN5		0x0000000000000020ULL
#define  XMAC_ADDR_CMPEN_EN4		0x0000000000000010ULL
#define  XMAC_ADDR_CMPEN_EN3		0x0000000000000008ULL
#define  XMAC_ADDR_CMPEN_EN2		0x0000000000000004ULL
#define  XMAC_ADDR_CMPEN_EN1		0x0000000000000002ULL
#define  XMAC_ADDR_CMPEN_EN0		0x0000000000000001ULL

#define XMAC_NUM_ALT_ADDR		16

#define XMAC_ALT_ADDR0(NUM)		(0x00218UL + (NUM)*0x18UL)
#define  XMAC_ALT_ADDR0_ADDR0		0x000000000000ffffULL

#define XMAC_ALT_ADDR1(NUM)		(0x00220UL + (NUM)*0x18UL)
#define  XMAC_ALT_ADDR1_ADDR1		0x000000000000ffffULL

#define XMAC_ALT_ADDR2(NUM)		(0x00228UL + (NUM)*0x18UL)
#define  XMAC_ALT_ADDR2_ADDR2		0x000000000000ffffULL

#define XMAC_ADD_FILT0			0x00818UL
#define  XMAC_ADD_FILT0_FILT0		0x000000000000ffffULL

#define XMAC_ADD_FILT1			0x00820UL
#define  XMAC_ADD_FILT1_FILT1		0x000000000000ffffULL

#define XMAC_ADD_FILT2			0x00828UL
#define  XMAC_ADD_FILT2_FILT2		0x000000000000ffffULL

#define XMAC_ADD_FILT12_MASK		0x00830UL
#define  XMAC_ADD_FILT12_MASK_VAL	0x00000000000000ffULL

#define XMAC_ADD_FILT00_MASK		0x00838UL
#define  XMAC_ADD_FILT00_MASK_VAL	0x000000000000ffffULL