📄 smc911x.h
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#define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register *///#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)#define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)//#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)//#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)//#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)//#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)//#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)//#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)//#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)#define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)#define PHY_INT_SRC ((u32)29)#define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)#define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)#define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)#define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)#define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)#define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)#define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)#define PHY_INT_MASK ((u32)30)#define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)#define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)#define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)#define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)#define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)#define PHY_SPECIAL ((u32)31)#define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)#define PHY_SPECIAL_RES_ ((u16)0x0040)#define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)#define PHY_SPECIAL_SPD_ ((u16)0x001C)#define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)#define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)#define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)#define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)#define LAN911X_INTERNAL_PHY_ID (0x0007C000)/* Chip ID values */#define CHIP_9115 0x115#define CHIP_9116 0x116#define CHIP_9117 0x117#define CHIP_9118 0x118struct chip_id { u16 id; char *name;};static const struct chip_id chip_ids[] = { { CHIP_9115, "LAN9115" }, { CHIP_9116, "LAN9116" }, { CHIP_9117, "LAN9117" }, { CHIP_9118, "LAN9118" }, { 0, NULL },};#define IS_REV_A(x) ((x & 0xFFFF)==0)/* * Macros to abstract register access according to the data bus * capabilities. Please use those and not the in/out primitives. *//* FIFO read/write macros */#define SMC_PUSH_DATA(p, l) SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 )#define SMC_PULL_DATA(p, l) SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 )#define SMC_SET_TX_FIFO(x) SMC_outl( x, ioaddr, TX_DATA_FIFO )#define SMC_GET_RX_FIFO() SMC_inl( ioaddr, RX_DATA_FIFO )/* I/O mapped register read/write macros */#define SMC_GET_TX_STS_FIFO() SMC_inl( ioaddr, TX_STATUS_FIFO )#define SMC_GET_RX_STS_FIFO() SMC_inl( ioaddr, RX_STATUS_FIFO )#define SMC_GET_RX_STS_FIFO_PEEK() SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK )#define SMC_GET_PN() (SMC_inl( ioaddr, ID_REV ) >> 16)#define SMC_GET_REV() (SMC_inl( ioaddr, ID_REV ) & 0xFFFF)#define SMC_GET_IRQ_CFG() SMC_inl( ioaddr, INT_CFG )#define SMC_SET_IRQ_CFG(x) SMC_outl( x, ioaddr, INT_CFG )#define SMC_GET_INT() SMC_inl( ioaddr, INT_STS )#define SMC_ACK_INT(x) SMC_outl( x, ioaddr, INT_STS )#define SMC_GET_INT_EN() SMC_inl( ioaddr, INT_EN )#define SMC_SET_INT_EN(x) SMC_outl( x, ioaddr, INT_EN )#define SMC_GET_BYTE_TEST() SMC_inl( ioaddr, BYTE_TEST )#define SMC_SET_BYTE_TEST(x) SMC_outl( x, ioaddr, BYTE_TEST )#define SMC_GET_FIFO_INT() SMC_inl( ioaddr, FIFO_INT )#define SMC_SET_FIFO_INT(x) SMC_outl( x, ioaddr, FIFO_INT )#define SMC_SET_FIFO_TDA(x) \ do { \ unsigned long __flags; \ int __mask; \ local_irq_save(__flags); \ __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24); \ SMC_SET_FIFO_INT( __mask | (x)<<24 ); \ local_irq_restore(__flags); \ } while (0)#define SMC_SET_FIFO_TSL(x) \ do { \ unsigned long __flags; \ int __mask; \ local_irq_save(__flags); \ __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16); \ SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \ local_irq_restore(__flags); \ } while (0)#define SMC_SET_FIFO_RSA(x) \ do { \ unsigned long __flags; \ int __mask; \ local_irq_save(__flags); \ __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8); \ SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8)); \ local_irq_restore(__flags); \ } while (0)#define SMC_SET_FIFO_RSL(x) \ do { \ unsigned long __flags; \ int __mask; \ local_irq_save(__flags); \ __mask = SMC_GET_FIFO_INT() & ~0xFF; \ SMC_SET_FIFO_INT( __mask | ((x) & 0xFF)); \ local_irq_restore(__flags); \ } while (0)#define SMC_GET_RX_CFG() SMC_inl( ioaddr, RX_CFG )#define SMC_SET_RX_CFG(x) SMC_outl( x, ioaddr, RX_CFG )#define SMC_GET_TX_CFG() SMC_inl( ioaddr, TX_CFG )#define SMC_SET_TX_CFG(x) SMC_outl( x, ioaddr, TX_CFG )#define SMC_GET_HW_CFG() SMC_inl( ioaddr, HW_CFG )#define SMC_SET_HW_CFG(x) SMC_outl( x, ioaddr, HW_CFG )#define SMC_GET_RX_DP_CTRL() SMC_inl( ioaddr, RX_DP_CTRL )#define SMC_SET_RX_DP_CTRL(x) SMC_outl( x, ioaddr, RX_DP_CTRL )#define SMC_GET_PMT_CTRL() SMC_inl( ioaddr, PMT_CTRL )#define SMC_SET_PMT_CTRL(x) SMC_outl( x, ioaddr, PMT_CTRL )#define SMC_GET_GPIO_CFG() SMC_inl( ioaddr, GPIO_CFG )#define SMC_SET_GPIO_CFG(x) SMC_outl( x, ioaddr, GPIO_CFG )#define SMC_GET_RX_FIFO_INF() SMC_inl( ioaddr, RX_FIFO_INF )#define SMC_SET_RX_FIFO_INF(x) SMC_outl( x, ioaddr, RX_FIFO_INF )#define SMC_GET_TX_FIFO_INF() SMC_inl( ioaddr, TX_FIFO_INF )#define SMC_SET_TX_FIFO_INF(x) SMC_outl( x, ioaddr, TX_FIFO_INF )#define SMC_GET_GPT_CFG() SMC_inl( ioaddr, GPT_CFG )#define SMC_SET_GPT_CFG(x) SMC_outl( x, ioaddr, GPT_CFG )#define SMC_GET_RX_DROP() SMC_inl( ioaddr, RX_DROP )#define SMC_SET_RX_DROP(x) SMC_outl( x, ioaddr, RX_DROP )#define SMC_GET_MAC_CMD() SMC_inl( ioaddr, MAC_CSR_CMD )#define SMC_SET_MAC_CMD(x) SMC_outl( x, ioaddr, MAC_CSR_CMD )#define SMC_GET_MAC_DATA() SMC_inl( ioaddr, MAC_CSR_DATA )#define SMC_SET_MAC_DATA(x) SMC_outl( x, ioaddr, MAC_CSR_DATA )#define SMC_GET_AFC_CFG() SMC_inl( ioaddr, AFC_CFG )#define SMC_SET_AFC_CFG(x) SMC_outl( x, ioaddr, AFC_CFG )#define SMC_GET_E2P_CMD() SMC_inl( ioaddr, E2P_CMD )#define SMC_SET_E2P_CMD(x) SMC_outl( x, ioaddr, E2P_CMD )#define SMC_GET_E2P_DATA() SMC_inl( ioaddr, E2P_DATA )#define SMC_SET_E2P_DATA(x) SMC_outl( x, ioaddr, E2P_DATA )/* MAC register read/write macros */#define SMC_GET_MAC_CSR(a,v) \ do { \ while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | \ MAC_CSR_CMD_R_NOT_W_ | (a) ); \ while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ v = SMC_GET_MAC_DATA(); \ } while (0)#define SMC_SET_MAC_CSR(a,v) \ do { \ while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ SMC_SET_MAC_DATA(v); \ SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) ); \ while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ } while (0)#define SMC_GET_MAC_CR(x) SMC_GET_MAC_CSR( MAC_CR, x )#define SMC_SET_MAC_CR(x) SMC_SET_MAC_CSR( MAC_CR, x )#define SMC_GET_ADDRH(x) SMC_GET_MAC_CSR( ADDRH, x )#define SMC_SET_ADDRH(x) SMC_SET_MAC_CSR( ADDRH, x )#define SMC_GET_ADDRL(x) SMC_GET_MAC_CSR( ADDRL, x )#define SMC_SET_ADDRL(x) SMC_SET_MAC_CSR( ADDRL, x )#define SMC_GET_HASHH(x) SMC_GET_MAC_CSR( HASHH, x )#define SMC_SET_HASHH(x) SMC_SET_MAC_CSR( HASHH, x )#define SMC_GET_HASHL(x) SMC_GET_MAC_CSR( HASHL, x )#define SMC_SET_HASHL(x) SMC_SET_MAC_CSR( HASHL, x )#define SMC_GET_MII_ACC(x) SMC_GET_MAC_CSR( MII_ACC, x )#define SMC_SET_MII_ACC(x) SMC_SET_MAC_CSR( MII_ACC, x )#define SMC_GET_MII_DATA(x) SMC_GET_MAC_CSR( MII_DATA, x )#define SMC_SET_MII_DATA(x) SMC_SET_MAC_CSR( MII_DATA, x )#define SMC_GET_FLOW(x) SMC_GET_MAC_CSR( FLOW, x )#define SMC_SET_FLOW(x) SMC_SET_MAC_CSR( FLOW, x )#define SMC_GET_VLAN1(x) SMC_GET_MAC_CSR( VLAN1, x )#define SMC_SET_VLAN1(x) SMC_SET_MAC_CSR( VLAN1, x )#define SMC_GET_VLAN2(x) SMC_GET_MAC_CSR( VLAN2, x )#define SMC_SET_VLAN2(x) SMC_SET_MAC_CSR( VLAN2, x )#define SMC_SET_WUFF(x) SMC_SET_MAC_CSR( WUFF, x )#define SMC_GET_WUCSR(x) SMC_GET_MAC_CSR( WUCSR, x )#define SMC_SET_WUCSR(x) SMC_SET_MAC_CSR( WUCSR, x )/* PHY register read/write macros */#define SMC_GET_MII(a,phy,v) \ do { \ u32 __v; \ do { \ SMC_GET_MII_ACC(__v); \ } while ( __v & MII_ACC_MII_BUSY_ ); \ SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \ MII_ACC_MII_BUSY_); \ do { \ SMC_GET_MII_ACC(__v); \ } while ( __v & MII_ACC_MII_BUSY_ ); \ SMC_GET_MII_DATA(v); \ } while (0)#define SMC_SET_MII(a,phy,v) \ do { \ u32 __v; \ do { \ SMC_GET_MII_ACC(__v); \ } while ( __v & MII_ACC_MII_BUSY_ ); \ SMC_SET_MII_DATA(v); \ SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \ MII_ACC_MII_BUSY_ | \ MII_ACC_MII_WRITE_ ); \ do { \ SMC_GET_MII_ACC(__v); \ } while ( __v & MII_ACC_MII_BUSY_ ); \ } while (0)#define SMC_GET_PHY_BMCR(phy,x) SMC_GET_MII( MII_BMCR, phy, x )#define SMC_SET_PHY_BMCR(phy,x) SMC_SET_MII( MII_BMCR, phy, x )#define SMC_GET_PHY_BMSR(phy,x) SMC_GET_MII( MII_BMSR, phy, x )#define SMC_GET_PHY_ID1(phy,x) SMC_GET_MII( MII_PHYSID1, phy, x )#define SMC_GET_PHY_ID2(phy,x) SMC_GET_MII( MII_PHYSID2, phy, x )#define SMC_GET_PHY_MII_ADV(phy,x) SMC_GET_MII( MII_ADVERTISE, phy, x )#define SMC_SET_PHY_MII_ADV(phy,x) SMC_SET_MII( MII_ADVERTISE, phy, x )#define SMC_GET_PHY_MII_LPA(phy,x) SMC_GET_MII( MII_LPA, phy, x )#define SMC_SET_PHY_MII_LPA(phy,x) SMC_SET_MII( MII_LPA, phy, x )#define SMC_GET_PHY_CTRL_STS(phy,x) SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x )#define SMC_SET_PHY_CTRL_STS(phy,x) SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x )#define SMC_GET_PHY_INT_SRC(phy,x) SMC_GET_MII( PHY_INT_SRC, phy, x )#define SMC_SET_PHY_INT_SRC(phy,x) SMC_SET_MII( PHY_INT_SRC, phy, x )#define SMC_GET_PHY_INT_MASK(phy,x) SMC_GET_MII( PHY_INT_MASK, phy, x )#define SMC_SET_PHY_INT_MASK(phy,x) SMC_SET_MII( PHY_INT_MASK, phy, x )#define SMC_GET_PHY_SPECIAL(phy,x) SMC_GET_MII( PHY_SPECIAL, phy, x )/* Misc read/write macros */#ifndef SMC_GET_MAC_ADDR#define SMC_GET_MAC_ADDR(addr) \ do { \ unsigned int __v; \ \ SMC_GET_MAC_CSR(ADDRL, __v); \ addr[0] = __v; addr[1] = __v >> 8; \ addr[2] = __v >> 16; addr[3] = __v >> 24; \ SMC_GET_MAC_CSR(ADDRH, __v); \ addr[4] = __v; addr[5] = __v >> 8; \ } while (0)#endif#define SMC_SET_MAC_ADDR(addr) \ do { \ SMC_SET_MAC_CSR(ADDRL, \ addr[0] | \ (addr[1] << 8) | \ (addr[2] << 16) | \ (addr[3] << 24)); \ SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\ } while (0)#define SMC_WRITE_EEPROM_CMD(cmd, addr) \ do { \ while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a ); \ while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ } while (0)#endif /* _SMC911X_H_ */⌨️ 快捷键说明
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