skge.h

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/*
 * Definitions for the new Marvell Yukon / SysKonnect driver.
 */
#ifndef _SKGE_H
#define _SKGE_H

/* PCI config registers */
#define PCI_DEV_REG1	0x40
#define  PCI_PHY_COMA	0x8000000
#define  PCI_VIO	0x2000000

#define PCI_DEV_REG2	0x44
#define  PCI_VPD_ROM_SZ	7L<<14	/* VPD ROM size 0=256, 1=512, ... */
#define  PCI_REV_DESC	1<<2	/* Reverse Descriptor bytes */

#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
			       PCI_STATUS_SIG_SYSTEM_ERROR | \
			       PCI_STATUS_REC_MASTER_ABORT | \
			       PCI_STATUS_REC_TARGET_ABORT | \
			       PCI_STATUS_PARITY)

enum csr_regs {
	B0_RAP	= 0x0000,
	B0_CTST	= 0x0004,
	B0_LED	= 0x0006,
	B0_POWER_CTRL	= 0x0007,
	B0_ISRC	= 0x0008,
	B0_IMSK	= 0x000c,
	B0_HWE_ISRC	= 0x0010,
	B0_HWE_IMSK	= 0x0014,
	B0_SP_ISRC	= 0x0018,
	B0_XM1_IMSK	= 0x0020,
	B0_XM1_ISRC	= 0x0028,
	B0_XM1_PHY_ADDR	= 0x0030,
	B0_XM1_PHY_DATA	= 0x0034,
	B0_XM2_IMSK	= 0x0040,
	B0_XM2_ISRC	= 0x0048,
	B0_XM2_PHY_ADDR	= 0x0050,
	B0_XM2_PHY_DATA	= 0x0054,
	B0_R1_CSR	= 0x0060,
	B0_R2_CSR	= 0x0064,
	B0_XS1_CSR	= 0x0068,
	B0_XA1_CSR	= 0x006c,
	B0_XS2_CSR	= 0x0070,
	B0_XA2_CSR	= 0x0074,

	B2_MAC_1	= 0x0100,
	B2_MAC_2	= 0x0108,
	B2_MAC_3	= 0x0110,
	B2_CONN_TYP	= 0x0118,
	B2_PMD_TYP	= 0x0119,
	B2_MAC_CFG	= 0x011a,
	B2_CHIP_ID	= 0x011b,
	B2_E_0		= 0x011c,
	B2_E_1		= 0x011d,
	B2_E_2		= 0x011e,
	B2_E_3		= 0x011f,
	B2_FAR		= 0x0120,
	B2_FDP		= 0x0124,
	B2_LD_CTRL	= 0x0128,
	B2_LD_TEST	= 0x0129,
	B2_TI_INI	= 0x0130,
	B2_TI_VAL	= 0x0134,
	B2_TI_CTRL	= 0x0138,
	B2_TI_TEST	= 0x0139,
	B2_IRQM_INI	= 0x0140,
	B2_IRQM_VAL	= 0x0144,
	B2_IRQM_CTRL	= 0x0148,
	B2_IRQM_TEST	= 0x0149,
	B2_IRQM_MSK	= 0x014c,
	B2_IRQM_HWE_MSK	= 0x0150,
	B2_TST_CTRL1	= 0x0158,
	B2_TST_CTRL2	= 0x0159,
	B2_GP_IO	= 0x015c,
	B2_I2C_CTRL	= 0x0160,
	B2_I2C_DATA	= 0x0164,
	B2_I2C_IRQ	= 0x0168,
	B2_I2C_SW	= 0x016c,
	B2_BSC_INI	= 0x0170,
	B2_BSC_VAL	= 0x0174,
	B2_BSC_CTRL	= 0x0178,
	B2_BSC_STAT	= 0x0179,
	B2_BSC_TST	= 0x017a,

	B3_RAM_ADDR	= 0x0180,
	B3_RAM_DATA_LO	= 0x0184,
	B3_RAM_DATA_HI	= 0x0188,
	B3_RI_WTO_R1	= 0x0190,
	B3_RI_WTO_XA1	= 0x0191,
	B3_RI_WTO_XS1	= 0x0192,
	B3_RI_RTO_R1	= 0x0193,
	B3_RI_RTO_XA1	= 0x0194,
	B3_RI_RTO_XS1	= 0x0195,
	B3_RI_WTO_R2	= 0x0196,
	B3_RI_WTO_XA2	= 0x0197,
	B3_RI_WTO_XS2	= 0x0198,
	B3_RI_RTO_R2	= 0x0199,
	B3_RI_RTO_XA2	= 0x019a,
	B3_RI_RTO_XS2	= 0x019b,
	B3_RI_TO_VAL	= 0x019c,
	B3_RI_CTRL	= 0x01a0,
	B3_RI_TEST	= 0x01a2,
	B3_MA_TOINI_RX1	= 0x01b0,
	B3_MA_TOINI_RX2	= 0x01b1,
	B3_MA_TOINI_TX1	= 0x01b2,
	B3_MA_TOINI_TX2	= 0x01b3,
	B3_MA_TOVAL_RX1	= 0x01b4,
	B3_MA_TOVAL_RX2	= 0x01b5,
	B3_MA_TOVAL_TX1	= 0x01b6,
	B3_MA_TOVAL_TX2	= 0x01b7,
	B3_MA_TO_CTRL	= 0x01b8,
	B3_MA_TO_TEST	= 0x01ba,
	B3_MA_RCINI_RX1	= 0x01c0,
	B3_MA_RCINI_RX2	= 0x01c1,
	B3_MA_RCINI_TX1	= 0x01c2,
	B3_MA_RCINI_TX2	= 0x01c3,
	B3_MA_RCVAL_RX1	= 0x01c4,
	B3_MA_RCVAL_RX2	= 0x01c5,
	B3_MA_RCVAL_TX1	= 0x01c6,
	B3_MA_RCVAL_TX2	= 0x01c7,
	B3_MA_RC_CTRL	= 0x01c8,
	B3_MA_RC_TEST	= 0x01ca,
	B3_PA_TOINI_RX1	= 0x01d0,
	B3_PA_TOINI_RX2	= 0x01d4,
	B3_PA_TOINI_TX1	= 0x01d8,
	B3_PA_TOINI_TX2	= 0x01dc,
	B3_PA_TOVAL_RX1	= 0x01e0,
	B3_PA_TOVAL_RX2	= 0x01e4,
	B3_PA_TOVAL_TX1	= 0x01e8,
	B3_PA_TOVAL_TX2	= 0x01ec,
	B3_PA_CTRL	= 0x01f0,
	B3_PA_TEST	= 0x01f2,
};

/*	B0_CTST			16 bit	Control/Status register */
enum {
	CS_CLK_RUN_HOT	= 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
	CS_CLK_RUN_RST	= 1<<12,/* CLK_RUN reset  (YUKON-Lite only) */
	CS_CLK_RUN_ENA	= 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
	CS_VAUX_AVAIL	= 1<<10,/* VAUX available (YUKON only) */
	CS_BUS_CLOCK	= 1<<9,	/* Bus Clock 0/1 = 33/66 MHz */
	CS_BUS_SLOT_SZ	= 1<<8,	/* Slot Size 0/1 = 32/64 bit slot */
	CS_ST_SW_IRQ	= 1<<7,	/* Set IRQ SW Request */
	CS_CL_SW_IRQ	= 1<<6,	/* Clear IRQ SW Request */
	CS_STOP_DONE	= 1<<5,	/* Stop Master is finished */
	CS_STOP_MAST	= 1<<4,	/* Command Bit to stop the master */
	CS_MRST_CLR	= 1<<3,	/* Clear Master reset	*/
	CS_MRST_SET	= 1<<2,	/* Set Master reset	*/
	CS_RST_CLR	= 1<<1,	/* Clear Software reset	*/
	CS_RST_SET	= 1,	/* Set   Software reset	*/

/*	B0_LED			 8 Bit	LED register */
/* Bit  7.. 2:	reserved */
	LED_STAT_ON	= 1<<1,	/* Status LED on	*/
	LED_STAT_OFF	= 1,		/* Status LED off	*/

/*	B0_POWER_CTRL	 8 Bit	Power Control reg (YUKON only) */
	PC_VAUX_ENA	= 1<<7,	/* Switch VAUX Enable  */
	PC_VAUX_DIS	= 1<<6,	/* Switch VAUX Disable */
	PC_VCC_ENA	= 1<<5,	/* Switch VCC Enable  */
	PC_VCC_DIS	= 1<<4,	/* Switch VCC Disable */
	PC_VAUX_ON	= 1<<3,	/* Switch VAUX On  */
	PC_VAUX_OFF	= 1<<2,	/* Switch VAUX Off */
	PC_VCC_ON	= 1<<1,	/* Switch VCC On  */
	PC_VCC_OFF	= 1<<0,	/* Switch VCC Off */
};

/*	B2_IRQM_MSK 	32 bit	IRQ Moderation Mask */
enum {
	IS_ALL_MSK	= 0xbffffffful,	/* All Interrupt bits */
	IS_HW_ERR	= 1<<31,	/* Interrupt HW Error */
					/* Bit 30:	reserved */
	IS_PA_TO_RX1	= 1<<29,	/* Packet Arb Timeout Rx1 */
	IS_PA_TO_RX2	= 1<<28,	/* Packet Arb Timeout Rx2 */
	IS_PA_TO_TX1	= 1<<27,	/* Packet Arb Timeout Tx1 */
	IS_PA_TO_TX2	= 1<<26,	/* Packet Arb Timeout Tx2 */
	IS_I2C_READY	= 1<<25,	/* IRQ on end of I2C Tx */
	IS_IRQ_SW	= 1<<24,	/* SW forced IRQ	*/
	IS_EXT_REG	= 1<<23,	/* IRQ from LM80 or PHY (GENESIS only) */
					/* IRQ from PHY (YUKON only) */
	IS_TIMINT	= 1<<22,	/* IRQ from Timer	*/
	IS_MAC1		= 1<<21,	/* IRQ from MAC 1	*/
	IS_LNK_SYNC_M1	= 1<<20,	/* Link Sync Cnt wrap MAC 1 */
	IS_MAC2		= 1<<19,	/* IRQ from MAC 2	*/
	IS_LNK_SYNC_M2	= 1<<18,	/* Link Sync Cnt wrap MAC 2 */
/* Receive Queue 1 */
	IS_R1_B		= 1<<17,	/* Q_R1 End of Buffer */
	IS_R1_F		= 1<<16,	/* Q_R1 End of Frame */
	IS_R1_C		= 1<<15,	/* Q_R1 Encoding Error */
/* Receive Queue 2 */
	IS_R2_B		= 1<<14,	/* Q_R2 End of Buffer */
	IS_R2_F		= 1<<13,	/* Q_R2 End of Frame */
	IS_R2_C		= 1<<12,	/* Q_R2 Encoding Error */
/* Synchronous Transmit Queue 1 */
	IS_XS1_B	= 1<<11,	/* Q_XS1 End of Buffer */
	IS_XS1_F	= 1<<10,	/* Q_XS1 End of Frame */
	IS_XS1_C	= 1<<9,		/* Q_XS1 Encoding Error */
/* Asynchronous Transmit Queue 1 */
	IS_XA1_B	= 1<<8,		/* Q_XA1 End of Buffer */
	IS_XA1_F	= 1<<7,		/* Q_XA1 End of Frame */
	IS_XA1_C	= 1<<6,		/* Q_XA1 Encoding Error */
/* Synchronous Transmit Queue 2 */
	IS_XS2_B	= 1<<5,		/* Q_XS2 End of Buffer */
	IS_XS2_F	= 1<<4,		/* Q_XS2 End of Frame */
	IS_XS2_C	= 1<<3,		/* Q_XS2 Encoding Error */
/* Asynchronous Transmit Queue 2 */
	IS_XA2_B	= 1<<2,		/* Q_XA2 End of Buffer */
	IS_XA2_F	= 1<<1,		/* Q_XA2 End of Frame */
	IS_XA2_C	= 1<<0,		/* Q_XA2 Encoding Error */

	IS_TO_PORT1	= IS_PA_TO_RX1 | IS_PA_TO_TX1,
	IS_TO_PORT2	= IS_PA_TO_RX2 | IS_PA_TO_TX2,

	IS_PORT_1	= IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
	IS_PORT_2	= IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
};


/*	B2_IRQM_HWE_MSK	32 bit	IRQ Moderation HW Error Mask */
enum {
	IS_IRQ_TIST_OV	= 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
	IS_IRQ_SENSOR	= 1<<12, /* IRQ from Sensor (YUKON only) */
	IS_IRQ_MST_ERR	= 1<<11, /* IRQ master error detected */
	IS_IRQ_STAT	= 1<<10, /* IRQ status exception */
	IS_NO_STAT_M1	= 1<<9,	/* No Rx Status from MAC 1 */
	IS_NO_STAT_M2	= 1<<8,	/* No Rx Status from MAC 2 */
	IS_NO_TIST_M1	= 1<<7,	/* No Time Stamp from MAC 1 */
	IS_NO_TIST_M2	= 1<<6,	/* No Time Stamp from MAC 2 */
	IS_RAM_RD_PAR	= 1<<5,	/* RAM Read  Parity Error */
	IS_RAM_WR_PAR	= 1<<4,	/* RAM Write Parity Error */
	IS_M1_PAR_ERR	= 1<<3,	/* MAC 1 Parity Error */
	IS_M2_PAR_ERR	= 1<<2,	/* MAC 2 Parity Error */
	IS_R1_PAR_ERR	= 1<<1,	/* Queue R1 Parity Error */
	IS_R2_PAR_ERR	= 1<<0,	/* Queue R2 Parity Error */

	IS_ERR_MSK	= IS_IRQ_MST_ERR | IS_IRQ_STAT
			| IS_RAM_RD_PAR | IS_RAM_WR_PAR
			| IS_M1_PAR_ERR | IS_M2_PAR_ERR
			| IS_R1_PAR_ERR | IS_R2_PAR_ERR,
};

/*	B2_TST_CTRL1	 8 bit	Test Control Register 1 */
enum {
	TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
	TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
	TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
	TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
	TST_FRC_APERR_M	 = 1<<3, /* force ADDRPERR on MST */
	TST_FRC_APERR_T	 = 1<<2, /* force ADDRPERR on TRG */
	TST_CFG_WRITE_ON = 1<<1, /* Enable  Config Reg WR */
	TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
};

/*	B2_MAC_CFG		 8 bit	MAC Configuration / Chip Revision */
enum {
	CFG_CHIP_R_MSK	  = 0xf<<4,	/* Bit 7.. 4: Chip Revision */
					/* Bit 3.. 2:	reserved */
	CFG_DIS_M2_CLK	  = 1<<1,	/* Disable Clock for 2nd MAC */
	CFG_SNG_MAC	  = 1<<0,	/* MAC Config: 0=2 MACs / 1=1 MAC*/
};

/*	B2_CHIP_ID		 8 bit 	Chip Identification Number */
enum {
	CHIP_ID_GENESIS	   = 0x0a, /* Chip ID for GENESIS */
	CHIP_ID_YUKON	   = 0xb0, /* Chip ID for YUKON */
	CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
	CHIP_ID_YUKON_LP   = 0xb2, /* Chip ID for YUKON-LP */
	CHIP_ID_YUKON_XL   = 0xb3, /* Chip ID for YUKON-2 XL */
	CHIP_ID_YUKON_EC   = 0xb6, /* Chip ID for YUKON-2 EC */
 	CHIP_ID_YUKON_FE   = 0xb7, /* Chip ID for YUKON-2 FE */

	CHIP_REV_YU_LITE_A1  = 3,	/* Chip Rev. for YUKON-Lite A1,A2 */
	CHIP_REV_YU_LITE_A3  = 7,	/* Chip Rev. for YUKON-Lite A3 */
};

/*	B2_TI_CTRL		 8 bit	Timer control */
/*	B2_IRQM_CTRL	 8 bit	IRQ Moderation Timer Control */
enum {
	TIM_START	= 1<<2,	/* Start Timer */
	TIM_STOP	= 1<<1,	/* Stop  Timer */
	TIM_CLR_IRQ	= 1<<0,	/* Clear Timer IRQ (!IRQM) */
};

/*	B2_TI_TEST		 8 Bit	Timer Test */
/*	B2_IRQM_TEST	 8 bit	IRQ Moderation Timer Test */
/*	B28_DPT_TST		 8 bit	Descriptor Poll Timer Test Reg */
enum {
	TIM_T_ON	= 1<<2,	/* Test mode on */
	TIM_T_OFF	= 1<<1,	/* Test mode off */
	TIM_T_STEP	= 1<<0,	/* Test step */
};

/*	B2_GP_IO		32 bit	General Purpose I/O Register */
enum {
	GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
	GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
	GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
	GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
	GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
	GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
	GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
	GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
	GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
	GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */

	GP_IO_9	= 1<<9,	/* IO_9 pin */
	GP_IO_8	= 1<<8,	/* IO_8 pin */
	GP_IO_7	= 1<<7,	/* IO_7 pin */
	GP_IO_6	= 1<<6,	/* IO_6 pin */
	GP_IO_5	= 1<<5,	/* IO_5 pin */
	GP_IO_4	= 1<<4,	/* IO_4 pin */
	GP_IO_3	= 1<<3,	/* IO_3 pin */
	GP_IO_2	= 1<<2,	/* IO_2 pin */
	GP_IO_1	= 1<<1,	/* IO_1 pin */
	GP_IO_0	= 1<<0,	/* IO_0 pin */
};

/* Descriptor Bit Definition */
/*	TxCtrl		Transmit Buffer Control Field */
/*	RxCtrl		Receive  Buffer Control Field */
enum {
	BMU_OWN		= 1<<31, /* OWN bit: 0=host/1=BMU */
	BMU_STF		= 1<<30, /* Start of Frame */
	BMU_EOF		= 1<<29, /* End of Frame */
	BMU_IRQ_EOB	= 1<<28, /* Req "End of Buffer" IRQ */
	BMU_IRQ_EOF	= 1<<27, /* Req "End of Frame" IRQ */
				/* TxCtrl specific bits */
	BMU_STFWD	= 1<<26, /* (Tx)	Store & Forward Frame */
	BMU_NO_FCS	= 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
	BMU_SW	= 1<<24, /* (Tx)	1 bit res. for SW use */
				/* RxCtrl specific bits */
	BMU_DEV_0	= 1<<26, /* (Rx)	Transfer data to Dev0 */
	BMU_STAT_VAL	= 1<<25, /* (Rx)	Rx Status Valid */
	BMU_TIST_VAL	= 1<<24, /* (Rx)	Rx TimeStamp Valid */
			/* Bit 23..16:	BMU Check Opcodes */
	BMU_CHECK	= 0x55<<16, /* Default BMU check */