regs.h
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/***************************************************************************** * * * File: regs.h * * $Revision: 1.8 $ * * $Date: 2005/06/21 18:29:48 $ * * Description: * * part of the Chelsio 10Gb Ethernet Driver. * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License, version 2, as * * published by the Free Software Foundation. * * * * You should have received a copy of the GNU General Public License along * * with this program; if not, write to the Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * * * * http://www.chelsio.com * * * * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * * All rights reserved. * * * * Maintainers: maintainers@chelsio.com * * * * Authors: Dimitrios Michailidis <dm@chelsio.com> * * Tina Yang <tainay@chelsio.com> * * Felix Marti <felix@chelsio.com> * * Scott Bardone <sbardone@chelsio.com> * * Kurt Ottaway <kottaway@chelsio.com> * * Frank DiMambro <frank@chelsio.com> * * * * History: * * * ****************************************************************************/#ifndef _CXGB_REGS_H_#define _CXGB_REGS_H_/* SGE registers */#define A_SG_CONTROL 0x0#define S_CMDQ0_ENABLE 0#define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)#define F_CMDQ0_ENABLE V_CMDQ0_ENABLE(1U)#define S_CMDQ1_ENABLE 1#define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)#define F_CMDQ1_ENABLE V_CMDQ1_ENABLE(1U)#define S_FL0_ENABLE 2#define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)#define F_FL0_ENABLE V_FL0_ENABLE(1U)#define S_FL1_ENABLE 3#define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)#define F_FL1_ENABLE V_FL1_ENABLE(1U)#define S_CPL_ENABLE 4#define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)#define F_CPL_ENABLE V_CPL_ENABLE(1U)#define S_RESPONSE_QUEUE_ENABLE 5#define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)#define F_RESPONSE_QUEUE_ENABLE V_RESPONSE_QUEUE_ENABLE(1U)#define S_CMDQ_PRIORITY 6#define M_CMDQ_PRIORITY 0x3#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)#define S_DISABLE_CMDQ0_GTS 8#define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS)#define F_DISABLE_CMDQ0_GTS V_DISABLE_CMDQ0_GTS(1U)#define S_DISABLE_CMDQ1_GTS 9#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)#define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U)#define S_DISABLE_FL0_GTS 10#define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)#define F_DISABLE_FL0_GTS V_DISABLE_FL0_GTS(1U)#define S_DISABLE_FL1_GTS 11#define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)#define F_DISABLE_FL1_GTS V_DISABLE_FL1_GTS(1U)#define S_ENABLE_BIG_ENDIAN 12#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)#define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U)#define S_FL_SELECTION_CRITERIA 13#define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA)#define F_FL_SELECTION_CRITERIA V_FL_SELECTION_CRITERIA(1U)#define S_ISCSI_COALESCE 14#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)#define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U)#define S_RX_PKT_OFFSET 15#define M_RX_PKT_OFFSET 0x7#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)#define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET)#define S_VLAN_XTRACT 18#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)#define F_VLAN_XTRACT V_VLAN_XTRACT(1U)#define A_SG_DOORBELL 0x4#define A_SG_CMD0BASELWR 0x8#define A_SG_CMD0BASEUPR 0xc#define A_SG_CMD1BASELWR 0x10#define A_SG_CMD1BASEUPR 0x14#define A_SG_FL0BASELWR 0x18#define A_SG_FL0BASEUPR 0x1c#define A_SG_FL1BASELWR 0x20#define A_SG_FL1BASEUPR 0x24#define A_SG_CMD0SIZE 0x28#define S_CMDQ0_SIZE 0#define M_CMDQ0_SIZE 0x1ffff#define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE)#define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE)#define A_SG_FL0SIZE 0x2c#define S_FL0_SIZE 0#define M_FL0_SIZE 0x1ffff#define V_FL0_SIZE(x) ((x) << S_FL0_SIZE)#define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE)#define A_SG_RSPSIZE 0x30#define S_RESPQ_SIZE 0#define M_RESPQ_SIZE 0x1ffff#define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE)#define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE)#define A_SG_RSPBASELWR 0x34#define A_SG_RSPBASEUPR 0x38#define A_SG_FLTHRESHOLD 0x3c#define S_FL_THRESHOLD 0#define M_FL_THRESHOLD 0xffff#define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD)#define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD)#define A_SG_RSPQUEUECREDIT 0x40#define S_RESPQ_CREDIT 0#define M_RESPQ_CREDIT 0x1ffff#define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT)#define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT)#define A_SG_SLEEPING 0x48#define S_SLEEPING 0#define M_SLEEPING 0xffff#define V_SLEEPING(x) ((x) << S_SLEEPING)#define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING)#define A_SG_INTRTIMER 0x4c#define S_INTERRUPT_TIMER_COUNT 0#define M_INTERRUPT_TIMER_COUNT 0xffffff#define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT)#define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT)#define A_SG_CMD0PTR 0x50#define S_CMDQ0_POINTER 0#define M_CMDQ0_POINTER 0xffff#define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER)#define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER)#define S_CURRENT_GENERATION_BIT 16#define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT)#define F_CURRENT_GENERATION_BIT V_CURRENT_GENERATION_BIT(1U)#define A_SG_CMD1PTR 0x54#define S_CMDQ1_POINTER 0#define M_CMDQ1_POINTER 0xffff#define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER)#define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER)#define A_SG_FL0PTR 0x58#define S_FL0_POINTER 0#define M_FL0_POINTER 0xffff#define V_FL0_POINTER(x) ((x) << S_FL0_POINTER)#define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER)#define A_SG_FL1PTR 0x5c#define S_FL1_POINTER 0#define M_FL1_POINTER 0xffff#define V_FL1_POINTER(x) ((x) << S_FL1_POINTER)#define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER)#define A_SG_VERSION 0x6c#define S_DAY 0#define M_DAY 0x1f#define V_DAY(x) ((x) << S_DAY)#define G_DAY(x) (((x) >> S_DAY) & M_DAY)#define S_MONTH 5#define M_MONTH 0xf#define V_MONTH(x) ((x) << S_MONTH)#define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH)#define A_SG_CMD1SIZE 0xb0#define S_CMDQ1_SIZE 0#define M_CMDQ1_SIZE 0x1ffff#define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE)#define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE)#define A_SG_FL1SIZE 0xb4#define S_FL1_SIZE 0#define M_FL1_SIZE 0x1ffff#define V_FL1_SIZE(x) ((x) << S_FL1_SIZE)#define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE)#define A_SG_INT_ENABLE 0xb8#define S_RESPQ_EXHAUSTED 0#define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)#define F_RESPQ_EXHAUSTED V_RESPQ_EXHAUSTED(1U)#define S_RESPQ_OVERFLOW 1#define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)#define F_RESPQ_OVERFLOW V_RESPQ_OVERFLOW(1U)#define S_FL_EXHAUSTED 2#define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)#define F_FL_EXHAUSTED V_FL_EXHAUSTED(1U)#define S_PACKET_TOO_BIG 3#define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)#define F_PACKET_TOO_BIG V_PACKET_TOO_BIG(1U)#define S_PACKET_MISMATCH 4#define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)#define F_PACKET_MISMATCH V_PACKET_MISMATCH(1U)#define A_SG_INT_CAUSE 0xbc#define A_SG_RESPACCUTIMER 0xc0/* MC3 registers */#define A_MC3_CFG 0x100#define S_CLK_ENABLE 0#define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE)#define F_CLK_ENABLE V_CLK_ENABLE(1U)#define S_READY 1#define V_READY(x) ((x) << S_READY)#define F_READY V_READY(1U)#define S_READ_TO_WRITE_DELAY 2#define M_READ_TO_WRITE_DELAY 0x7#define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY)#define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY)#define S_WRITE_TO_READ_DELAY 5#define M_WRITE_TO_READ_DELAY 0x7#define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY)#define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY)#define S_MC3_BANK_CYCLE 8#define M_MC3_BANK_CYCLE 0xf#define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE)#define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE)#define S_REFRESH_CYCLE 12#define M_REFRESH_CYCLE 0xf#define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE)#define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE)#define S_PRECHARGE_CYCLE 16#define M_PRECHARGE_CYCLE 0x3#define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE)#define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE)#define S_ACTIVE_TO_READ_WRITE_DELAY 18#define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY)#define F_ACTIVE_TO_READ_WRITE_DELAY V_ACTIVE_TO_READ_WRITE_DELAY(1U)#define S_ACTIVE_TO_PRECHARGE_DELAY 19#define M_ACTIVE_TO_PRECHARGE_DELAY 0x7#define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY)#define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY)#define S_WRITE_RECOVERY_DELAY 22#define M_WRITE_RECOVERY_DELAY 0x3#define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY)#define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY)#define S_DENSITY 24#define M_DENSITY 0x3#define V_DENSITY(x) ((x) << S_DENSITY)#define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY)#define S_ORGANIZATION 26#define V_ORGANIZATION(x) ((x) << S_ORGANIZATION)#define F_ORGANIZATION V_ORGANIZATION(1U)#define S_BANKS 27#define V_BANKS(x) ((x) << S_BANKS)#define F_BANKS V_BANKS(1U)#define S_UNREGISTERED 28#define V_UNREGISTERED(x) ((x) << S_UNREGISTERED)#define F_UNREGISTERED V_UNREGISTERED(1U)#define S_MC3_WIDTH 29#define M_MC3_WIDTH 0x3#define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH)#define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH)#define S_MC3_SLOW 31#define V_MC3_SLOW(x) ((x) << S_MC3_SLOW)#define F_MC3_SLOW V_MC3_SLOW(1U)#define A_MC3_MODE 0x104#define S_MC3_MODE 0#define M_MC3_MODE 0x3fff#define V_MC3_MODE(x) ((x) << S_MC3_MODE)#define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE)#define S_BUSY 31#define V_BUSY(x) ((x) << S_BUSY)#define F_BUSY V_BUSY(1U)#define A_MC3_EXT_MODE 0x108#define S_MC3_EXTENDED_MODE 0#define M_MC3_EXTENDED_MODE 0x3fff#define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE)#define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE)#define A_MC3_PRECHARG 0x10c#define A_MC3_REFRESH 0x110#define S_REFRESH_ENABLE 0#define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE)#define F_REFRESH_ENABLE V_REFRESH_ENABLE(1U)#define S_REFRESH_DIVISOR 1#define M_REFRESH_DIVISOR 0x3fff#define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR)#define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR)#define A_MC3_STROBE 0x114#define S_MASTER_DLL_RESET 0#define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET)#define F_MASTER_DLL_RESET V_MASTER_DLL_RESET(1U)#define S_MASTER_DLL_TAP_COUNT 1#define M_MASTER_DLL_TAP_COUNT 0xff#define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT)#define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT)#define S_MASTER_DLL_LOCKED 9#define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED)#define F_MASTER_DLL_LOCKED V_MASTER_DLL_LOCKED(1U)#define S_MASTER_DLL_MAX_TAP_COUNT 10#define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT)#define F_MASTER_DLL_MAX_TAP_COUNT V_MASTER_DLL_MAX_TAP_COUNT(1U)#define S_MASTER_DLL_TAP_COUNT_OFFSET 11#define M_MASTER_DLL_TAP_COUNT_OFFSET 0x3f#define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET)⌨️ 快捷键说明
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