vsc7326.c

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/* $Date: 2006/04/28 19:20:06 $ $RCSfile: vsc7326.c,v $ $Revision: 1.19 $ */

/* Driver for Vitesse VSC7326 (Schaumburg) MAC */

#include "gmac.h"
#include "elmer0.h"
#include "vsc7326_reg.h"

/* Update fast changing statistics every 15 seconds */
#define STATS_TICK_SECS 15
/* 30 minutes for full statistics update */
#define MAJOR_UPDATE_TICKS (1800 / STATS_TICK_SECS)

#define MAX_MTU 9600

/* The egress WM value 0x01a01fff should be used only when the
 * interface is down (MAC port disabled). This is a workaround
 * for disabling the T2/MAC flow-control. When the interface is
 * enabled, the WM value should be set to 0x014a03F0.
 */
#define WM_DISABLE	0x01a01fff
#define WM_ENABLE	0x014a03F0

struct init_table {
	u32 addr;
	u32 data;
};

struct _cmac_instance {
	u32 index;
	u32 ticks;
};

#define INITBLOCK_SLEEP	0xffffffff

static void vsc_read(adapter_t *adapter, u32 addr, u32 *val)
{
	u32 status, vlo, vhi;
	int i;

	spin_lock_bh(&adapter->mac_lock);
	t1_tpi_read(adapter, (addr << 2) + 4, &vlo);
	i = 0;
	do {
		t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo);
		t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi);
		status = (vhi << 16) | vlo;
		i++;
	} while (((status & 1) == 0) && (i < 50));
	if (i == 50)
		CH_ERR("Invalid tpi read from MAC, breaking loop.\n");

	t1_tpi_read(adapter, (REG_LOCAL_DATA << 2) + 4, &vlo);
	t1_tpi_read(adapter, REG_LOCAL_DATA << 2, &vhi);

	*val = (vhi << 16) | vlo;

	/* CH_ERR("rd: block: 0x%x  sublock: 0x%x  reg: 0x%x  data: 0x%x\n",
		((addr&0xe000)>>13), ((addr&0x1e00)>>9),
		((addr&0x01fe)>>1), *val); */
	spin_unlock_bh(&adapter->mac_lock);
}

static void vsc_write(adapter_t *adapter, u32 addr, u32 data)
{
	spin_lock_bh(&adapter->mac_lock);
	t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF);
	t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF);
	/* CH_ERR("wr: block: 0x%x  sublock: 0x%x  reg: 0x%x  data: 0x%x\n",
		((addr&0xe000)>>13), ((addr&0x1e00)>>9),
		((addr&0x01fe)>>1), data); */
	spin_unlock_bh(&adapter->mac_lock);
}

/* Hard reset the MAC.  This wipes out *all* configuration. */
static void vsc7326_full_reset(adapter_t* adapter)
{
	u32 val;
	u32 result = 0xffff;

	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	val &= ~1;
	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	udelay(2);
	val |= 0x1;	/* Enable mac MAC itself */
	val |= 0x800;	/* Turn off the red LED */
	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	mdelay(1);
	vsc_write(adapter, REG_SW_RESET, 0x80000001);
	do {
		mdelay(1);
		vsc_read(adapter, REG_SW_RESET, &result);
	} while (result != 0x0);
}

static struct init_table vsc7326_reset[] = {
	{      REG_IFACE_MODE, 0x00000000 },
	{         REG_CRC_CFG, 0x00000020 },
	{   REG_PLL_CLK_SPEED, 0x00050c00 },
	{   REG_PLL_CLK_SPEED, 0x00050c00 },
	{            REG_MSCH, 0x00002f14 },
	{       REG_SPI4_MISC, 0x00040409 },
	{     REG_SPI4_DESKEW, 0x00080000 },
	{ REG_SPI4_ING_SETUP2, 0x08080004 },
	{ REG_SPI4_ING_SETUP0, 0x04111004 },
	{ REG_SPI4_EGR_SETUP0, 0x80001a04 },
	{ REG_SPI4_ING_SETUP1, 0x02010000 },
	{      REG_AGE_INC(0), 0x00000000 },
	{      REG_AGE_INC(1), 0x00000000 },
	{     REG_ING_CONTROL, 0x0a200011 },
	{     REG_EGR_CONTROL, 0xa0010091 },
};

static struct init_table vsc7326_portinit[4][22] = {
	{	/* Port 0 */
			/* FIFO setup */
		{           REG_DBG(0), 0x000004f0 },
		{           REG_HDX(0), 0x00073101 },
		{        REG_TEST(0,0), 0x00000022 },
		{        REG_TEST(1,0), 0x00000022 },
		{  REG_TOP_BOTTOM(0,0), 0x003f0000 },
		{  REG_TOP_BOTTOM(1,0), 0x00120000 },
		{ REG_HIGH_LOW_WM(0,0), 0x07460757 },
		{ REG_HIGH_LOW_WM(1,0), WM_DISABLE },
		{   REG_CT_THRHLD(0,0), 0x00000000 },
		{   REG_CT_THRHLD(1,0), 0x00000000 },
		{         REG_BUCKE(0), 0x0002ffff },
		{         REG_BUCKI(0), 0x0002ffff },
		{        REG_TEST(0,0), 0x00000020 },
		{        REG_TEST(1,0), 0x00000020 },
			/* Port config */
		{       REG_MAX_LEN(0), 0x00002710 },
		{     REG_PORT_FAIL(0), 0x00000002 },
		{    REG_NORMALIZER(0), 0x00000a64 },
		{        REG_DENORM(0), 0x00000010 },
		{     REG_STICK_BIT(0), 0x03baa370 },
		{     REG_DEV_SETUP(0), 0x00000083 },
		{     REG_DEV_SETUP(0), 0x00000082 },
		{      REG_MODE_CFG(0), 0x0200259f },
	},
	{	/* Port 1 */
			/* FIFO setup */
		{           REG_DBG(1), 0x000004f0 },
		{           REG_HDX(1), 0x00073101 },
		{        REG_TEST(0,1), 0x00000022 },
		{        REG_TEST(1,1), 0x00000022 },
		{  REG_TOP_BOTTOM(0,1), 0x007e003f },
		{  REG_TOP_BOTTOM(1,1), 0x00240012 },
		{ REG_HIGH_LOW_WM(0,1), 0x07460757 },
		{ REG_HIGH_LOW_WM(1,1), WM_DISABLE },
		{   REG_CT_THRHLD(0,1), 0x00000000 },
		{   REG_CT_THRHLD(1,1), 0x00000000 },
		{         REG_BUCKE(1), 0x0002ffff },
		{         REG_BUCKI(1), 0x0002ffff },
		{        REG_TEST(0,1), 0x00000020 },
		{        REG_TEST(1,1), 0x00000020 },
			/* Port config */
		{       REG_MAX_LEN(1), 0x00002710 },
		{     REG_PORT_FAIL(1), 0x00000002 },
		{    REG_NORMALIZER(1), 0x00000a64 },
		{        REG_DENORM(1), 0x00000010 },
		{     REG_STICK_BIT(1), 0x03baa370 },
		{     REG_DEV_SETUP(1), 0x00000083 },
		{     REG_DEV_SETUP(1), 0x00000082 },
		{      REG_MODE_CFG(1), 0x0200259f },
	},
	{	/* Port 2 */
			/* FIFO setup */
		{           REG_DBG(2), 0x000004f0 },
		{           REG_HDX(2), 0x00073101 },
		{        REG_TEST(0,2), 0x00000022 },
		{        REG_TEST(1,2), 0x00000022 },
		{  REG_TOP_BOTTOM(0,2), 0x00bd007e },
		{  REG_TOP_BOTTOM(1,2), 0x00360024 },
		{ REG_HIGH_LOW_WM(0,2), 0x07460757 },
		{ REG_HIGH_LOW_WM(1,2), WM_DISABLE },
		{   REG_CT_THRHLD(0,2), 0x00000000 },
		{   REG_CT_THRHLD(1,2), 0x00000000 },
		{         REG_BUCKE(2), 0x0002ffff },
		{         REG_BUCKI(2), 0x0002ffff },
		{        REG_TEST(0,2), 0x00000020 },
		{        REG_TEST(1,2), 0x00000020 },
			/* Port config */
		{       REG_MAX_LEN(2), 0x00002710 },
		{     REG_PORT_FAIL(2), 0x00000002 },
		{    REG_NORMALIZER(2), 0x00000a64 },
		{        REG_DENORM(2), 0x00000010 },
		{     REG_STICK_BIT(2), 0x03baa370 },
		{     REG_DEV_SETUP(2), 0x00000083 },
		{     REG_DEV_SETUP(2), 0x00000082 },
		{      REG_MODE_CFG(2), 0x0200259f },
	},
	{	/* Port 3 */
			/* FIFO setup */
		{           REG_DBG(3), 0x000004f0 },
		{           REG_HDX(3), 0x00073101 },
		{        REG_TEST(0,3), 0x00000022 },
		{        REG_TEST(1,3), 0x00000022 },
		{  REG_TOP_BOTTOM(0,3), 0x00fc00bd },
		{  REG_TOP_BOTTOM(1,3), 0x00480036 },
		{ REG_HIGH_LOW_WM(0,3), 0x07460757 },
		{ REG_HIGH_LOW_WM(1,3), WM_DISABLE },
		{   REG_CT_THRHLD(0,3), 0x00000000 },
		{   REG_CT_THRHLD(1,3), 0x00000000 },
		{         REG_BUCKE(3), 0x0002ffff },
		{         REG_BUCKI(3), 0x0002ffff },
		{        REG_TEST(0,3), 0x00000020 },
		{        REG_TEST(1,3), 0x00000020 },
			/* Port config */
		{       REG_MAX_LEN(3), 0x00002710 },
		{     REG_PORT_FAIL(3), 0x00000002 },
		{    REG_NORMALIZER(3), 0x00000a64 },
		{        REG_DENORM(3), 0x00000010 },
		{     REG_STICK_BIT(3), 0x03baa370 },
		{     REG_DEV_SETUP(3), 0x00000083 },
		{     REG_DEV_SETUP(3), 0x00000082 },
		{      REG_MODE_CFG(3), 0x0200259f },
	},
};

static void run_table(adapter_t *adapter, struct init_table *ib, int len)
{
	int i;

	for (i = 0; i < len; i++) {
		if (ib[i].addr == INITBLOCK_SLEEP) {
			udelay( ib[i].data );
			CH_ERR("sleep %d us\n",ib[i].data);
		} else
			vsc_write( adapter, ib[i].addr, ib[i].data );
	}
}

static int bist_rd(adapter_t *adapter, int moduleid, int address)
{
	int data = 0;
	u32 result = 0;

	if ((address != 0x0) &&
	    (address != 0x1) &&
	    (address != 0x2) &&
	    (address != 0xd) &&
	    (address != 0xe))
			CH_ERR("No bist address: 0x%x\n", address);

	data = ((0x00 << 24) | ((address & 0xff) << 16) | (0x00 << 8) |
		((moduleid & 0xff) << 0));
	vsc_write(adapter, REG_RAM_BIST_CMD, data);

	udelay(10);

	vsc_read(adapter, REG_RAM_BIST_RESULT, &result);
	if ((result & (1 << 9)) != 0x0)
		CH_ERR("Still in bist read: 0x%x\n", result);
	else if ((result & (1 << 8)) != 0x0)
		CH_ERR("bist read error: 0x%x\n", result);

	return (result & 0xff);
}

static int bist_wr(adapter_t *adapter, int moduleid, int address, int value)
{
	int data = 0;
	u32 result = 0;

	if ((address != 0x0) &&
	    (address != 0x1) &&
	    (address != 0x2) &&
	    (address != 0xd) &&
	    (address != 0xe))
			CH_ERR("No bist address: 0x%x\n", address);

	if (value > 255)
		CH_ERR("Suspicious write out of range value: 0x%x\n", value);

	data = ((0x01 << 24) | ((address & 0xff) << 16) | (value << 8) |
		((moduleid & 0xff) << 0));
	vsc_write(adapter, REG_RAM_BIST_CMD, data);

	udelay(5);

	vsc_read(adapter, REG_RAM_BIST_CMD, &result);
	if ((result & (1 << 27)) != 0x0)
		CH_ERR("Still in bist write: 0x%x\n", result);
	else if ((result & (1 << 26)) != 0x0)
		CH_ERR("bist write error: 0x%x\n", result);

	return 0;
}

static int run_bist(adapter_t *adapter, int moduleid)
{
	/*run bist*/
	(void) bist_wr(adapter,moduleid, 0x00, 0x02);
	(void) bist_wr(adapter,moduleid, 0x01, 0x01);

	return 0;
}

static int check_bist(adapter_t *adapter, int moduleid)
{
	int result=0;
	int column=0;
	/*check bist*/
	result = bist_rd(adapter,moduleid, 0x02);
	column = ((bist_rd(adapter,moduleid, 0x0e)<<8) +
			(bist_rd(adapter,moduleid, 0x0d)));
	if ((result & 3) != 0x3)
		CH_ERR("Result: 0x%x  BIST error in ram %d, column: 0x%04x\n",
			result, moduleid, column);
	return 0;
}

static int enable_mem(adapter_t *adapter, int moduleid)
{
	/*enable mem*/
	(void) bist_wr(adapter,moduleid, 0x00, 0x00);
	return 0;
}

static int run_bist_all(adapter_t *adapter)
{
	int port = 0;
	u32 val = 0;

	vsc_write(adapter, REG_MEM_BIST, 0x5);
	vsc_read(adapter, REG_MEM_BIST, &val);

	for (port = 0; port < 12; port++)
		vsc_write(adapter, REG_DEV_SETUP(port), 0x0);

	udelay(300);
	vsc_write(adapter, REG_SPI4_MISC, 0x00040409);
	udelay(300);

	(void) run_bist(adapter,13);
	(void) run_bist(adapter,14);
	(void) run_bist(adapter,20);
	(void) run_bist(adapter,21);
	mdelay(200);
	(void) check_bist(adapter,13);
	(void) check_bist(adapter,14);
	(void) check_bist(adapter,20);
	(void) check_bist(adapter,21);
	udelay(100);
	(void) enable_mem(adapter,13);
	(void) enable_mem(adapter,14);
	(void) enable_mem(adapter,20);
	(void) enable_mem(adapter,21);
	udelay(300);
	vsc_write(adapter, REG_SPI4_MISC, 0x60040400);
	udelay(300);
	for (port = 0; port < 12; port++)
		vsc_write(adapter, REG_DEV_SETUP(port), 0x1);

	udelay(300);
	vsc_write(adapter, REG_MEM_BIST, 0x0);
	mdelay(10);
	return 0;
}

static int mac_intr_handler(struct cmac *mac)
{
	return 0;
}