adm8211.h

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#define SI4126_RF1_R_DIV	6 /* only Si4136 */
#define SI4126_RF2_R_DIV	7
#define SI4126_IF_R_DIV		8

/* Main Configuration */
#define SI4126_MAIN_XINDIV2	(1 << 6)
#define SI4126_MAIN_IFDIV	((1 << 11) | (1 << 10))
/* Powerdown */
#define SI4126_POWERDOWN_PDIB	(1 << 1)
#define SI4126_POWERDOWN_PDRB	(1 << 0)


/* RF3000 BBP - Control Port Registers */
/* 0x00 - reserved */
#define RF3000_MODEM_CTRL__RX_STATUS 0x01
#define RF3000_CCA_CTRL 0x02
#define RF3000_DIVERSITY__RSSI 0x03
#define RF3000_RX_SIGNAL_FIELD 0x04
#define RF3000_RX_LEN_MSB 0x05
#define RF3000_RX_LEN_LSB 0x06
#define RF3000_RX_SERVICE_FIELD 0x07
#define RF3000_TX_VAR_GAIN__TX_LEN_EXT 0x11
#define RF3000_TX_LEN_MSB 0x12
#define RF3000_TX_LEN_LSB 0x13
#define RF3000_LOW_GAIN_CALIB 0x14
#define RF3000_HIGH_GAIN_CALIB 0x15

/* ADM8211 revisions */
#define ADM8211_REV_AB 0x11
#define ADM8211_REV_AF 0x15
#define ADM8211_REV_BA 0x20
#define ADM8211_REV_CA 0x30

struct adm8211_desc {
	__le32 status;
	__le32 length;
	__le32 buffer1;
	__le32 buffer2;
};

#define RDES0_STATUS_OWN	(1 << 31)
#define RDES0_STATUS_ES		(1 << 30)
#define RDES0_STATUS_SQL	(1 << 29)
#define RDES0_STATUS_DE		(1 << 28)
#define RDES0_STATUS_FS		(1 << 27)
#define RDES0_STATUS_LS		(1 << 26)
#define RDES0_STATUS_PCF	(1 << 25)
#define RDES0_STATUS_SFDE	(1 << 24)
#define RDES0_STATUS_SIGE	(1 << 23)
#define RDES0_STATUS_CRC16E	(1 << 22)
#define RDES0_STATUS_RXTOE	(1 << 21)
#define RDES0_STATUS_CRC32E	(1 << 20)
#define RDES0_STATUS_ICVE	(1 << 19)
#define RDES0_STATUS_DA1	(1 << 17)
#define RDES0_STATUS_DA0	(1 << 16)
#define RDES0_STATUS_RXDR	((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12))
#define RDES0_STATUS_FL		(0x00000fff)

#define RDES1_CONTROL_RER	(1 << 25)
#define RDES1_CONTROL_RCH	(1 << 24)
#define RDES1_CONTROL_RBS2	(0x00fff000)
#define RDES1_CONTROL_RBS1	(0x00000fff)

#define RDES1_STATUS_RSSI	(0x0000007f)


#define TDES0_CONTROL_OWN	(1 << 31)
#define TDES0_CONTROL_DONE	(1 << 30)
#define TDES0_CONTROL_TXDR	(0x0ff00000)

#define TDES0_STATUS_OWN	(1 << 31)
#define TDES0_STATUS_DONE	(1 << 30)
#define TDES0_STATUS_ES		(1 << 29)
#define TDES0_STATUS_TLT	(1 << 28)
#define TDES0_STATUS_TRT	(1 << 27)
#define TDES0_STATUS_TUF	(1 << 26)
#define TDES0_STATUS_TRO	(1 << 25)
#define TDES0_STATUS_SOFBR	(1 << 24)
#define TDES0_STATUS_ACR	(0x00000fff)

#define TDES1_CONTROL_IC	(1 << 31)
#define TDES1_CONTROL_LS	(1 << 30)
#define TDES1_CONTROL_FS	(1 << 29)
#define TDES1_CONTROL_TER	(1 << 25)
#define TDES1_CONTROL_TCH	(1 << 24)
#define TDES1_CONTROL_RBS2	(0x00fff000)
#define TDES1_CONTROL_RBS1	(0x00000fff)

/* SRAM offsets */
#define ADM8211_SRAM(x) (priv->pdev->revision < ADM8211_REV_BA ? \
        ADM8211_SRAM_A_ ## x : ADM8211_SRAM_B_ ## x)

#define ADM8211_SRAM_INDIV_KEY   0x0000
#define ADM8211_SRAM_A_SHARE_KEY 0x0160
#define ADM8211_SRAM_B_SHARE_KEY 0x00c0

#define ADM8211_SRAM_A_SSID      0x0180
#define ADM8211_SRAM_B_SSID      0x00d4
#define ADM8211_SRAM_SSID ADM8211_SRAM(SSID)

#define ADM8211_SRAM_A_SUPP_RATE 0x0191
#define ADM8211_SRAM_B_SUPP_RATE 0x00dd
#define ADM8211_SRAM_SUPP_RATE ADM8211_SRAM(SUPP_RATE)

#define ADM8211_SRAM_A_SIZE      0x0200
#define ADM8211_SRAM_B_SIZE      0x01c0
#define ADM8211_SRAM_SIZE ADM8211_SRAM(SIZE)

struct adm8211_rx_ring_info {
	struct sk_buff *skb;
	dma_addr_t mapping;
};

struct adm8211_tx_ring_info {
	struct sk_buff *skb;
	dma_addr_t mapping;
	struct ieee80211_tx_control tx_control;
	size_t hdrlen;
};

#define PLCP_SIGNAL_1M		0x0a
#define PLCP_SIGNAL_2M		0x14
#define PLCP_SIGNAL_5M5		0x37
#define PLCP_SIGNAL_11M		0x6e

struct adm8211_tx_hdr {
	u8 da[6];
	u8 signal; /* PLCP signal / TX rate in 100 Kbps */
	u8 service;
	__le16 frame_body_size;
	__le16 frame_control;
	__le16 plcp_frag_tail_len;
	__le16 plcp_frag_head_len;
	__le16 dur_frag_tail;
	__le16 dur_frag_head;
	u8 addr4[6];

#define ADM8211_TXHDRCTL_SHORT_PREAMBLE		(1 <<  0)
#define ADM8211_TXHDRCTL_MORE_FRAG		(1 <<  1)
#define ADM8211_TXHDRCTL_MORE_DATA		(1 <<  2)
#define ADM8211_TXHDRCTL_FRAG_NO		(1 <<  3) /* ? */
#define ADM8211_TXHDRCTL_ENABLE_RTS		(1 <<  4)
#define ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE	(1 <<  5)
#define ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER	(1 << 15) /* ? */
	__le16 header_control;
	__le16 frag;
	u8 reserved_0;
	u8 retry_limit;

	u32 wep2key0;
	u32 wep2key1;
	u32 wep2key2;
	u32 wep2key3;

	u8 keyid;
	u8 entry_control;	// huh??
	u16 reserved_1;
	u32 reserved_2;
} __attribute__ ((packed));


#define RX_COPY_BREAK 128
#define RX_PKT_SIZE 2500

struct adm8211_eeprom {
	__le16	signature;		/* 0x00 */
	u8	major_version;		/* 0x02 */
	u8	minor_version;		/* 0x03 */
	u8	reserved_1[4];		/* 0x04 */
	u8	hwaddr[6];		/* 0x08 */
	u8	reserved_2[8];		/* 0x1E */
	__le16	cr49;			/* 0x16 */
	u8	cr03;			/* 0x18 */
	u8	cr28;			/* 0x19 */
	u8	cr29;			/* 0x1A */
	u8	country_code;		/* 0x1B */

/* specific bbp types */
#define ADM8211_BBP_RFMD3000	0x00
#define ADM8211_BBP_RFMD3002	0x01
#define ADM8211_BBP_ADM8011	0x04
	u8	specific_bbptype;	/* 0x1C */
	u8	specific_rftype;	/* 0x1D */
	u8	reserved_3[2];		/* 0x1E */
	__le16	device_id;		/* 0x20 */
	__le16	vendor_id;		/* 0x22 */
	__le16	subsystem_id;		/* 0x24 */
	__le16	subsystem_vendor_id;	/* 0x26 */
	u8	maxlat;			/* 0x28 */
	u8	mingnt;			/* 0x29 */
	__le16	cis_pointer_low;	/* 0x2A */
	__le16	cis_pointer_high;	/* 0x2C */
	__le16	csr18;			/* 0x2E */
	u8	reserved_4[16];		/* 0x30 */
	u8	d1_pwrdara;		/* 0x40 */
	u8	d0_pwrdara;		/* 0x41 */
	u8	d3_pwrdara;		/* 0x42 */
	u8	d2_pwrdara;		/* 0x43 */
	u8	antenna_power[14];	/* 0x44 */
	__le16	cis_wordcnt;		/* 0x52 */
	u8	tx_power[14];		/* 0x54 */
	u8	lpf_cutoff[14];		/* 0x62 */
	u8	lnags_threshold[14];	/* 0x70 */
	__le16	checksum;		/* 0x7E */
	u8	cis_data[0];		/* 0x80, 384 bytes */
} __attribute__ ((packed));

static const struct ieee80211_rate adm8211_rates[] = {
	{ .rate = 10,
	  .val = 10,
	  .val2 = -10,
	  .flags = IEEE80211_RATE_CCK_2 },
	{ .rate = 20,
	  .val = 20,
	  .val2 = -20,
	  .flags = IEEE80211_RATE_CCK_2 },
	{ .rate = 55,
	  .val = 55,
	  .val2 = -55,
	  .flags = IEEE80211_RATE_CCK_2 },
	{ .rate = 110,
	  .val = 110,
	  .val2 = -110,
	  .flags = IEEE80211_RATE_CCK_2 }
};

struct ieee80211_chan_range {
	u8 min;
	u8 max;
};

static const struct ieee80211_channel adm8211_channels[] = {
	{ .chan = 1,
	  .freq = 2412},
	{ .chan = 2,
	  .freq = 2417},
	{ .chan = 3,
	  .freq = 2422},
	{ .chan = 4,
	  .freq = 2427},
	{ .chan = 5,
	  .freq = 2432},
	{ .chan = 6,
	  .freq = 2437},
	{ .chan = 7,
	  .freq = 2442},
	{ .chan = 8,
	  .freq = 2447},
	{ .chan = 9,
	  .freq = 2452},
	{ .chan = 10,
	  .freq = 2457},
	{ .chan = 11,
	  .freq = 2462},
	{ .chan = 12,
	  .freq = 2467},
	{ .chan = 13,
	  .freq = 2472},
	{ .chan = 14,
	  .freq = 2484},
};

struct adm8211_priv {
	struct pci_dev *pdev;
	spinlock_t lock;
	struct adm8211_csr __iomem *map;
	struct adm8211_desc *rx_ring;
	struct adm8211_desc *tx_ring;
	dma_addr_t rx_ring_dma;
	dma_addr_t tx_ring_dma;
	struct adm8211_rx_ring_info *rx_buffers;
	struct adm8211_tx_ring_info *tx_buffers;
	unsigned int rx_ring_size, tx_ring_size;
	unsigned int cur_tx, dirty_tx, cur_rx;

	struct ieee80211_low_level_stats stats;
	struct ieee80211_hw_mode modes[1];
	struct ieee80211_channel channels[ARRAY_SIZE(adm8211_channels)];
	struct ieee80211_rate rates[ARRAY_SIZE(adm8211_rates)];
	int mode;

	int channel;
	u8 bssid[ETH_ALEN];
	u8 ssid[32];
	size_t ssid_len;

	u8 soft_rx_crc;
	u8 retry_limit;

	u8 ant_power;
	u8 tx_power;
	u8 lpf_cutoff;
	u8 lnags_threshold;
	struct adm8211_eeprom *eeprom;
	size_t eeprom_len;

	u32 nar;

#define ADM8211_TYPE_INTERSIL	0x00
#define ADM8211_TYPE_RFMD	0x01
#define ADM8211_TYPE_MARVEL	0x02
#define ADM8211_TYPE_AIROHA	0x03
#define ADM8211_TYPE_ADMTEK     0x05
	unsigned int rf_type:3;
	unsigned int bbp_type:3;

	u8 specific_bbptype;
	enum {
		ADM8211_RFMD2948 = 0x0,
		ADM8211_RFMD2958 = 0x1,
		ADM8211_RFMD2958_RF3000_CONTROL_POWER = 0x2,
		ADM8211_MAX2820 = 0x8,
		ADM8211_AL2210L = 0xC,	/* Airoha */
	} transceiver_type;
};

static const struct ieee80211_chan_range cranges[] = {
	{1,  11},	/* FCC */
	{1,  11},	/* IC */
	{1,  13},	/* ETSI */
	{10, 11},	/* SPAIN */
	{10, 13},	/* FRANCE */
	{14, 14},	/* MMK */
	{1,  14},	/* MMK2 */
};

#endif /* ADM8211_H */