saa9730.h

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#define TX_STATUS_TX_COLL_SHF           0
#define TX_STATUS_TX_COLL_MSK           (0xf << TX_STATUS_TX_COLL_SHF)

/* RECEIVE CONTROL register. */
#define RX_CTL_EN_GOOD                  0x00004000
#define RX_CTL_EN_RX_PAR                0x00002000
#define RX_CTL_EN_LONG_ERR              0x00000800
#define RX_CTL_EN_OVER                  0x00000400
#define RX_CTL_EN_CRC_ERR               0x00000200
#define RX_CTL_EN_ALIGN                 0x00000100
#define RX_CTL_IGNORE_CRC               0x00000040
#define RX_CTL_PASS_CTL                 0x00000020
#define RX_CTL_STRIP_CRC                0x00000010
#define RX_CTL_SHORT_EN                 0x00000008
#define RX_CTL_LONG_EN                  0x00000004
#define RX_CTL_RX_HALT                  0x00000002
#define RX_CTL_RX_EN                    0x00000001

/* RECEIVE STATUS register. */
#define RX_STATUS_RX_HALTED             0x00008000
#define RX_STATUS_GOOD                  0x00004000
#define RX_STATUS_RX_PAR                0x00002000
#define RX_STATUS_LONG_ERR              0x00000800
#define RX_STATUS_OVERFLOW              0x00000400
#define RX_STATUS_CRC_ERR               0x00000200
#define RX_STATUS_ALIGN_ERR             0x00000100
#define RX_STATUS_RX10_STAT             0x00000080
#define RX_STATUS_INT_RX                0x00000040
#define RX_STATUS_CTL_RECD              0x00000020

/* MD_CA register. */
#define MD_CA_PRE_SUP                   0x00001000
#define MD_CA_BUSY                      0x00000800
#define MD_CA_WR                        0x00000400
#define MD_CA_PHY_SHF                   5
#define MD_CA_PHY_MSK                   (0x1f << MD_CA_PHY_SHF)
#define MD_CA_ADDR_SHF                  0
#define MD_CA_ADDR_MSK                  (0x1f << MD_CA_ADDR_SHF)

/* Tx Status/Control. */
#define TX_STAT_CTL_OWNER_SHF           30
#define TX_STAT_CTL_OWNER_MSK           (0x3 << TX_STAT_CTL_OWNER_SHF)
#define TX_STAT_CTL_FRAME_SHF           27
#define TX_STAT_CTL_FRAME_MSK           (0x7 << TX_STAT_CTL_FRAME_SHF)
#define TX_STAT_CTL_STATUS_SHF          11
#define TX_STAT_CTL_STATUS_MSK          (0x1ffff << TX_STAT_CTL_STATUS_SHF)
#define TX_STAT_CTL_LENGTH_SHF          0
#define TX_STAT_CTL_LENGTH_MSK          (0x7ff << TX_STAT_CTL_LENGTH_SHF)

#define TX_STAT_CTL_ERROR_MSK           ((TX_STATUS_SQ_ERR      |     \
					  TX_STATUS_TX_HALTED   |     \
					  TX_STATUS_TX_PAR      |     \
					  TX_STATUS_LATE_COLL   |     \
					  TX_STATUS_L_CARR      |     \
					  TX_STATUS_EX_DEFER    |     \
					  TX_STATUS_UNDER       |     \
					  TX_STATUS_PAUSED      |     \
					  TX_STATUS_TX_DEFERRED |     \
					  TX_STATUS_EX_COLL     |     \
					  TX_STATUS_TX_COLL_MSK)      \
                                                    << TX_STAT_CTL_STATUS_SHF)
#define TX_STAT_CTL_INT_AFTER_TX        0x4

/* Rx Status/Control. */
#define RX_STAT_CTL_OWNER_SHF           30
#define RX_STAT_CTL_OWNER_MSK           (0x3 << RX_STAT_CTL_OWNER_SHF)
#define RX_STAT_CTL_STATUS_SHF          11
#define RX_STAT_CTL_STATUS_MSK          (0xffff << RX_STAT_CTL_STATUS_SHF)
#define RX_STAT_CTL_LENGTH_SHF          0
#define RX_STAT_CTL_LENGTH_MSK          (0x7ff << RX_STAT_CTL_LENGTH_SHF)



/* The SAA9730 (LAN) controller register map, as seen via the PCI-bus. */
#define SAA9730_LAN_REGS_ADDR   0x20400
#define SAA9730_LAN_REGS_SIZE   0x00400

struct lan_saa9730_regmap {
	volatile unsigned int TxBuffA;			/* 0x20400 */
	volatile unsigned int TxBuffB;			/* 0x20404 */
	volatile unsigned int RxBuffA;			/* 0x20408 */
	volatile unsigned int RxBuffB;			/* 0x2040c */
	volatile unsigned int PacketCount;		/* 0x20410 */
	volatile unsigned int Ok2Use;			/* 0x20414 */
	volatile unsigned int LanDmaCtl;		/* 0x20418 */
	volatile unsigned int Timeout;			/* 0x2041c */
	volatile unsigned int DmaStatus;		/* 0x20420 */
	volatile unsigned int DmaTest;			/* 0x20424 */
	volatile unsigned char filler20428[0x20430 - 0x20428];
	volatile unsigned int PauseCount;		/* 0x20430 */
	volatile unsigned int RemotePauseCount;		/* 0x20434 */
	volatile unsigned char filler20438[0x20440 - 0x20438];
	volatile unsigned int MacCtl;			/* 0x20440 */
	volatile unsigned int CamCtl;			/* 0x20444 */
	volatile unsigned int TxCtl;			/* 0x20448 */
	volatile unsigned int TxStatus;			/* 0x2044c */
	volatile unsigned int RxCtl;			/* 0x20450 */
	volatile unsigned int RxStatus;			/* 0x20454 */
	volatile unsigned int StationMgmtData;		/* 0x20458 */
	volatile unsigned int StationMgmtCtl;		/* 0x2045c */
	volatile unsigned int CamAddress;		/* 0x20460 */
	volatile unsigned int CamData;			/* 0x20464 */
	volatile unsigned int CamEnable;		/* 0x20468 */
	volatile unsigned char filler2046c[0x20500 - 0x2046c];
	volatile unsigned int DebugPCIMasterAddr;	/* 0x20500 */
	volatile unsigned int DebugLanTxStateMachine;	/* 0x20504 */
	volatile unsigned int DebugLanRxStateMachine;	/* 0x20508 */
	volatile unsigned int DebugLanTxFifoPointers;	/* 0x2050c */
	volatile unsigned int DebugLanRxFifoPointers;	/* 0x20510 */
	volatile unsigned int DebugLanCtlStateMachine;	/* 0x20514 */
};
typedef volatile struct lan_saa9730_regmap t_lan_saa9730_regmap;


/* EVM interrupt control registers. */
#define EVM_LAN_INT                     0x00010000
#define EVM_MASTER_EN                   0x00000001

/* The SAA9730 (EVM) controller register map, as seen via the PCI-bus. */
#define SAA9730_EVM_REGS_ADDR   0x02000
#define SAA9730_EVM_REGS_SIZE   0x00400

struct evm_saa9730_regmap {
	volatile unsigned int InterruptStatus1;		/* 0x2000 */
	volatile unsigned int InterruptEnable1;		/* 0x2004 */
	volatile unsigned int InterruptMonitor1;	/* 0x2008 */
	volatile unsigned int Counter;			/* 0x200c */
	volatile unsigned int CounterThreshold;		/* 0x2010 */
	volatile unsigned int CounterControl;		/* 0x2014 */
	volatile unsigned int GpioControl1;		/* 0x2018 */
	volatile unsigned int InterruptStatus2;		/* 0x201c */
	volatile unsigned int InterruptEnable2;		/* 0x2020 */
	volatile unsigned int InterruptMonitor2;	/* 0x2024 */
	volatile unsigned int GpioControl2;		/* 0x2028 */
	volatile unsigned int InterruptBlock1;		/* 0x202c */
	volatile unsigned int InterruptBlock2;		/* 0x2030 */
};
typedef volatile struct evm_saa9730_regmap t_evm_saa9730_regmap;


struct lan_saa9730_private {
	/*
	 * Rx/Tx packet buffers.
	 * The Rx and Tx packets must be PACKET_SIZE aligned.
	 */
	void		*buffer_start;
	unsigned int	buffer_size;

	/*
	 * DMA address of beginning of this object, returned
	 * by pci_alloc_consistent().
	 */
	dma_addr_t	dma_addr;

	/* Pointer to the associated pci device structure */
	struct pci_dev	*pci_dev;

	/* Pointer for the SAA9730 LAN controller register set. */
	t_lan_saa9730_regmap *lan_saa9730_regs;

	/* Pointer to the SAA9730 EVM register. */
	t_evm_saa9730_regmap *evm_saa9730_regs;

	/* Rcv buffer Index. */
	unsigned char NextRcvPacketIndex;
	/* Next buffer index. */
	unsigned char NextRcvBufferIndex;

	/* Index of next packet to use in that buffer. */
	unsigned char NextTxmPacketIndex;
	/* Next buffer index. */
	unsigned char NextTxmBufferIndex;

	/* Index of first pending packet ready to send. */
	unsigned char PendingTxmPacketIndex;
	/* Pending buffer index. */
	unsigned char PendingTxmBufferIndex;

	unsigned char DmaRcvPackets;
	unsigned char DmaTxmPackets;

	void	      *TxmBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_TXM_Q_SIZE];
	void	      *RcvBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_RCV_Q_SIZE];
	unsigned int TxBufferFree[LAN_SAA9730_BUFFERS];

	unsigned char PhysicalAddress[LAN_SAA9730_CAM_ENTRIES][6];

	spinlock_t lock;
};

#endif /* _SAA9730_H */