smc91x.h

linux 内核源代码

#define PTR_AUTOINC 	0x4000 // Auto increment the pointer on each access
#define PTR_READ	0x2000 // When 1 the operation is a read


// Data Register
/* BANK 2 */
#define DATA_REG	SMC_REG(0x0008, 2)


// Interrupt Status/Acknowledge Register
/* BANK 2 */
#define INT_REG		SMC_REG(0x000C, 2)


// Interrupt Mask Register
/* BANK 2 */
#define IM_REG		SMC_REG(0x000D, 2)
#define IM_MDINT	0x80 // PHY MI Register 18 Interrupt
#define IM_ERCV_INT	0x40 // Early Receive Interrupt
#define IM_EPH_INT	0x20 // Set by Ethernet Protocol Handler section
#define IM_RX_OVRN_INT	0x10 // Set by Receiver Overruns
#define IM_ALLOC_INT	0x08 // Set when allocation request is completed
#define IM_TX_EMPTY_INT	0x04 // Set if the TX FIFO goes empty
#define IM_TX_INT	0x02 // Transmit Interrupt
#define IM_RCV_INT	0x01 // Receive Interrupt


// Multicast Table Registers
/* BANK 3 */
#define MCAST_REG1	SMC_REG(0x0000, 3)
#define MCAST_REG2	SMC_REG(0x0002, 3)
#define MCAST_REG3	SMC_REG(0x0004, 3)
#define MCAST_REG4	SMC_REG(0x0006, 3)


// Management Interface Register (MII)
/* BANK 3 */
#define MII_REG		SMC_REG(0x0008, 3)
#define MII_MSK_CRS100	0x4000 // Disables CRS100 detection during tx half dup
#define MII_MDOE	0x0008 // MII Output Enable
#define MII_MCLK	0x0004 // MII Clock, pin MDCLK
#define MII_MDI		0x0002 // MII Input, pin MDI
#define MII_MDO		0x0001 // MII Output, pin MDO


// Revision Register
/* BANK 3 */
/* ( hi: chip id   low: rev # ) */
#define REV_REG		SMC_REG(0x000A, 3)


// Early RCV Register
/* BANK 3 */
/* this is NOT on SMC9192 */
#define ERCV_REG	SMC_REG(0x000C, 3)
#define ERCV_RCV_DISCRD	0x0080 // When 1 discards a packet being received
#define ERCV_THRESHOLD	0x001F // ERCV Threshold Mask


// External Register
/* BANK 7 */
#define EXT_REG		SMC_REG(0x0000, 7)


#define CHIP_9192	3
#define CHIP_9194	4
#define CHIP_9195	5
#define CHIP_9196	6
#define CHIP_91100	7
#define CHIP_91100FD	8
#define CHIP_91111FD	9

static const char * chip_ids[ 16 ] =  {
	NULL, NULL, NULL,
	/* 3 */ "SMC91C90/91C92",
	/* 4 */ "SMC91C94",
	/* 5 */ "SMC91C95",
	/* 6 */ "SMC91C96",
	/* 7 */ "SMC91C100",
	/* 8 */ "SMC91C100FD",
	/* 9 */ "SMC91C11xFD",
	NULL, NULL, NULL,
	NULL, NULL, NULL};


/*
 . Receive status bits
*/
#define RS_ALGNERR	0x8000
#define RS_BRODCAST	0x4000
#define RS_BADCRC	0x2000
#define RS_ODDFRAME	0x1000
#define RS_TOOLONG	0x0800
#define RS_TOOSHORT	0x0400
#define RS_MULTICAST	0x0001
#define RS_ERRORS	(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)


/*
 * PHY IDs
 *  LAN83C183 == LAN91C111 Internal PHY
 */
#define PHY_LAN83C183	0x0016f840
#define PHY_LAN83C180	0x02821c50

/*
 * PHY Register Addresses (LAN91C111 Internal PHY)
 *
 * Generic PHY registers can be found in <linux/mii.h>
 *
 * These phy registers are specific to our on-board phy.
 */

// PHY Configuration Register 1
#define PHY_CFG1_REG		0x10
#define PHY_CFG1_LNKDIS		0x8000	// 1=Rx Link Detect Function disabled
#define PHY_CFG1_XMTDIS		0x4000	// 1=TP Transmitter Disabled
#define PHY_CFG1_XMTPDN		0x2000	// 1=TP Transmitter Powered Down
#define PHY_CFG1_BYPSCR		0x0400	// 1=Bypass scrambler/descrambler
#define PHY_CFG1_UNSCDS		0x0200	// 1=Unscramble Idle Reception Disable
#define PHY_CFG1_EQLZR		0x0100	// 1=Rx Equalizer Disabled
#define PHY_CFG1_CABLE		0x0080	// 1=STP(150ohm), 0=UTP(100ohm)
#define PHY_CFG1_RLVL0		0x0040	// 1=Rx Squelch level reduced by 4.5db
#define PHY_CFG1_TLVL_SHIFT	2	// Transmit Output Level Adjust
#define PHY_CFG1_TLVL_MASK	0x003C
#define PHY_CFG1_TRF_MASK	0x0003	// Transmitter Rise/Fall time


// PHY Configuration Register 2
#define PHY_CFG2_REG		0x11
#define PHY_CFG2_APOLDIS	0x0020	// 1=Auto Polarity Correction disabled
#define PHY_CFG2_JABDIS		0x0010	// 1=Jabber disabled
#define PHY_CFG2_MREG		0x0008	// 1=Multiple register access (MII mgt)
#define PHY_CFG2_INTMDIO	0x0004	// 1=Interrupt signaled with MDIO pulseo

// PHY Status Output (and Interrupt status) Register
#define PHY_INT_REG		0x12	// Status Output (Interrupt Status)
#define PHY_INT_INT		0x8000	// 1=bits have changed since last read
#define PHY_INT_LNKFAIL		0x4000	// 1=Link Not detected
#define PHY_INT_LOSSSYNC	0x2000	// 1=Descrambler has lost sync
#define PHY_INT_CWRD		0x1000	// 1=Invalid 4B5B code detected on rx
#define PHY_INT_SSD		0x0800	// 1=No Start Of Stream detected on rx
#define PHY_INT_ESD		0x0400	// 1=No End Of Stream detected on rx
#define PHY_INT_RPOL		0x0200	// 1=Reverse Polarity detected
#define PHY_INT_JAB		0x0100	// 1=Jabber detected
#define PHY_INT_SPDDET		0x0080	// 1=100Base-TX mode, 0=10Base-T mode
#define PHY_INT_DPLXDET		0x0040	// 1=Device in Full Duplex

// PHY Interrupt/Status Mask Register
#define PHY_MASK_REG		0x13	// Interrupt Mask
// Uses the same bit definitions as PHY_INT_REG


/*
 * SMC91C96 ethernet config and status registers.
 * These are in the "attribute" space.
 */
#define ECOR			0x8000
#define ECOR_RESET		0x80
#define ECOR_LEVEL_IRQ		0x40
#define ECOR_WR_ATTRIB		0x04
#define ECOR_ENABLE		0x01

#define ECSR			0x8002
#define ECSR_IOIS8		0x20
#define ECSR_PWRDWN		0x04
#define ECSR_INT		0x02

#define ATTRIB_SIZE		((64*1024) << SMC_IO_SHIFT)


/*
 * Macros to abstract register access according to the data bus
 * capabilities.  Please use those and not the in/out primitives.
 * Note: the following macros do *not* select the bank -- this must
 * be done separately as needed in the main code.  The SMC_REG() macro
 * only uses the bank argument for debugging purposes (when enabled).
 *
 * Note: despite inline functions being safer, everything leading to this
 * should preferably be macros to let BUG() display the line number in
 * the core source code since we're interested in the top call site
 * not in any inline function location.
 */

#if SMC_DEBUG > 0
#define SMC_REG(reg, bank)						\
	({								\
		int __b = SMC_CURRENT_BANK();				\
		if (unlikely((__b & ~0xf0) != (0x3300 | bank))) {	\
			printk( "%s: bank reg screwed (0x%04x)\n",	\
				CARDNAME, __b );			\
			BUG();						\
		}							\
		reg<<SMC_IO_SHIFT;					\
	})
#else
#define SMC_REG(reg, bank)	(reg<<SMC_IO_SHIFT)
#endif

/*
 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
 * aligned to a 32 bit boundary.  I tell you that does exist!
 * Fortunately the affected register accesses can be easily worked around
 * since we can write zeroes to the preceeding 16 bits without adverse
 * effects and use a 32-bit access.
 *
 * Enforce it on any 32-bit capable setup for now.
 */
#define SMC_MUST_ALIGN_WRITE	SMC_CAN_USE_32BIT

#define SMC_GET_PN()							\
	( SMC_CAN_USE_8BIT	? (SMC_inb(ioaddr, PN_REG))		\
				: (SMC_inw(ioaddr, PN_REG) & 0xFF) )

#define SMC_SET_PN(x)							\
	do {								\
		if (SMC_MUST_ALIGN_WRITE)				\
			SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2));	\
		else if (SMC_CAN_USE_8BIT)				\
			SMC_outb(x, ioaddr, PN_REG);			\
		else							\
			SMC_outw(x, ioaddr, PN_REG);			\
	} while (0)

#define SMC_GET_AR()							\
	( SMC_CAN_USE_8BIT	? (SMC_inb(ioaddr, AR_REG))		\
	  			: (SMC_inw(ioaddr, PN_REG) >> 8) )

#define SMC_GET_TXFIFO()						\
	( SMC_CAN_USE_8BIT	? (SMC_inb(ioaddr, TXFIFO_REG))		\
				: (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )

#define SMC_GET_RXFIFO()						\
	  ( SMC_CAN_USE_8BIT	? (SMC_inb(ioaddr, RXFIFO_REG))		\
				: (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )

#define SMC_GET_INT()							\
	( SMC_CAN_USE_8BIT	? (SMC_inb(ioaddr, INT_REG))		\
				: (SMC_inw(ioaddr, INT_REG) & 0xFF) )

#define SMC_ACK_INT(x)							\
	do {								\
		if (SMC_CAN_USE_8BIT)					\
			SMC_outb(x, ioaddr, INT_REG);			\
		else {							\
			unsigned long __flags;				\
			int __mask;					\
			local_irq_save(__flags);			\
			__mask = SMC_inw( ioaddr, INT_REG ) & ~0xff;	\
			SMC_outw( __mask | (x), ioaddr, INT_REG );	\
			local_irq_restore(__flags);			\
		}							\
	} while (0)

#define SMC_GET_INT_MASK()						\
	( SMC_CAN_USE_8BIT	? (SMC_inb(ioaddr, IM_REG))		\
				: (SMC_inw( ioaddr, INT_REG ) >> 8) )

#define SMC_SET_INT_MASK(x)						\
	do {								\
		if (SMC_CAN_USE_8BIT)					\
			SMC_outb(x, ioaddr, IM_REG);			\
		else							\
			SMC_outw((x) << 8, ioaddr, INT_REG);		\
	} while (0)

#define SMC_CURRENT_BANK()	SMC_inw(ioaddr, BANK_SELECT)

#define SMC_SELECT_BANK(x)						\
	do {								\
		if (SMC_MUST_ALIGN_WRITE)				\
			SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT);	\
		else							\
			SMC_outw(x, ioaddr, BANK_SELECT);		\
	} while (0)

#define SMC_GET_BASE()		SMC_inw(ioaddr, BASE_REG)

#define SMC_SET_BASE(x)		SMC_outw(x, ioaddr, BASE_REG)

#define SMC_GET_CONFIG()	SMC_inw(ioaddr, CONFIG_REG)

#define SMC_SET_CONFIG(x)	SMC_outw(x, ioaddr, CONFIG_REG)

#define SMC_GET_COUNTER()	SMC_inw(ioaddr, COUNTER_REG)

#define SMC_GET_CTL()		SMC_inw(ioaddr, CTL_REG)

#define SMC_SET_CTL(x)		SMC_outw(x, ioaddr, CTL_REG)

#define SMC_GET_MII()		SMC_inw(ioaddr, MII_REG)

#define SMC_SET_MII(x)		SMC_outw(x, ioaddr, MII_REG)

#define SMC_GET_MIR()		SMC_inw(ioaddr, MIR_REG)

#define SMC_SET_MIR(x)		SMC_outw(x, ioaddr, MIR_REG)

#define SMC_GET_MMU_CMD()	SMC_inw(ioaddr, MMU_CMD_REG)

#define SMC_SET_MMU_CMD(x)	SMC_outw(x, ioaddr, MMU_CMD_REG)

#define SMC_GET_FIFO()		SMC_inw(ioaddr, FIFO_REG)

#define SMC_GET_PTR()		SMC_inw(ioaddr, PTR_REG)

#define SMC_SET_PTR(x)							\
	do {								\
		if (SMC_MUST_ALIGN_WRITE)				\
			SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2));	\
		else							\
			SMC_outw(x, ioaddr, PTR_REG);			\
	} while (0)

#define SMC_GET_EPH_STATUS()	SMC_inw(ioaddr, EPH_STATUS_REG)

#define SMC_GET_RCR()		SMC_inw(ioaddr, RCR_REG)

#define SMC_SET_RCR(x)		SMC_outw(x, ioaddr, RCR_REG)

#define SMC_GET_REV()		SMC_inw(ioaddr, REV_REG)

#define SMC_GET_RPC()		SMC_inw(ioaddr, RPC_REG)

#define SMC_SET_RPC(x)							\
	do {								\
		if (SMC_MUST_ALIGN_WRITE)				\
			SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0));	\
		else							\
			SMC_outw(x, ioaddr, RPC_REG);			\
	} while (0)

#define SMC_GET_TCR()		SMC_inw(ioaddr, TCR_REG)

#define SMC_SET_TCR(x)		SMC_outw(x, ioaddr, TCR_REG)

#ifndef SMC_GET_MAC_ADDR
#define SMC_GET_MAC_ADDR(addr)						\
	do {								\
		unsigned int __v;					\
		__v = SMC_inw( ioaddr, ADDR0_REG );			\
		addr[0] = __v; addr[1] = __v >> 8;			\
		__v = SMC_inw( ioaddr, ADDR1_REG );			\
		addr[2] = __v; addr[3] = __v >> 8;			\
		__v = SMC_inw( ioaddr, ADDR2_REG );			\
		addr[4] = __v; addr[5] = __v >> 8;			\
	} while (0)
#endif

#define SMC_SET_MAC_ADDR(addr)						\
	do {								\
		SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG );	\
		SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG );	\
		SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG );	\
	} while (0)

#define SMC_SET_MCAST(x)						\
	do {								\
		const unsigned char *mt = (x);				\
		SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 );	\
		SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 );	\
		SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 );	\
		SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 );	\
	} while (0)

#define SMC_PUT_PKT_HDR(status, length)					\
	do {								\
		if (SMC_CAN_USE_32BIT)					\
			SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
		else {							\
			SMC_outw(status, ioaddr, DATA_REG);		\
			SMC_outw(length, ioaddr, DATA_REG);		\
		}							\
	} while (0)

#define SMC_GET_PKT_HDR(status, length)					\
	do {								\
		if (SMC_CAN_USE_32BIT) {				\
			unsigned int __val = SMC_inl(ioaddr, DATA_REG);	\
			(status) = __val & 0xffff;			\
			(length) = __val >> 16;				\
		} else {						\
			(status) = SMC_inw(ioaddr, DATA_REG);		\
			(length) = SMC_inw(ioaddr, DATA_REG);		\
		}							\
	} while (0)

#define SMC_PUSH_DATA(p, l)						\
	do {								\
		if (SMC_CAN_USE_32BIT) {				\
			void *__ptr = (p);				\
			int __len = (l);				\
			void __iomem *__ioaddr = ioaddr;		\
			if (__len >= 2 && (unsigned long)__ptr & 2) {	\
				__len -= 2;				\
				SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
				__ptr += 2;				\
			}						\
			if (SMC_CAN_USE_DATACS && lp->datacs)		\
				__ioaddr = lp->datacs;			\
			SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2);	\
			if (__len & 2) {				\
				__ptr += (__len & ~3);			\
				SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
			}						\
		} else if (SMC_CAN_USE_16BIT)				\
			SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1);	\
		else if (SMC_CAN_USE_8BIT)				\
			SMC_outsb(ioaddr, DATA_REG, p, l);		\
	} while (0)

#define SMC_PULL_DATA(p, l)						\
	do {								\
		if (SMC_CAN_USE_32BIT) {				\
			void *__ptr = (p);				\
			int __len = (l);				\
			void __iomem *__ioaddr = ioaddr;		\
			if ((unsigned long)__ptr & 2) {			\
				/*					\
				 * We want 32bit alignment here.	\
				 * Since some buses perform a full	\
				 * 32bit fetch even for 16bit data	\
				 * we can't use SMC_inw() here.		\
				 * Back both source (on-chip) and	\
				 * destination pointers of 2 bytes.	\
				 * This is possible since the call to	\
				 * SMC_GET_PKT_HDR() already advanced	\
				 * the source pointer of 4 bytes, and	\
				 * the skb_reserve(skb, 2) advanced	\
				 * the destination pointer of 2 bytes.	\
				 */					\
				__ptr -= 2;				\
				__len += 2;				\
				SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
			}						\
			if (SMC_CAN_USE_DATACS && lp->datacs)		\
				__ioaddr = lp->datacs;			\
			__len += 2;					\
			SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2);	\
		} else if (SMC_CAN_USE_16BIT)				\
			SMC_insw(ioaddr, DATA_REG, p, (l) >> 1);	\
		else if (SMC_CAN_USE_8BIT)				\
			SMC_insb(ioaddr, DATA_REG, p, l);		\
	} while (0)

#endif  /* _SMC91X_H_ */