smc91x.h

linux 内核源代码

/*------------------------------------------------------------------------
 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
 .
 . Copyright (C) 1996 by Erik Stahlman
 . Copyright (C) 2001 Standard Microsystems Corporation
 .	Developed by Simple Network Magic Corporation
 . Copyright (C) 2003 Monta Vista Software, Inc.
 .	Unified SMC91x driver by Nicolas Pitre
 .
 . This program is free software; you can redistribute it and/or modify
 . it under the terms of the GNU General Public License as published by
 . the Free Software Foundation; either version 2 of the License, or
 . (at your option) any later version.
 .
 . This program is distributed in the hope that it will be useful,
 . but WITHOUT ANY WARRANTY; without even the implied warranty of
 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 . GNU General Public License for more details.
 .
 . You should have received a copy of the GNU General Public License
 . along with this program; if not, write to the Free Software
 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 .
 . Information contained in this file was obtained from the LAN91C111
 . manual from SMC.  To get a copy, if you really want one, you can find
 . information under www.smsc.com.
 .
 . Authors
 .	Erik Stahlman		<[e-mail]>
 .	Daris A Nevil		<[e-mail]>
 .	Nicolas Pitre 		<[e-mail]>
 .
 ---------------------------------------------------------------------------*/
#ifndef _SMC91X_H_
#define _SMC91X_H_


/*
 * Define your architecture specific bus configuration parameters here.
 */

#if	defined(CONFIG_ARCH_LUBBOCK)

/* We can only do 16-bit reads and writes in the static memory space. */
#define SMC_CAN_USE_8BIT	0
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	0
#define SMC_NOWAIT		1

/* The first two address lines aren't connected... */
#define SMC_IO_SHIFT		2

#define SMC_inw(a, r)		readw((a) + (r))
#define SMC_outw(v, a, r)	writew(v, (a) + (r))
#define SMC_insw(a, r, p, l)	readsw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l)	writesw((a) + (r), p, l)

#elif defined(CONFIG_BLACKFIN)

#define SMC_IRQ_FLAGS		IRQF_TRIGGER_HIGH
#define RPC_LSA_DEFAULT		RPC_LED_100_10
#define RPC_LSB_DEFAULT		RPC_LED_TX_RX

# if defined (CONFIG_BFIN561_EZKIT)
#define SMC_CAN_USE_8BIT	0
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	1
#define SMC_IO_SHIFT		0
#define SMC_NOWAIT      	1
#define SMC_USE_BFIN_DMA	0


#define SMC_inw(a, r)       	readw((a) + (r))
#define SMC_outw(v, a, r)   	writew(v, (a) + (r))
#define SMC_inl(a, r)       	readl((a) + (r))
#define SMC_outl(v, a, r)   	writel(v, (a) + (r))
#define SMC_outsl(a, r, p, l)	outsl((unsigned long *)((a) + (r)), p, l)
#define SMC_insl(a, r, p, l) 	insl ((unsigned long *)((a) + (r)), p, l)
# else
#define SMC_CAN_USE_8BIT	0
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	0
#define SMC_IO_SHIFT		0
#define SMC_NOWAIT      	1
#define SMC_USE_BFIN_DMA	0


#define SMC_inw(a, r)       	readw((a) + (r))
#define SMC_outw(v, a, r)   	writew(v, (a) + (r))
#define SMC_outsw(a, r, p, l)	outsw((unsigned long *)((a) + (r)), p, l)
#define SMC_insw(a, r, p, l) 	insw ((unsigned long *)((a) + (r)), p, l)
# endif
/* check if the mac in reg is valid */
#define SMC_GET_MAC_ADDR(addr)					\
	do {							\
		unsigned int __v;				\
		__v = SMC_inw(ioaddr, ADDR0_REG);		\
		addr[0] = __v; addr[1] = __v >> 8;		\
		__v = SMC_inw(ioaddr, ADDR1_REG);		\
		addr[2] = __v; addr[3] = __v >> 8;		\
		__v = SMC_inw(ioaddr, ADDR2_REG);		\
		addr[4] = __v; addr[5] = __v >> 8;		\
		if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) {		\
			random_ether_addr(addr);		\
		}						\
	} while (0)
#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)

/* We can only do 16-bit reads and writes in the static memory space. */
#define SMC_CAN_USE_8BIT	0
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	0
#define SMC_NOWAIT		1

#define SMC_IO_SHIFT		0

#define SMC_inw(a, r)		in_be16((volatile u16 *)((a) + (r)))
#define SMC_outw(v, a, r)	out_be16((volatile u16 *)((a) + (r)), v)
#define SMC_insw(a, r, p, l) 						\
	do {								\
		unsigned long __port = (a) + (r);			\
		u16 *__p = (u16 *)(p);					\
		int __l = (l);						\
		insw(__port, __p, __l);					\
		while (__l > 0) {					\
			*__p = swab16(*__p);				\
			__p++;						\
			__l--;						\
		}							\
	} while (0)
#define SMC_outsw(a, r, p, l) 						\
	do {								\
		unsigned long __port = (a) + (r);			\
		u16 *__p = (u16 *)(p);					\
		int __l = (l);						\
		while (__l > 0) {					\
			/* Believe it or not, the swab isn't needed. */	\
			outw( /* swab16 */ (*__p++), __port);		\
			__l--;						\
		}							\
	} while (0)
#define SMC_IRQ_FLAGS		(0)

#elif defined(CONFIG_SA1100_PLEB)
/* We can only do 16-bit reads and writes in the static memory space. */
#define SMC_CAN_USE_8BIT	1
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	0
#define SMC_IO_SHIFT		0
#define SMC_NOWAIT		1

#define SMC_inb(a, r)		readb((a) + (r))
#define SMC_insb(a, r, p, l)	readsb((a) + (r), p, (l))
#define SMC_inw(a, r)		readw((a) + (r))
#define SMC_insw(a, r, p, l)	readsw((a) + (r), p, l)
#define SMC_outb(v, a, r)	writeb(v, (a) + (r))
#define SMC_outsb(a, r, p, l)	writesb((a) + (r), p, (l))
#define SMC_outw(v, a, r)	writew(v, (a) + (r))
#define SMC_outsw(a, r, p, l)	writesw((a) + (r), p, l)

#define SMC_IRQ_FLAGS		(0)

#elif defined(CONFIG_SA1100_ASSABET)

#include <asm/arch/neponset.h>

/* We can only do 8-bit reads and writes in the static memory space. */
#define SMC_CAN_USE_8BIT	1
#define SMC_CAN_USE_16BIT	0
#define SMC_CAN_USE_32BIT	0
#define SMC_NOWAIT		1

/* The first two address lines aren't connected... */
#define SMC_IO_SHIFT		2

#define SMC_inb(a, r)		readb((a) + (r))
#define SMC_outb(v, a, r)	writeb(v, (a) + (r))
#define SMC_insb(a, r, p, l)	readsb((a) + (r), p, (l))
#define SMC_outsb(a, r, p, l)	writesb((a) + (r), p, (l))

#elif	defined(CONFIG_MACH_LOGICPD_PXA270)

#define SMC_CAN_USE_8BIT	0
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	0
#define SMC_IO_SHIFT		0
#define SMC_NOWAIT		1

#define SMC_inw(a, r)		readw((a) + (r))
#define SMC_outw(v, a, r)	writew(v, (a) + (r))
#define SMC_insw(a, r, p, l)	readsw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l)	writesw((a) + (r), p, l)

#elif	defined(CONFIG_ARCH_INNOKOM) || \
	defined(CONFIG_MACH_MAINSTONE) || \
	defined(CONFIG_ARCH_PXA_IDP) || \
	defined(CONFIG_ARCH_RAMSES)

#define SMC_CAN_USE_8BIT	1
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	1
#define SMC_IO_SHIFT		0
#define SMC_NOWAIT		1
#define SMC_USE_PXA_DMA		1

#define SMC_inb(a, r)		readb((a) + (r))
#define SMC_inw(a, r)		readw((a) + (r))
#define SMC_inl(a, r)		readl((a) + (r))
#define SMC_outb(v, a, r)	writeb(v, (a) + (r))
#define SMC_outl(v, a, r)	writel(v, (a) + (r))
#define SMC_insl(a, r, p, l)	readsl((a) + (r), p, l)
#define SMC_outsl(a, r, p, l)	writesl((a) + (r), p, l)

/* We actually can't write halfwords properly if not word aligned */
static inline void
SMC_outw(u16 val, void __iomem *ioaddr, int reg)
{
	if (reg & 2) {
		unsigned int v = val << 16;
		v |= readl(ioaddr + (reg & ~2)) & 0xffff;
		writel(v, ioaddr + (reg & ~2));
	} else {
		writew(val, ioaddr + reg);
	}
}

#elif defined(CONFIG_MACH_ZYLONITE)

#define SMC_CAN_USE_8BIT        1
#define SMC_CAN_USE_16BIT       1
#define SMC_CAN_USE_32BIT       0
#define SMC_IO_SHIFT            0
#define SMC_NOWAIT              1
#define SMC_USE_PXA_DMA		1
#define SMC_inb(a, r)           readb((a) + (r))
#define SMC_inw(a, r)           readw((a) + (r))
#define SMC_insw(a, r, p, l)    insw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l)   outsw((a) + (r), p, l)
#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
#define SMC_outw(v, a, r)       writew(v, (a) + (r))

#elif	defined(CONFIG_ARCH_OMAP)

/* We can only do 16-bit reads and writes in the static memory space. */
#define SMC_CAN_USE_8BIT	0
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	0
#define SMC_IO_SHIFT		0
#define SMC_NOWAIT		1

#define SMC_inw(a, r)		readw((a) + (r))
#define SMC_outw(v, a, r)	writew(v, (a) + (r))
#define SMC_insw(a, r, p, l)	readsw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l)	writesw((a) + (r), p, l)

#include <asm/mach-types.h>
#include <asm/arch/cpu.h>

#define	SMC_IRQ_FLAGS (( \
		   machine_is_omap_h2() \
		|| machine_is_omap_h3() \
		|| machine_is_omap_h4() \
		|| (machine_is_omap_innovator() && !cpu_is_omap1510()) \
	) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)


#elif	defined(CONFIG_SH_SH4202_MICRODEV)

#define SMC_CAN_USE_8BIT	0
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	0

#define SMC_inb(a, r)		inb((a) + (r) - 0xa0000000)
#define SMC_inw(a, r)		inw((a) + (r) - 0xa0000000)
#define SMC_inl(a, r)		inl((a) + (r) - 0xa0000000)
#define SMC_outb(v, a, r)	outb(v, (a) + (r) - 0xa0000000)
#define SMC_outw(v, a, r)	outw(v, (a) + (r) - 0xa0000000)
#define SMC_outl(v, a, r)	outl(v, (a) + (r) - 0xa0000000)
#define SMC_insl(a, r, p, l)	insl((a) + (r) - 0xa0000000, p, l)
#define SMC_outsl(a, r, p, l)	outsl((a) + (r) - 0xa0000000, p, l)
#define SMC_insw(a, r, p, l)	insw((a) + (r) - 0xa0000000, p, l)
#define SMC_outsw(a, r, p, l)	outsw((a) + (r) - 0xa0000000, p, l)

#define SMC_IRQ_FLAGS		(0)

#elif	defined(CONFIG_ISA)

#define SMC_CAN_USE_8BIT	1
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	0

#define SMC_inb(a, r)		inb((a) + (r))
#define SMC_inw(a, r)		inw((a) + (r))
#define SMC_outb(v, a, r)	outb(v, (a) + (r))
#define SMC_outw(v, a, r)	outw(v, (a) + (r))
#define SMC_insw(a, r, p, l)	insw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l)	outsw((a) + (r), p, l)

#elif   defined(CONFIG_SUPERH)

#ifdef CONFIG_SOLUTION_ENGINE
#define SMC_IRQ_FLAGS		(0)
#define SMC_CAN_USE_8BIT       0
#define SMC_CAN_USE_16BIT      1
#define SMC_CAN_USE_32BIT      0
#define SMC_IO_SHIFT           0
#define SMC_NOWAIT             1

#define SMC_inw(a, r)          inw((a) + (r))
#define SMC_outw(v, a, r)      outw(v, (a) + (r))
#define SMC_insw(a, r, p, l)   insw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l)  outsw((a) + (r), p, l)

#else /* BOARDS */

#define SMC_CAN_USE_8BIT       1
#define SMC_CAN_USE_16BIT      1
#define SMC_CAN_USE_32BIT      0

#define SMC_inb(a, r)          inb((a) + (r))
#define SMC_inw(a, r)          inw((a) + (r))
#define SMC_outb(v, a, r)      outb(v, (a) + (r))
#define SMC_outw(v, a, r)      outw(v, (a) + (r))
#define SMC_insw(a, r, p, l)   insw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l)  outsw((a) + (r), p, l)

#endif  /* BOARDS */

#elif   defined(CONFIG_M32R)

#define SMC_CAN_USE_8BIT	0
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	0

#define SMC_inb(a, r)		inb(((u32)a) + (r))
#define SMC_inw(a, r)		inw(((u32)a) + (r))
#define SMC_outb(v, a, r)	outb(v, ((u32)a) + (r))
#define SMC_outw(v, a, r)	outw(v, ((u32)a) + (r))
#define SMC_insw(a, r, p, l)	insw(((u32)a) + (r), p, l)
#define SMC_outsw(a, r, p, l)	outsw(((u32)a) + (r), p, l)

#define SMC_IRQ_FLAGS		(0)

#define RPC_LSA_DEFAULT		RPC_LED_TX_RX
#define RPC_LSB_DEFAULT		RPC_LED_100_10

#elif   defined(CONFIG_MACH_LPD79520) \
     || defined(CONFIG_MACH_LPD7A400) \
     || defined(CONFIG_MACH_LPD7A404)

/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
 * way that the CPU handles chip selects and the way that the SMC chip
 * expects the chip select to operate.  Refer to
 * Documentation/arm/Sharp-LH/IOBarrier for details.  The read from
 * IOBARRIER is a byte, in order that we read the least-common
 * denominator.  It would be wasteful to read 32 bits from an 8-bit
 * accessible region.
 *
 * There is no explicit protection against interrupts intervening
 * between the writew and the IOBARRIER.  In SMC ISR there is a
 * preamble that performs an IOBARRIER in the extremely unlikely event
 * that the driver interrupts itself between a writew to the chip an
 * the IOBARRIER that follows *and* the cache is large enough that the
 * first off-chip access while handing the interrupt is to the SMC
 * chip.  Other devices in the same address space as the SMC chip must
 * be aware of the potential for trouble and perform a similar
 * IOBARRIER on entry to their ISR.
 */

#include <asm/arch/constants.h>	/* IOBARRIER_VIRT */

#define SMC_CAN_USE_8BIT	0
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	0
#define SMC_NOWAIT		0
#define LPD7X_IOBARRIER		readb (IOBARRIER_VIRT)

#define SMC_inw(a,r)\
   ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
#define SMC_outw(v,a,r)	  ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })

#define SMC_insw		LPD7_SMC_insw
static inline void LPD7_SMC_insw (unsigned char* a, int r,
				  unsigned char* p, int l)
{
	unsigned short* ps = (unsigned short*) p;
	while (l-- > 0) {
		*ps++ = readw (a + r);
		LPD7X_IOBARRIER;
	}
}

#define SMC_outsw		LPD7_SMC_outsw
static inline void LPD7_SMC_outsw (unsigned char* a, int r,
				   unsigned char* p, int l)
{
	unsigned short* ps = (unsigned short*) p;
	while (l-- > 0) {
		writew (*ps++, a + r);
		LPD7X_IOBARRIER;
	}
}

#define SMC_INTERRUPT_PREAMBLE	LPD7X_IOBARRIER

#define RPC_LSA_DEFAULT		RPC_LED_TX_RX
#define RPC_LSB_DEFAULT		RPC_LED_100_10

#elif defined(CONFIG_SOC_AU1X00)

#include <au1xxx.h>

/* We can only do 16-bit reads and writes in the static memory space. */
#define SMC_CAN_USE_8BIT	0
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	0
#define SMC_IO_SHIFT		0
#define SMC_NOWAIT		1

#define SMC_inw(a, r)		au_readw((unsigned long)((a) + (r)))
#define SMC_insw(a, r, p, l)	\
	do {	\
		unsigned long _a = (unsigned long)((a) + (r)); \
		int _l = (l); \
		u16 *_p = (u16 *)(p); \
		while (_l-- > 0) \
			*_p++ = au_readw(_a); \
	} while(0)
#define SMC_outw(v, a, r)	au_writew(v, (unsigned long)((a) + (r)))
#define SMC_outsw(a, r, p, l)	\
	do {	\
		unsigned long _a = (unsigned long)((a) + (r)); \
		int _l = (l); \
		const u16 *_p = (const u16 *)(p); \
		while (_l-- > 0) \
			au_writew(*_p++ , _a); \
	} while(0)

#define SMC_IRQ_FLAGS		(0)

#elif	defined(CONFIG_ARCH_VERSATILE)

#define SMC_CAN_USE_8BIT	1
#define SMC_CAN_USE_16BIT	1
#define SMC_CAN_USE_32BIT	1
#define SMC_NOWAIT		1

#define SMC_inb(a, r)		readb((a) + (r))