ipath_init_chip.c
来自「linux 内核源代码」· C语言 代码 · 共 1,018 行 · 第 1/3 页
C
1,018 行
* Do the actual initialization sequence on the chip. This is done * both from the init routine called from the PCI infrastructure, and * when we reset the chip, or detect that it was reset internally, * or it's administratively re-enabled. * * Memory allocation here and in called routines is only done in * the first case (reinit == 0). We have to be careful, because even * without memory allocation, we need to re-write all the chip registers * TIDs, etc. after the reset or enable has completed. */int ipath_init_chip(struct ipath_devdata *dd, int reinit){ int ret = 0, i; u32 val32, kpiobufs; u32 piobufs, uports; u64 val; struct ipath_portdata *pd = NULL; /* keep gcc4 happy */ gfp_t gfp_flags = GFP_USER | __GFP_COMP; ret = init_housekeeping(dd, &pd, reinit); if (ret) goto done; /* * we ignore most issues after reporting them, but have to specially * handle hardware-disabled chips. */ if (ret == 2) { /* unique error, known to ipath_init_one */ ret = -EPERM; goto done; } /* * We could bump this to allow for full rcvegrcnt + rcvtidcnt, * but then it no longer nicely fits power of two, and since * we now use routines that backend onto __get_free_pages, the * rest would be wasted. */ dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt; ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt, dd->ipath_rcvhdrcnt); /* * Set up the shadow copies of the piobufavail registers, * which we compare against the chip registers for now, and * the in memory DMA'ed copies of the registers. This has to * be done early, before we calculate lastport, etc. */ piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k; /* * calc number of pioavail registers, and save it; we have 2 * bits per buffer. */ dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) / (sizeof(u64) * BITS_PER_BYTE / 2); uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0; if (ipath_kpiobufs == 0) { /* not set by user (this is default) */ if (piobufs > 144) kpiobufs = 32; else kpiobufs = 16; } else kpiobufs = ipath_kpiobufs; if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) { i = (int) piobufs - (int) (uports * IPATH_MIN_USER_PORT_BUFCNT); if (i < 0) i = 0; dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of " "%d for kernel leaves too few for %d user ports " "(%d each); using %u\n", kpiobufs, piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i); /* * shouldn't change ipath_kpiobufs, because could be * different for different devices... */ kpiobufs = i; } dd->ipath_lastport_piobuf = piobufs - kpiobufs; dd->ipath_pbufsport = uports ? dd->ipath_lastport_piobuf / uports : 0; val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports); if (val32 > 0) { ipath_dbg("allocating %u pbufs/port leaves %u unused, " "add to kernel\n", dd->ipath_pbufsport, val32); dd->ipath_lastport_piobuf -= val32; ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n", dd->ipath_pbufsport, val32); } dd->ipath_lastpioindex = dd->ipath_lastport_piobuf; ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u " "each for %u user ports\n", kpiobufs, piobufs, dd->ipath_pbufsport, uports); dd->ipath_f_early_init(dd); /* * cancel any possible active sends from early driver load. * Follows early_init because some chips have to initialize * PIO buffers in early_init to avoid false parity errors. */ ipath_cancel_sends(dd, 0); /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be * done after early_init */ dd->ipath_hdrqlast = dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1); ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize, dd->ipath_rcvhdrentsize); ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize, dd->ipath_rcvhdrsize); if (!reinit) { ret = init_pioavailregs(dd); init_shadow_tids(dd); if (ret) goto done; } (void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr, dd->ipath_pioavailregs_phys); /* * this is to detect s/w errors, which the h/w works around by * ignoring the low 6 bits of address, if it wasn't aligned. */ val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr); if (val != dd->ipath_pioavailregs_phys) { ipath_dev_err(dd, "Catastrophic software error, " "SendPIOAvailAddr written as %lx, " "read back as %llx\n", (unsigned long) dd->ipath_pioavailregs_phys, (unsigned long long) val); ret = -EINVAL; goto done; } ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP); /* * make sure we are not in freeze, and PIO send enabled, so * writes to pbc happen */ ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL); ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED); ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL); ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, INFINIPATH_S_PIOENABLE); /* * before error clears, since we expect serdes pll errors during * this, the first time after reset */ if (bringup_link(dd)) { dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n"); ret = -ENETDOWN; goto done; } /* * clear any "expected" hwerrs from reset and/or initialization * clear any that aren't enabled (at least this once), and then * set the enable mask */ dd->ipath_f_init_hwerrors(dd); ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED); ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, dd->ipath_hwerrmask); /* clear all */ ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL); /* enable errors that are masked, at least this first time. */ ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, ~dd->ipath_maskederrs); dd->ipath_errormask = ipath_read_kreg64(dd, dd->ipath_kregs->kr_errormask); /* clear any interrupts up to this point (ints still not enabled) */ ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL); /* * Set up the port 0 (kernel) rcvhdr q and egr TIDs. If doing * re-init, the simplest way to handle this is to free * existing, and re-allocate. * Need to re-create rest of port 0 portdata as well. */ if (reinit) { /* Alloc and init new ipath_portdata for port0, * Then free old pd. Could lead to fragmentation, but also * makes later support for hot-swap easier. */ struct ipath_portdata *npd; npd = create_portdata0(dd); if (npd) { ipath_free_pddata(dd, pd); dd->ipath_pd[0] = pd = npd; } else { ipath_dev_err(dd, "Unable to allocate portdata for" " port 0, failing\n"); ret = -ENOMEM; goto done; } } dd->ipath_f_tidtemplate(dd); ret = ipath_create_rcvhdrq(dd, pd); if (!ret) { dd->ipath_hdrqtailptr = (volatile __le64 *)pd->port_rcvhdrtail_kvaddr; ret = create_port0_egr(dd); } if (ret) ipath_dev_err(dd, "failed to allocate port 0 (kernel) " "rcvhdrq and/or egr bufs\n"); else enable_chip(dd, pd, reinit); if (!ret && !reinit) { /* used when we close a port, for DMA already in flight at close */ dd->ipath_dummy_hdrq = dma_alloc_coherent( &dd->pcidev->dev, pd->port_rcvhdrq_size, &dd->ipath_dummy_hdrq_phys, gfp_flags); if (!dd->ipath_dummy_hdrq ) { dev_info(&dd->pcidev->dev, "Couldn't allocate 0x%lx bytes for dummy hdrq\n", pd->port_rcvhdrq_size); /* fallback to just 0'ing */ dd->ipath_dummy_hdrq_phys = 0UL; } } /* * cause retrigger of pending interrupts ignored during init, * even if we had errors */ ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL); if(!dd->ipath_stats_timer_active) { /* * first init, or after an admin disable/enable * set up stats retrieval timer, even if we had errors * in last portion of setup */ init_timer(&dd->ipath_stats_timer); dd->ipath_stats_timer.function = ipath_get_faststats; dd->ipath_stats_timer.data = (unsigned long) dd; /* every 5 seconds; */ dd->ipath_stats_timer.expires = jiffies + 5 * HZ; /* takes ~16 seconds to overflow at full IB 4x bandwdith */ add_timer(&dd->ipath_stats_timer); dd->ipath_stats_timer_active = 1; }done: if (!ret) { *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT; if (!dd->ipath_f_intrsetup(dd)) { /* now we can enable all interrupts from the chip */ ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, -1LL); /* force re-interrupt of any pending interrupts. */ ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL); /* chip is usable; mark it as initialized */ *dd->ipath_statusp |= IPATH_STATUS_INITTED; } else ipath_dev_err(dd, "No interrupts enabled, couldn't " "setup interrupt address\n"); if (dd->ipath_cfgports > ipath_stats.sps_nports) /* * sps_nports is a global, so, we set it to * the highest number of ports of any of the * chips we find; we never decrement it, at * least for now. Since this might have changed * over disable/enable or prior to reset, always * do the check and potentially adjust. */ ipath_stats.sps_nports = dd->ipath_cfgports; } else ipath_dbg("Failed (%d) to initialize chip\n", ret); /* if ret is non-zero, we probably should do some cleanup here... */ return ret;}static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp){ struct ipath_devdata *dd; unsigned long flags; unsigned short val; int ret; ret = ipath_parse_ushort(str, &val); spin_lock_irqsave(&ipath_devs_lock, flags); if (ret < 0) goto bail; if (val == 0) { ret = -EINVAL; goto bail; } list_for_each_entry(dd, &ipath_dev_list, ipath_list) { if (dd->ipath_kregbase) continue; if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - (dd->ipath_cfgports * IPATH_MIN_USER_PORT_BUFCNT))) { ipath_dev_err( dd, "Allocating %d PIO bufs for kernel leaves " "too few for %d user ports (%d each)\n", val, dd->ipath_cfgports - 1, IPATH_MIN_USER_PORT_BUFCNT); ret = -EINVAL; goto bail; } dd->ipath_lastport_piobuf = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val; } ipath_kpiobufs = val; ret = 0;bail: spin_unlock_irqrestore(&ipath_devs_lock, flags); return ret;}
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