sh-sci.h

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  }

#ifdef CONFIG_CPU_SH3
#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
		                sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
		                 h8_sci_offset, h8_sci_size) \
  CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
	  CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
      defined(CONFIG_CPU_SUBTYPE_SH7720)
#define SCIF_FNS(name, scif_offset, scif_size) \
  CPU_SCIF_FNS(name, scif_offset, scif_size)
#else
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
		 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
                 h8_sci_offset, h8_sci_size) \
  CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
  CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
#endif
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
		 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
                 h8_sci_offset, h8_sci_size) \
  CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
#else
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
		 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
		 h8_sci_offset, h8_sci_size) \
  CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
  CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#endif

#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
    defined(CONFIG_CPU_SUBTYPE_SH7720)

SCIF_FNS(SCSMR,  0x00, 16)
SCIF_FNS(SCBRR,  0x04,  8)
SCIF_FNS(SCSCR,  0x08, 16)
SCIF_FNS(SCTDSR, 0x0c,  8)
SCIF_FNS(SCFER,  0x10, 16)
SCIF_FNS(SCxSR,  0x14, 16)
SCIF_FNS(SCFCR,  0x18, 16)
SCIF_FNS(SCFDR,  0x1c, 16)
SCIF_FNS(SCxTDR, 0x20,  8)
SCIF_FNS(SCxRDR, 0x24,  8)
SCIF_FNS(SCLSR,  0x24, 16)
#else
/*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
/*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
    defined(CONFIG_CPU_SUBTYPE_SH7780) || \
    defined(CONFIG_CPU_SUBTYPE_SH7785)
SCIF_FNS(SCFDR,			     0x0e, 16, 0x1C, 16)
SCIF_FNS(SCTFDR,		     0x0e, 16, 0x1C, 16)
SCIF_FNS(SCRFDR,		     0x0e, 16, 0x20, 16)
SCIF_FNS(SCSPTR,			0,  0, 0x24, 16)
SCIF_FNS(SCLSR,				0,  0, 0x28, 16)
#else
SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
#endif
#endif
#define sci_in(port, reg) sci_##reg##_in(port)
#define sci_out(port, reg, value) sci_##reg##_out(port, value)

/* H8/300 series SCI pins assignment */
#if defined(__H8300H__) || defined(__H8300S__)
static const struct __attribute__((packed)) {
	int port;             /* GPIO port no */
	unsigned short rx,tx; /* GPIO bit no */
} h8300_sci_pins[] = {
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
	{    /* SCI0 */
		.port = H8300_GPIO_P9,
		.rx   = H8300_GPIO_B2,
		.tx   = H8300_GPIO_B0,
	},
	{    /* SCI1 */
		.port = H8300_GPIO_P9,
		.rx   = H8300_GPIO_B3,
		.tx   = H8300_GPIO_B1,
	},
	{    /* SCI2 */
		.port = H8300_GPIO_PB,
		.rx   = H8300_GPIO_B7,
		.tx   = H8300_GPIO_B6,
	}
#elif defined(CONFIG_H8S2678)
	{    /* SCI0 */
		.port = H8300_GPIO_P3,
		.rx   = H8300_GPIO_B2,
		.tx   = H8300_GPIO_B0,
	},
	{    /* SCI1 */
		.port = H8300_GPIO_P3,
		.rx   = H8300_GPIO_B3,
		.tx   = H8300_GPIO_B1,
	},
	{    /* SCI2 */
		.port = H8300_GPIO_P5,
		.rx   = H8300_GPIO_B1,
		.tx   = H8300_GPIO_B0,
	}
#endif
};
#endif

#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7708) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == 0xfffffe80)
		return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
	if (port->mapbase == 0xa4000150)
		return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xa4000140)
		return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == SCIF0)
		return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
	if (port->mapbase == SCIF2)
		return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
static inline int sci_rxd_in(struct uart_port *port)
{
	  return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
}
static inline void set_sh771x_scif_pfc(struct uart_port *port)
{
	if (port->mapbase == 0xA4400000){
		ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
		ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
		return;
	}
	if (port->mapbase == 0xA4410000){
		ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
		return;
	}
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == 0xa4430000)
		return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
	else if (port->mapbase == 0xa4438000)
		return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
      defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
      defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
      defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
      defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
      defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
      defined(CONFIG_CPU_SUBTYPE_SH4_202)
static inline int sci_rxd_in(struct uart_port *port)
{
#ifndef SCIF_ONLY
	if (port->mapbase == 0xffe00000)
		return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
#endif
#ifndef SCI_ONLY
	if (port->mapbase == 0xffe80000)
		return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
#endif
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == 0xfe600000)
		return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xfe610000)
		return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xfe620000)
		return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == 0xffe00000)
		return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffe10000)
		return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffe20000)
		return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffe30000)
		return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == 0xffe00000)
		return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
static inline int sci_rxd_in(struct uart_port *port)
{
         return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
}
#elif defined(__H8300H__) || defined(__H8300S__)
static inline int sci_rxd_in(struct uart_port *port)
{
	int ch = (port->mapbase - SMR0) >> 3;
	return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == 0xff923000)
		return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xff924000)
		return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xff925000)
		return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == 0xffe00000)
		return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffe10000)
		return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == 0xffea0000)
		return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffeb0000)
		return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffec0000)
		return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffed0000)
		return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffee0000)
		return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffef0000)
		return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == 0xfffe8000)
		return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xfffe8800)
		return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xfffe9000)
		return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xfffe9800)
		return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == 0xf8400000)
		return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xf8410000)
		return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xf8420000)
		return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
	return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
static inline int sci_rxd_in(struct uart_port *port)
{
	if (port->mapbase == 0xffc30000)
		return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffc40000)
		return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffc50000)
		return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
	if (port->mapbase == 0xffc60000)
		return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
	return 1;
}
#endif

/*
 * Values for the BitRate Register (SCBRR)
 *
 * The values are actually divisors for a frequency which can
 * be internal to the SH3 (14.7456MHz) or derived from an external
 * clock source.  This driver assumes the internal clock is used;
 * to support using an external clock source, config options or
 * possibly command-line options would need to be added.
 *
 * Also, to support speeds below 2400 (why?) the lower 2 bits of
 * the SCSMR register would also need to be set to non-zero values.
 *
 * -- Greg Banks 27Feb2000
 *
 * Answer: The SCBRR register is only eight bits, and the value in
 * it gets larger with lower baud rates. At around 2400 (depending on
 * the peripherial module clock) you run out of bits. However the
 * lower two bits of SCSMR allow the module clock to be divided down,
 * scaling the value which is needed in SCBRR.
 *
 * -- Stuart Menefy - 23 May 2000
 *
 * I meant, why would anyone bother with bitrates below 2400.
 *
 * -- Greg Banks - 7Jul2000
 *
 * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 * tape reader as a console!
 *
 * -- Mitch Davis - 15 Jul 2000
 */

#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
    defined(CONFIG_CPU_SUBTYPE_SH7785)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
      defined(CONFIG_CPU_SUBTYPE_SH7720)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
#elif defined(CONFIG_SUPERH64)
#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
#else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif