aic7xxx_old.c

linux 内核源代码

        AHC_B_SCANNED             = 0x00200000,
        AHC_MULTI_CHANNEL         = 0x00400000,
        AHC_BIOS_ENABLED          = 0x00800000,
        AHC_SEEPROM_FOUND         = 0x01000000,
        AHC_TERM_ENB_LVD          = 0x02000000,
        AHC_ABORT_PENDING         = 0x04000000,
        AHC_RESET_PENDING         = 0x08000000,
#define AHC_IN_ISR_BIT              28
        AHC_IN_ISR                = 0x10000000,
        AHC_IN_ABORT              = 0x20000000,
        AHC_IN_RESET              = 0x40000000,
        AHC_EXTERNAL_SRAM         = 0x80000000
} ahc_flag_type;

typedef enum {
  AHC_NONE             = 0x0000,
  AHC_CHIPID_MASK      = 0x00ff,
  AHC_AIC7770          = 0x0001,
  AHC_AIC7850          = 0x0002,
  AHC_AIC7860          = 0x0003,
  AHC_AIC7870          = 0x0004,
  AHC_AIC7880          = 0x0005,
  AHC_AIC7890          = 0x0006,
  AHC_AIC7895          = 0x0007,
  AHC_AIC7896          = 0x0008,
  AHC_AIC7892          = 0x0009,
  AHC_AIC7899          = 0x000a,
  AHC_VL               = 0x0100,
  AHC_EISA             = 0x0200,
  AHC_PCI              = 0x0400,
} ahc_chip;

typedef enum {
  AHC_FENONE           = 0x0000,
  AHC_ULTRA            = 0x0001,
  AHC_ULTRA2           = 0x0002,
  AHC_WIDE             = 0x0004,
  AHC_TWIN             = 0x0008,
  AHC_MORE_SRAM        = 0x0010,
  AHC_CMD_CHAN         = 0x0020,
  AHC_QUEUE_REGS       = 0x0040,
  AHC_SG_PRELOAD       = 0x0080,
  AHC_SPIOCAP          = 0x0100,
  AHC_ULTRA3           = 0x0200,
  AHC_NEW_AUTOTERM     = 0x0400,
  AHC_AIC7770_FE       = AHC_FENONE,
  AHC_AIC7850_FE       = AHC_SPIOCAP,
  AHC_AIC7860_FE       = AHC_ULTRA|AHC_SPIOCAP,
  AHC_AIC7870_FE       = AHC_FENONE,
  AHC_AIC7880_FE       = AHC_ULTRA,
  AHC_AIC7890_FE       = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|
                         AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_NEW_AUTOTERM,
  AHC_AIC7895_FE       = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA,
  AHC_AIC7896_FE       = AHC_AIC7890_FE,
  AHC_AIC7892_FE       = AHC_AIC7890_FE|AHC_ULTRA3,
  AHC_AIC7899_FE       = AHC_AIC7890_FE|AHC_ULTRA3,
} ahc_feature;

#define SCB_DMA_ADDR(scb, addr) ((unsigned long)(addr) + (scb)->scb_dma->dma_offset)

struct aic7xxx_scb_dma {
	unsigned long	       dma_offset;    /* Correction you have to add
					       * to virtual address to get
					       * dma handle in this region */
	dma_addr_t	       dma_address;   /* DMA handle of the start,
					       * for unmap */
	unsigned int	       dma_len;	      /* DMA length */
};

typedef enum {
  AHC_BUG_NONE            = 0x0000,
  AHC_BUG_TMODE_WIDEODD   = 0x0001,
  AHC_BUG_AUTOFLUSH       = 0x0002,
  AHC_BUG_CACHETHEN       = 0x0004,
  AHC_BUG_CACHETHEN_DIS   = 0x0008,
  AHC_BUG_PCI_2_1_RETRY   = 0x0010,
  AHC_BUG_PCI_MWI         = 0x0020,
  AHC_BUG_SCBCHAN_UPLOAD  = 0x0040,
} ahc_bugs;

struct aic7xxx_scb {
	struct aic7xxx_hwscb	*hscb;		/* corresponding hardware scb */
	struct scsi_cmnd	*cmd;		/* scsi_cmnd for this scb */
	struct aic7xxx_scb	*q_next;        /* next scb in queue */
	volatile scb_flag_type	flags;		/* current state of scb */
	struct hw_scatterlist	*sg_list;	/* SG list in adapter format */
	unsigned char		tag_action;
	unsigned char		sg_count;
	unsigned char		*sense_cmd;	/*
						 * Allocate 6 characters for
						 * sense command.
						 */
	unsigned char		*cmnd;
	unsigned int		sg_length;	/*
						 * We init this during
						 * buildscb so we don't have
						 * to calculate anything during
						 * underflow/overflow/stat code
						 */
	void			*kmalloc_ptr;
	struct aic7xxx_scb_dma	*scb_dma;
};

/*
 * Define a linked list of SCBs.
 */
typedef struct {
  struct aic7xxx_scb *head;
  struct aic7xxx_scb *tail;
} scb_queue_type;

static struct {
  unsigned char errno;
  const char *errmesg;
} hard_error[] = {
  { ILLHADDR,  "Illegal Host Access" },
  { ILLSADDR,  "Illegal Sequencer Address referenced" },
  { ILLOPCODE, "Illegal Opcode in sequencer program" },
  { SQPARERR,  "Sequencer Ram Parity Error" },
  { DPARERR,   "Data-Path Ram Parity Error" },
  { MPARERR,   "Scratch Ram/SCB Array Ram Parity Error" },
  { PCIERRSTAT,"PCI Error detected" },
  { CIOPARERR, "CIOBUS Parity Error" }
};

static unsigned char
generic_sense[] = { REQUEST_SENSE, 0, 0, 0, 255, 0 };

typedef struct {
  scb_queue_type free_scbs;        /*
                                    * SCBs assigned to free slot on
                                    * card (no paging required)
                                    */
  struct aic7xxx_scb   *scb_array[AIC7XXX_MAXSCB];
  struct aic7xxx_hwscb *hscbs;
  unsigned char  numscbs;          /* current number of scbs */
  unsigned char  maxhscbs;         /* hardware scbs */
  unsigned char  maxscbs;          /* max scbs including pageable scbs */
  dma_addr_t	 hscbs_dma;	   /* DMA handle to hscbs */
  unsigned int   hscbs_dma_len;    /* length of the above DMA area */
  void          *hscb_kmalloc_ptr;
} scb_data_type;

struct target_cmd {
  unsigned char mesg_bytes[4];
  unsigned char command[28];
};

#define AHC_TRANS_CUR    0x0001
#define AHC_TRANS_ACTIVE 0x0002
#define AHC_TRANS_GOAL   0x0004
#define AHC_TRANS_USER   0x0008
#define AHC_TRANS_QUITE  0x0010
typedef struct {
  unsigned char width;
  unsigned char period;
  unsigned char offset;
  unsigned char options;
} transinfo_type;

struct aic_dev_data {
  volatile scb_queue_type  delayed_scbs;
  volatile unsigned short  temp_q_depth;
  unsigned short           max_q_depth;
  volatile unsigned char   active_cmds;
  /*
   * Statistics Kept:
   *
   * Total Xfers (count for each command that has a data xfer),
   * broken down by reads && writes.
   *
   * Further sorted into a few bins for keeping tabs on how many commands
   * we get of various sizes.
   *
   */
  long w_total;                          /* total writes */
  long r_total;                          /* total reads */
  long barrier_total;			 /* total num of REQ_BARRIER commands */
  long ordered_total;			 /* How many REQ_BARRIER commands we
					    used ordered tags to satisfy */
  long w_bins[6];                       /* binned write */
  long r_bins[6];                       /* binned reads */
  transinfo_type	cur;
  transinfo_type	goal;
#define  BUS_DEVICE_RESET_PENDING       0x01
#define  DEVICE_RESET_DELAY             0x02
#define  DEVICE_PRINT_DTR               0x04
#define  DEVICE_WAS_BUSY                0x08
#define  DEVICE_DTR_SCANNED		0x10
#define  DEVICE_SCSI_3			0x20
  volatile unsigned char   flags;
  unsigned needppr:1;
  unsigned needppr_copy:1;
  unsigned needsdtr:1;
  unsigned needsdtr_copy:1;
  unsigned needwdtr:1;
  unsigned needwdtr_copy:1;
  unsigned dtr_pending:1;
  struct scsi_device *SDptr;
  struct list_head list;
};

/*
 * Define a structure used for each host adapter.  Note, in order to avoid
 * problems with architectures I can't test on (because I don't have one,
 * such as the Alpha based systems) which happen to give faults for
 * non-aligned memory accesses, care was taken to align this structure
 * in a way that gauranteed all accesses larger than 8 bits were aligned
 * on the appropriate boundary.  It's also organized to try and be more
 * cache line efficient.  Be careful when changing this lest you might hurt
 * overall performance and bring down the wrath of the masses.
 */
struct aic7xxx_host {
  /*
   *  This is the first 64 bytes in the host struct
   */

  /*
   * We are grouping things here....first, items that get either read or
   * written with nearly every interrupt
   */
	volatile long	flags;
	ahc_feature	features;	/* chip features */
	unsigned long	base;		/* card base address */
	volatile unsigned char  __iomem *maddr;	/* memory mapped address */
	unsigned long	isr_count;	/* Interrupt count */
	unsigned long	spurious_int;
	scb_data_type	*scb_data;
	struct aic7xxx_cmd_queue {
		struct scsi_cmnd *head;
		struct scsi_cmnd *tail;
	} completeq;

	/*
	* Things read/written on nearly every entry into aic7xxx_queue()
	*/
	volatile scb_queue_type	waiting_scbs;
	unsigned char	unpause;	/* unpause value for HCNTRL */
	unsigned char	pause;		/* pause value for HCNTRL */
	volatile unsigned char	qoutfifonext;
	volatile unsigned char	activescbs;	/* active scbs */
	volatile unsigned char	max_activescbs;
	volatile unsigned char	qinfifonext;
	volatile unsigned char	*untagged_scbs;
	volatile unsigned char	*qoutfifo;
	volatile unsigned char	*qinfifo;

	unsigned char	dev_last_queue_full[MAX_TARGETS];
	unsigned char	dev_last_queue_full_count[MAX_TARGETS];
	unsigned short	ultraenb; /* Gets downloaded to card as a bitmap */
	unsigned short	discenable; /* Gets downloaded to card as a bitmap */
	transinfo_type	user[MAX_TARGETS];

	unsigned char	msg_buf[13];	/* The message for the target */
	unsigned char	msg_type;
#define MSG_TYPE_NONE              0x00
#define MSG_TYPE_INITIATOR_MSGOUT  0x01
#define MSG_TYPE_INITIATOR_MSGIN   0x02
	unsigned char	msg_len;	/* Length of message */
	unsigned char	msg_index;	/* Index into msg_buf array */


	/*
	 * We put the less frequently used host structure items
	 * after the more frequently used items to try and ease
	 * the burden on the cache subsystem.
	 * These entries are not *commonly* accessed, whereas
	 * the preceding entries are accessed very often.
	 */

	unsigned int	irq;		/* IRQ for this adapter */
	int		instance;	/* aic7xxx instance number */
	int		scsi_id;	/* host adapter SCSI ID */
	int		scsi_id_b;	/* channel B for twin adapters */
	unsigned int	bios_address;
	int		board_name_index;
	unsigned short	bios_control;		/* bios control - SEEPROM */
	unsigned short	adapter_control;	/* adapter control - SEEPROM */
	struct pci_dev	*pdev;
	unsigned char	pci_bus;
	unsigned char	pci_device_fn;
	struct seeprom_config	sc;
	unsigned short	sc_type;
	unsigned short	sc_size;
	struct aic7xxx_host	*next;	/* allow for multiple IRQs */
	struct Scsi_Host	*host;	/* pointer to scsi host */
	struct list_head	 aic_devs; /* all aic_dev structs on host */
	int		host_no;	/* SCSI host number */
	unsigned long	mbase;		/* I/O memory address */
	ahc_chip	chip;		/* chip type */
	ahc_bugs	bugs;
	dma_addr_t	fifo_dma;	/* DMA handle for fifo arrays */
};

/*
 * Valid SCSIRATE values. (p. 3-17)
 * Provides a mapping of transfer periods in ns/4 to the proper value to
 * stick in the SCSIRATE reg to use that transfer rate.
 */
#define AHC_SYNCRATE_ULTRA3 0
#define AHC_SYNCRATE_ULTRA2 1
#define AHC_SYNCRATE_ULTRA  3
#define AHC_SYNCRATE_FAST   6
#define AHC_SYNCRATE_CRC 0x40
#define AHC_SYNCRATE_SE  0x10
static struct aic7xxx_syncrate {
  /* Rates in Ultra mode have bit 8 of sxfr set */
#define                ULTRA_SXFR 0x100
  int sxfr_ultra2;
  int sxfr;
  unsigned char period;
  const char *rate[2];
} aic7xxx_syncrates[] = {
  { 0x42,  0x000,   9,  {"80.0", "160.0"} },
  { 0x13,  0x000,  10,  {"40.0", "80.0"} },
  { 0x14,  0x000,  11,  {"33.0", "66.6"} },
  { 0x15,  0x100,  12,  {"20.0", "40.0"} },
  { 0x16,  0x110,  15,  {"16.0", "32.0"} },
  { 0x17,  0x120,  18,  {"13.4", "26.8"} },
  { 0x18,  0x000,  25,  {"10.0", "20.0"} },
  { 0x19,  0x010,  31,  {"8.0",  "16.0"} },
  { 0x1a,  0x020,  37,  {"6.67", "13.3"} },
  { 0x1b,  0x030,  43,  {"5.7",  "11.4"} },
  { 0x10,  0x040,  50,  {"5.0",  "10.0"} },
  { 0x00,  0x050,  56,  {"4.4",  "8.8" } },
  { 0x00,  0x060,  62,  {"4.0",  "8.0" } },
  { 0x00,  0x070,  68,  {"3.6",  "7.2" } },
  { 0x00,  0x000,  0,   {NULL, NULL}   },
};

#define CTL_OF_SCB(scb) (((scb->hscb)->target_channel_lun >> 3) & 0x1),  \
                        (((scb->hscb)->target_channel_lun >> 4) & 0xf), \
                        ((scb->hscb)->target_channel_lun & 0x07)

#define CTL_OF_CMD(cmd) ((cmd->device->channel) & 0x01),  \
                        ((cmd->device->id) & 0x0f), \
                        ((cmd->device->lun) & 0x07)

#define TARGET_INDEX(cmd)  ((cmd)->device->id | ((cmd)->device->channel << 3))

/*
 * A nice little define to make doing our printks a little easier
 */

#define WARN_LEAD KERN_WARNING "(scsi%d:%d:%d:%d) "
#define INFO_LEAD KERN_INFO "(scsi%d:%d:%d:%d) "

/*
 * XXX - these options apply unilaterally to _all_ 274x/284x/294x
 *       cards in the system.  This should be fixed.  Exceptions to this