qla_def.h

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/*
 * QLogic Fibre Channel HBA Driver
 * Copyright (c)  2003-2005 QLogic Corporation
 *
 * See LICENSE.qla2xxx for copyright and licensing details.
 */
#ifndef __QLA_DEF_H
#define __QLA_DEF_H

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/dmapool.h>
#include <linux/mempool.h>
#include <linux/spinlock.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/workqueue.h>
#include <linux/firmware.h>
#include <linux/aer.h>
#include <asm/semaphore.h>

#include <scsi/scsi.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_transport_fc.h>

#define QLA2XXX_DRIVER_NAME  "qla2xxx"

/*
 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
 * but that's fine as we don't look at the last 24 ones for
 * ISP2100 HBAs.
 */
#define MAILBOX_REGISTER_COUNT_2100	8
#define MAILBOX_REGISTER_COUNT		32

#define QLA2200A_RISC_ROM_VER	4
#define FPM_2300		6
#define FPM_2310		7

#include "qla_settings.h"

/*
 * Data bit definitions
 */
#define BIT_0	0x1
#define BIT_1	0x2
#define BIT_2	0x4
#define BIT_3	0x8
#define BIT_4	0x10
#define BIT_5	0x20
#define BIT_6	0x40
#define BIT_7	0x80
#define BIT_8	0x100
#define BIT_9	0x200
#define BIT_10	0x400
#define BIT_11	0x800
#define BIT_12	0x1000
#define BIT_13	0x2000
#define BIT_14	0x4000
#define BIT_15	0x8000
#define BIT_16	0x10000
#define BIT_17	0x20000
#define BIT_18	0x40000
#define BIT_19	0x80000
#define BIT_20	0x100000
#define BIT_21	0x200000
#define BIT_22	0x400000
#define BIT_23	0x800000
#define BIT_24	0x1000000
#define BIT_25	0x2000000
#define BIT_26	0x4000000
#define BIT_27	0x8000000
#define BIT_28	0x10000000
#define BIT_29	0x20000000
#define BIT_30	0x40000000
#define BIT_31	0x80000000

#define LSB(x)	((uint8_t)(x))
#define MSB(x)	((uint8_t)((uint16_t)(x) >> 8))

#define LSW(x)	((uint16_t)(x))
#define MSW(x)	((uint16_t)((uint32_t)(x) >> 16))

#define LSD(x)	((uint32_t)((uint64_t)(x)))
#define MSD(x)	((uint32_t)((((uint64_t)(x)) >> 16) >> 16))


/*
 * I/O register
*/

#define RD_REG_BYTE(addr)		readb(addr)
#define RD_REG_WORD(addr)		readw(addr)
#define RD_REG_DWORD(addr)		readl(addr)
#define RD_REG_BYTE_RELAXED(addr)	readb_relaxed(addr)
#define RD_REG_WORD_RELAXED(addr)	readw_relaxed(addr)
#define RD_REG_DWORD_RELAXED(addr)	readl_relaxed(addr)
#define WRT_REG_BYTE(addr, data)	writeb(data,addr)
#define WRT_REG_WORD(addr, data)	writew(data,addr)
#define WRT_REG_DWORD(addr, data)	writel(data,addr)

/*
 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
 * 133Mhz slot.
 */
#define RD_REG_WORD_PIO(addr)		(inw((unsigned long)addr))
#define WRT_REG_WORD_PIO(addr, data)	(outw(data,(unsigned long)addr))

/*
 * Fibre Channel device definitions.
 */
#define WWN_SIZE		8	/* Size of WWPN, WWN & WWNN */
#define MAX_FIBRE_DEVICES	512
#define MAX_FIBRE_LUNS  	0xFFFF
#define	MAX_RSCN_COUNT		32
#define	MAX_HOST_COUNT		16

/*
 * Host adapter default definitions.
 */
#define MAX_BUSES		1  /* We only have one bus today */
#define MAX_TARGETS_2100	MAX_FIBRE_DEVICES
#define MAX_TARGETS_2200	MAX_FIBRE_DEVICES
#define MIN_LUNS		8
#define MAX_LUNS		MAX_FIBRE_LUNS
#define MAX_CMDS_PER_LUN	255

/*
 * Fibre Channel device definitions.
 */
#define SNS_LAST_LOOP_ID_2100	0xfe
#define SNS_LAST_LOOP_ID_2300	0x7ff

#define LAST_LOCAL_LOOP_ID	0x7d
#define SNS_FL_PORT		0x7e
#define FABRIC_CONTROLLER	0x7f
#define SIMPLE_NAME_SERVER	0x80
#define SNS_FIRST_LOOP_ID	0x81
#define MANAGEMENT_SERVER	0xfe
#define BROADCAST		0xff

/*
 * There is no correspondence between an N-PORT id and an AL_PA.  Therefore the
 * valid range of an N-PORT id is 0 through 0x7ef.
 */
#define NPH_LAST_HANDLE		0x7ef
#define NPH_MGMT_SERVER		0x7fa		/*  FFFFFA */
#define NPH_SNS			0x7fc		/*  FFFFFC */
#define NPH_FABRIC_CONTROLLER	0x7fd		/*  FFFFFD */
#define NPH_F_PORT		0x7fe		/*  FFFFFE */
#define NPH_IP_BROADCAST	0x7ff		/*  FFFFFF */

#define MAX_CMDSZ	16		/* SCSI maximum CDB size. */
#include "qla_fw.h"

/*
 * Timeout timer counts in seconds
 */
#define PORT_RETRY_TIME			1
#define LOOP_DOWN_TIMEOUT		60
#define LOOP_DOWN_TIME			255	/* 240 */
#define	LOOP_DOWN_RESET			(LOOP_DOWN_TIME - 30)

/* Maximum outstanding commands in ISP queues (1-65535) */
#define MAX_OUTSTANDING_COMMANDS	1024

/* ISP request and response entry counts (37-65535) */
#define REQUEST_ENTRY_CNT_2100		128	/* Number of request entries. */
#define REQUEST_ENTRY_CNT_2200		2048	/* Number of request entries. */
#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM	4096	/* Number of request entries. */
#define REQUEST_ENTRY_CNT_24XX		4096	/* Number of request entries. */
#define RESPONSE_ENTRY_CNT_2100		64	/* Number of response entries.*/
#define RESPONSE_ENTRY_CNT_2300		512	/* Number of response entries.*/

/*
 * SCSI Request Block
 */
typedef struct srb {
	struct scsi_qla_host *ha;	/* HA the SP is queued on */
	struct fc_port *fcport;

	struct scsi_cmnd *cmd;		/* Linux SCSI command pkt */

	uint16_t flags;

	/* Single transfer DMA context */
	dma_addr_t dma_handle;

	uint32_t request_sense_length;
	uint8_t *request_sense_ptr;
} srb_t;

/*
 * SRB flag definitions
 */
#define SRB_TIMEOUT		BIT_0	/* Command timed out */
#define SRB_DMA_VALID		BIT_1	/* Command sent to ISP */
#define SRB_WATCHDOG		BIT_2	/* Command on watchdog list */
#define SRB_ABORT_PENDING	BIT_3	/* Command abort sent to device */

#define SRB_ABORTED		BIT_4	/* Command aborted command already */
#define SRB_RETRY		BIT_5	/* Command needs retrying */
#define SRB_GOT_SENSE		BIT_6	/* Command has sense data */
#define SRB_FAILOVER		BIT_7	/* Command in failover state */

#define SRB_BUSY		BIT_8	/* Command is in busy retry state */
#define SRB_FO_CANCEL		BIT_9	/* Command don't need to do failover */
#define SRB_IOCTL		BIT_10	/* IOCTL command. */
#define SRB_TAPE		BIT_11	/* FCP2 (Tape) command. */

/*
 * ISP I/O Register Set structure definitions.
 */
struct device_reg_2xxx {
	uint16_t flash_address; 	/* Flash BIOS address */
	uint16_t flash_data;		/* Flash BIOS data */
	uint16_t unused_1[1];		/* Gap */
	uint16_t ctrl_status;		/* Control/Status */
#define CSR_FLASH_64K_BANK	BIT_3	/* Flash upper 64K bank select */
#define CSR_FLASH_ENABLE	BIT_1	/* Flash BIOS Read/Write enable */
#define CSR_ISP_SOFT_RESET	BIT_0	/* ISP soft reset */

	uint16_t ictrl;			/* Interrupt control */
#define ICR_EN_INT		BIT_15	/* ISP enable interrupts. */
#define ICR_EN_RISC		BIT_3	/* ISP enable RISC interrupts. */

	uint16_t istatus;		/* Interrupt status */
#define ISR_RISC_INT		BIT_3	/* RISC interrupt */

	uint16_t semaphore;		/* Semaphore */
	uint16_t nvram;			/* NVRAM register. */
#define NVR_DESELECT		0
#define NVR_BUSY		BIT_15
#define NVR_WRT_ENABLE		BIT_14	/* Write enable */
#define NVR_PR_ENABLE		BIT_13	/* Protection register enable */
#define NVR_DATA_IN		BIT_3
#define NVR_DATA_OUT		BIT_2
#define NVR_SELECT		BIT_1
#define NVR_CLOCK		BIT_0

#define NVR_WAIT_CNT		20000

	union {
		struct {
			uint16_t mailbox0;
			uint16_t mailbox1;
			uint16_t mailbox2;
			uint16_t mailbox3;
			uint16_t mailbox4;
			uint16_t mailbox5;
			uint16_t mailbox6;
			uint16_t mailbox7;
			uint16_t unused_2[59];	/* Gap */
		} __attribute__((packed)) isp2100;
		struct {
						/* Request Queue */
			uint16_t req_q_in;	/*  In-Pointer */
			uint16_t req_q_out;	/*  Out-Pointer */
						/* Response Queue */
			uint16_t rsp_q_in;	/*  In-Pointer */
			uint16_t rsp_q_out;	/*  Out-Pointer */

						/* RISC to Host Status */
			uint32_t host_status;
#define HSR_RISC_INT		BIT_15	/* RISC interrupt */
#define HSR_RISC_PAUSED		BIT_8	/* RISC Paused */

					/* Host to Host Semaphore */
			uint16_t host_semaphore;
			uint16_t unused_3[17];	/* Gap */
			uint16_t mailbox0;
			uint16_t mailbox1;
			uint16_t mailbox2;
			uint16_t mailbox3;
			uint16_t mailbox4;
			uint16_t mailbox5;
			uint16_t mailbox6;
			uint16_t mailbox7;
			uint16_t mailbox8;
			uint16_t mailbox9;
			uint16_t mailbox10;
			uint16_t mailbox11;
			uint16_t mailbox12;
			uint16_t mailbox13;
			uint16_t mailbox14;
			uint16_t mailbox15;
			uint16_t mailbox16;
			uint16_t mailbox17;
			uint16_t mailbox18;
			uint16_t mailbox19;
			uint16_t mailbox20;
			uint16_t mailbox21;
			uint16_t mailbox22;
			uint16_t mailbox23;
			uint16_t mailbox24;
			uint16_t mailbox25;
			uint16_t mailbox26;
			uint16_t mailbox27;
			uint16_t mailbox28;
			uint16_t mailbox29;
			uint16_t mailbox30;
			uint16_t mailbox31;
			uint16_t fb_cmd;
			uint16_t unused_4[10];	/* Gap */
		} __attribute__((packed)) isp2300;
	} u;

	uint16_t fpm_diag_config;
	uint16_t unused_5[0x4];		/* Gap */
	uint16_t risc_hw;
	uint16_t unused_5_1;		/* Gap */
	uint16_t pcr;			/* Processor Control Register. */
	uint16_t unused_6[0x5];		/* Gap */
	uint16_t mctr;			/* Memory Configuration and Timing. */
	uint16_t unused_7[0x3];		/* Gap */
	uint16_t fb_cmd_2100;		/* Unused on 23XX */
	uint16_t unused_8[0x3];		/* Gap */
	uint16_t hccr;			/* Host command & control register. */
#define HCCR_HOST_INT		BIT_7	/* Host interrupt bit */
#define HCCR_RISC_PAUSE		BIT_5	/* Pause mode bit */
					/* HCCR commands */
#define HCCR_RESET_RISC		0x1000	/* Reset RISC */
#define HCCR_PAUSE_RISC		0x2000	/* Pause RISC */
#define HCCR_RELEASE_RISC	0x3000	/* Release RISC from reset. */
#define HCCR_SET_HOST_INT	0x5000	/* Set host interrupt */
#define HCCR_CLR_HOST_INT	0x6000	/* Clear HOST interrupt */
#define HCCR_CLR_RISC_INT	0x7000	/* Clear RISC interrupt */
#define	HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
#define HCCR_ENABLE_PARITY	0xA000	/* Enable PARITY interrupt */

	uint16_t unused_9[5];		/* Gap */
	uint16_t gpiod;			/* GPIO Data register. */
	uint16_t gpioe;			/* GPIO Enable register. */
#define GPIO_LED_MASK			0x00C0
#define GPIO_LED_GREEN_OFF_AMBER_OFF	0x0000
#define GPIO_LED_GREEN_ON_AMBER_OFF	0x0040
#define GPIO_LED_GREEN_OFF_AMBER_ON	0x0080
#define GPIO_LED_GREEN_ON_AMBER_ON	0x00C0
#define GPIO_LED_ALL_OFF		0x0000
#define GPIO_LED_RED_ON_OTHER_OFF	0x0001	/* isp2322 */
#define GPIO_LED_RGA_ON			0x00C1	/* isp2322: red green amber */

	union {
		struct {
			uint16_t unused_10[8];	/* Gap */
			uint16_t mailbox8;
			uint16_t mailbox9;
			uint16_t mailbox10;
			uint16_t mailbox11;
			uint16_t mailbox12;
			uint16_t mailbox13;
			uint16_t mailbox14;
			uint16_t mailbox15;
			uint16_t mailbox16;
			uint16_t mailbox17;
			uint16_t mailbox18;
			uint16_t mailbox19;
			uint16_t mailbox20;
			uint16_t mailbox21;
			uint16_t mailbox22;
			uint16_t mailbox23;	/* Also probe reg. */
		} __attribute__((packed)) isp2200;
	} u_end;
};

typedef union {
		struct device_reg_2xxx isp;
		struct device_reg_24xx isp24;
} device_reg_t;

#define ISP_REQ_Q_IN(ha, reg) \
	(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
	 &(reg)->u.isp2100.mailbox4 : \
	 &(reg)->u.isp2300.req_q_in)
#define ISP_REQ_Q_OUT(ha, reg) \
	(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
	 &(reg)->u.isp2100.mailbox4 : \
	 &(reg)->u.isp2300.req_q_out)
#define ISP_RSP_Q_IN(ha, reg) \
	(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
	 &(reg)->u.isp2100.mailbox5 : \
	 &(reg)->u.isp2300.rsp_q_in)
#define ISP_RSP_Q_OUT(ha, reg) \
	(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
	 &(reg)->u.isp2100.mailbox5 : \
	 &(reg)->u.isp2300.rsp_q_out)

#define MAILBOX_REG(ha, reg, num) \
	(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
	 (num < 8 ? \
	  &(reg)->u.isp2100.mailbox0 + (num) : \
	  &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
	 &(reg)->u.isp2300.mailbox0 + (num))
#define RD_MAILBOX_REG(ha, reg, num) \
	RD_REG_WORD(MAILBOX_REG(ha, reg, num))
#define WRT_MAILBOX_REG(ha, reg, num, data) \
	WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)

#define FB_CMD_REG(ha, reg) \
	(IS_QLA2100(ha) || IS_QLA2200(ha) ? \
	 &(reg)->fb_cmd_2100 : \
	 &(reg)->u.isp2300.fb_cmd)
#define RD_FB_CMD_REG(ha, reg) \
	RD_REG_WORD(FB_CMD_REG(ha, reg))
#define WRT_FB_CMD_REG(ha, reg, data) \
	WRT_REG_WORD(FB_CMD_REG(ha, reg), data)

typedef struct {
	uint32_t	out_mb;		/* outbound from driver */
	uint32_t	in_mb;			/* Incoming from RISC */
	uint16_t	mb[MAILBOX_REGISTER_COUNT];
	long		buf_size;
	void		*bufp;
	uint32_t	tov;
	uint8_t		flags;
#define MBX_DMA_IN	BIT_0
#define	MBX_DMA_OUT	BIT_1
#define IOCTL_CMD	BIT_2
} mbx_cmd_t;

#define	MBX_TOV_SECONDS	30

/*
 *  ISP product identification definitions in mailboxes after reset.
 */
#define PROD_ID_1		0x4953
#define PROD_ID_2		0x0000
#define PROD_ID_2a		0x5020
#define PROD_ID_3		0x2020

/*
 * ISP mailbox Self-Test status codes
 */
#define MBS_FRM_ALIVE		0	/* Firmware Alive. */
#define MBS_CHKSUM_ERR		1	/* Checksum Error. */
#define MBS_BUSY		4	/* Busy. */

/*
 * ISP mailbox command complete status codes
 */
#define MBS_COMMAND_COMPLETE		0x4000
#define MBS_INVALID_COMMAND		0x4001
#define MBS_HOST_INTERFACE_ERROR	0x4002
#define MBS_TEST_FAILED			0x4003
#define MBS_COMMAND_ERROR		0x4005
#define MBS_COMMAND_PARAMETER_ERROR	0x4006
#define MBS_PORT_ID_USED		0x4007
#define MBS_LOOP_ID_USED		0x4008