qla1280.h

linux 内核源代码

/******************************************************************************
*                  QLOGIC LINUX SOFTWARE
*
* QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver
* Copyright (C) 2000 Qlogic Corporation
* (www.qlogic.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
******************************************************************************/

#ifndef	_QLA1280_H
#define	_QLA1280_H

/*
 * Data bit definitions.
 */
#define BIT_0	0x1
#define BIT_1	0x2
#define BIT_2	0x4
#define BIT_3	0x8
#define BIT_4	0x10
#define BIT_5	0x20
#define BIT_6	0x40
#define BIT_7	0x80
#define BIT_8	0x100
#define BIT_9	0x200
#define BIT_10	0x400
#define BIT_11	0x800
#define BIT_12	0x1000
#define BIT_13	0x2000
#define BIT_14	0x4000
#define BIT_15	0x8000
#define BIT_16	0x10000
#define BIT_17	0x20000
#define BIT_18	0x40000
#define BIT_19	0x80000
#define BIT_20	0x100000
#define BIT_21	0x200000
#define BIT_22	0x400000
#define BIT_23	0x800000
#define BIT_24	0x1000000
#define BIT_25	0x2000000
#define BIT_26	0x4000000
#define BIT_27	0x8000000
#define BIT_28	0x10000000
#define BIT_29	0x20000000
#define BIT_30	0x40000000
#define BIT_31	0x80000000

#if MEMORY_MAPPED_IO
#define RD_REG_WORD(addr)		readw_relaxed(addr)
#define RD_REG_WORD_dmasync(addr)	readw(addr)
#define WRT_REG_WORD(addr, data)	writew(data, addr)
#else				/* MEMORY_MAPPED_IO */
#define RD_REG_WORD(addr)		inw((unsigned long)addr)
#define RD_REG_WORD_dmasync(addr)	RD_REG_WORD(addr)
#define WRT_REG_WORD(addr, data)	outw(data, (unsigned long)addr)
#endif				/* MEMORY_MAPPED_IO */

/*
 * Host adapter default definitions.
 */
#define MAX_BUSES	2	/* 2 */
#define MAX_B_BITS	1

#define MAX_TARGETS	16	/* 16 */
#define MAX_T_BITS	4	/* 4 */

#define MAX_LUNS	8	/* 32 */
#define MAX_L_BITS	3	/* 5 */

/*
 * Watchdog time quantum
 */
#define QLA1280_WDG_TIME_QUANTUM	5	/* In seconds */

/* Command retry count (0-65535) */
#define COMMAND_RETRY_COUNT		255

/* Maximum outstanding commands in ISP queues */
#define MAX_OUTSTANDING_COMMANDS	512
#define INVALID_HANDLE			(MAX_OUTSTANDING_COMMANDS + 2)

/* ISP request and response entry counts (37-65535) */
#define REQUEST_ENTRY_CNT		255 /* Number of request entries. */
#define RESPONSE_ENTRY_CNT		63  /* Number of response entries. */

/*
 * SCSI Request Block structure  (sp)  that is placed
 * on cmd->SCp location of every I/O
 */
struct srb {
	struct list_head list;		/* (8/16) LU queue */
	struct scsi_cmnd *cmd;	/* (4/8) SCSI command block */
	/* NOTE: the sp->cmd will be NULL when this completion is
	 * called, so you should know the scsi_cmnd when using this */
	struct completion *wait;
	dma_addr_t saved_dma_handle;	/* for unmap of single transfers */
	uint8_t flags;		/* (1) Status flags. */
	uint8_t dir;		/* direction of transfer */
};

/*
 * SRB flag definitions
 */
#define SRB_TIMEOUT		(1 << 0)	/* Command timed out */
#define SRB_SENT		(1 << 1)	/* Command sent to ISP */
#define SRB_ABORT_PENDING	(1 << 2)	/* Command abort sent to device */
#define SRB_ABORTED		(1 << 3)	/* Command aborted command already */

/*
 *  ISP I/O Register Set structure definitions.
 */
struct device_reg {
	uint16_t id_l;		/* ID low */
	uint16_t id_h;		/* ID high */
	uint16_t cfg_0;		/* Configuration 0 */
#define ISP_CFG0_HWMSK   0x000f	/* Hardware revision mask */
#define ISP_CFG0_1020    BIT_0	/* ISP1020 */
#define ISP_CFG0_1020A	 BIT_1	/* ISP1020A */
#define ISP_CFG0_1040	 BIT_2	/* ISP1040 */
#define ISP_CFG0_1040A	 BIT_3	/* ISP1040A */
#define ISP_CFG0_1040B	 BIT_4	/* ISP1040B */
#define ISP_CFG0_1040C	 BIT_5	/* ISP1040C */
	uint16_t cfg_1;		/* Configuration 1 */
#define ISP_CFG1_F128    BIT_6  /* 128-byte FIFO threshold */
#define ISP_CFG1_F64     BIT_4|BIT_5 /* 128-byte FIFO threshold */
#define ISP_CFG1_F32     BIT_5  /* 128-byte FIFO threshold */
#define ISP_CFG1_F16     BIT_4  /* 128-byte FIFO threshold */
#define ISP_CFG1_BENAB   BIT_2  /* Global Bus burst enable */
#define ISP_CFG1_SXP     BIT_0  /* SXP register select */
	uint16_t ictrl;		/* Interface control */
#define ISP_RESET        BIT_0	/* ISP soft reset */
#define ISP_EN_INT       BIT_1	/* ISP enable interrupts. */
#define ISP_EN_RISC      BIT_2	/* ISP enable RISC interrupts. */
#define ISP_FLASH_ENABLE BIT_8	/* Flash BIOS Read/Write enable */
#define ISP_FLASH_UPPER  BIT_9	/* Flash upper bank select */
	uint16_t istatus;	/* Interface status */
#define PCI_64BIT_SLOT   BIT_14	/* PCI 64-bit slot indicator. */
#define RISC_INT         BIT_2	/* RISC interrupt */
#define PCI_INT          BIT_1	/* PCI interrupt */
	uint16_t semaphore;	/* Semaphore */
	uint16_t nvram;		/* NVRAM register. */
#define NV_DESELECT     0
#define NV_CLOCK        BIT_0
#define NV_SELECT       BIT_1
#define NV_DATA_OUT     BIT_2
#define NV_DATA_IN      BIT_3
	uint16_t flash_data;	/* Flash BIOS data */
	uint16_t flash_address;	/* Flash BIOS address */

	uint16_t unused_1[0x06];
	
	/* cdma_* and ddma_* are 1040 only */
	uint16_t cdma_cfg;
#define CDMA_CONF_SENAB  BIT_3	/* SXP to DMA Data enable */
#define CDMA_CONF_RIRQ   BIT_2	/* RISC interrupt enable */
#define CDMA_CONF_BENAB  BIT_1	/* Bus burst enable */
#define CDMA_CONF_DIR    BIT_0	/* DMA direction (0=fifo->host 1=host->fifo) */
	uint16_t cdma_ctrl; 
	uint16_t cdma_status;   
	uint16_t cdma_fifo_status;
	uint16_t cdma_count;
	uint16_t cdma_reserved;
	uint16_t cdma_address_count_0;
	uint16_t cdma_address_count_1;
	uint16_t cdma_address_count_2;
	uint16_t cdma_address_count_3;

	uint16_t unused_2[0x06];

	uint16_t ddma_cfg;
#define DDMA_CONF_SENAB  BIT_3	/* SXP to DMA Data enable */
#define DDMA_CONF_RIRQ   BIT_2	/* RISC interrupt enable */
#define DDMA_CONF_BENAB  BIT_1	/* Bus burst enable */
#define DDMA_CONF_DIR    BIT_0	/* DMA direction (0=fifo->host 1=host->fifo) */
	uint16_t ddma_ctrl;
	uint16_t ddma_status; 
	uint16_t ddma_fifo_status;
	uint16_t ddma_xfer_count_low;
	uint16_t ddma_xfer_count_high;
	uint16_t ddma_addr_count_0;
	uint16_t ddma_addr_count_1;
	uint16_t ddma_addr_count_2;
	uint16_t ddma_addr_count_3; 

	uint16_t unused_3[0x0e];

	uint16_t mailbox0;	/* Mailbox 0 */
	uint16_t mailbox1;	/* Mailbox 1 */
	uint16_t mailbox2;	/* Mailbox 2 */
	uint16_t mailbox3;	/* Mailbox 3 */
	uint16_t mailbox4;	/* Mailbox 4 */
	uint16_t mailbox5;	/* Mailbox 5 */
	uint16_t mailbox6;	/* Mailbox 6 */
	uint16_t mailbox7;	/* Mailbox 7 */

	uint16_t unused_4[0x20];/* 0x80-0xbf Gap */

	uint16_t host_cmd;	/* Host command and control */
#define HOST_INT      BIT_7	/* host interrupt bit */
#define BIOS_ENABLE   BIT_0

	uint16_t unused_5[0x5];	/* 0xc2-0xcb Gap */

	uint16_t gpio_data;
	uint16_t gpio_enable;

	uint16_t unused_6[0x11];	/* d0-f0 */
	uint16_t scsiControlPins;	/* f2 */
};

#define MAILBOX_REGISTER_COUNT	8

/*
 *  ISP product identification definitions in mailboxes after reset.
 */
#define PROD_ID_1		0x4953
#define PROD_ID_2		0x0000
#define PROD_ID_2a		0x5020
#define PROD_ID_3		0x2020
#define PROD_ID_4		0x1

/*
 * ISP host command and control register command definitions
 */
#define HC_RESET_RISC		0x1000	/* Reset RISC */
#define HC_PAUSE_RISC		0x2000	/* Pause RISC */
#define HC_RELEASE_RISC		0x3000	/* Release RISC from reset. */
#define HC_SET_HOST_INT		0x5000	/* Set host interrupt */
#define HC_CLR_HOST_INT		0x6000	/* Clear HOST interrupt */
#define HC_CLR_RISC_INT		0x7000	/* Clear RISC interrupt */
#define HC_DISABLE_BIOS		0x9000	/* Disable BIOS. */

/*
 * ISP mailbox Self-Test status codes
 */
#define MBS_FRM_ALIVE		0	/* Firmware Alive. */
#define MBS_CHKSUM_ERR		1	/* Checksum Error. */
#define MBS_SHADOW_LD_ERR	2	/* Shadow Load Error. */
#define MBS_BUSY		4	/* Busy. */

/*
 * ISP mailbox command complete status codes
 */
#define MBS_CMD_CMP		0x4000	/* Command Complete. */
#define MBS_INV_CMD		0x4001	/* Invalid Command. */
#define MBS_HOST_INF_ERR	0x4002	/* Host Interface Error. */
#define MBS_TEST_FAILED		0x4003	/* Test Failed. */
#define MBS_CMD_ERR		0x4005	/* Command Error. */
#define MBS_CMD_PARAM_ERR	0x4006	/* Command Parameter Error. */

/*
 * ISP mailbox asynchronous event status codes
 */
#define MBA_ASYNC_EVENT		0x8000	/* Asynchronous event. */
#define MBA_BUS_RESET		0x8001	/* SCSI Bus Reset. */
#define MBA_SYSTEM_ERR		0x8002	/* System Error. */
#define MBA_REQ_TRANSFER_ERR	0x8003	/* Request Transfer Error. */
#define MBA_RSP_TRANSFER_ERR	0x8004	/* Response Transfer Error. */
#define MBA_WAKEUP_THRES	0x8005	/* Request Queue Wake-up. */
#define MBA_TIMEOUT_RESET	0x8006	/* Execution Timeout Reset. */
#define MBA_DEVICE_RESET	0x8007	/* Bus Device Reset. */
#define MBA_BUS_MODE_CHANGE	0x800E	/* SCSI bus mode transition. */
#define MBA_SCSI_COMPLETION	0x8020	/* Completion response. */

/*
 * ISP mailbox commands
 */
#define MBC_NOP				0	/* No Operation */
#define MBC_LOAD_RAM			1	/* Load RAM */
#define MBC_EXECUTE_FIRMWARE		2	/* Execute firmware */
#define MBC_DUMP_RAM			3	/* Dump RAM contents */
#define MBC_WRITE_RAM_WORD		4	/* Write ram word */
#define MBC_READ_RAM_WORD		5	/* Read ram word */
#define MBC_MAILBOX_REGISTER_TEST	6	/* Wrap incoming mailboxes */
#define MBC_VERIFY_CHECKSUM		7	/* Verify checksum */
#define MBC_ABOUT_FIRMWARE		8	/* Get firmware revision */
#define MBC_INIT_REQUEST_QUEUE		0x10	/* Initialize request queue */
#define MBC_INIT_RESPONSE_QUEUE		0x11	/* Initialize response queue */
#define MBC_EXECUTE_IOCB		0x12	/* Execute IOCB command */
#define MBC_ABORT_COMMAND		0x15	/* Abort IOCB command */
#define MBC_ABORT_DEVICE		0x16	/* Abort device (ID/LUN) */
#define MBC_ABORT_TARGET		0x17	/* Abort target (ID) */
#define MBC_BUS_RESET			0x18	/* SCSI bus reset */
#define MBC_GET_RETRY_COUNT		0x22	/* Get retry count and delay */
#define MBC_GET_TARGET_PARAMETERS	0x28	/* Get target parameters */
#define MBC_SET_INITIATOR_ID		0x30	/* Set initiator SCSI ID */
#define MBC_SET_SELECTION_TIMEOUT	0x31	/* Set selection timeout */
#define MBC_SET_RETRY_COUNT		0x32	/* Set retry count and delay */
#define MBC_SET_TAG_AGE_LIMIT		0x33	/* Set tag age limit */
#define MBC_SET_CLOCK_RATE		0x34	/* Set clock rate */
#define MBC_SET_ACTIVE_NEGATION		0x35	/* Set active negation state */
#define MBC_SET_ASYNC_DATA_SETUP	0x36	/* Set async data setup time */
#define MBC_SET_PCI_CONTROL		0x37	/* Set BUS control parameters */
#define MBC_SET_TARGET_PARAMETERS	0x38	/* Set target parameters */
#define MBC_SET_DEVICE_QUEUE		0x39	/* Set device queue parameters */
#define MBC_SET_RESET_DELAY_PARAMETERS	0x3A	/* Set reset delay parameters */
#define MBC_SET_SYSTEM_PARAMETER	0x45	/* Set system parameter word */
#define MBC_SET_FIRMWARE_FEATURES	0x4A	/* Set firmware feature word */
#define MBC_INIT_REQUEST_QUEUE_A64	0x52	/* Initialize request queue A64 */
#define MBC_INIT_RESPONSE_QUEUE_A64	0x53	/* Initialize response q A64 */
#define MBC_ENABLE_TARGET_MODE		0x55	/* Enable target mode */
#define MBC_SET_DATA_OVERRUN_RECOVERY	0x5A	/* Set data overrun recovery mode */

/*
 * ISP Get/Set Target Parameters mailbox command control flags.
 */
#define TP_PPR			BIT_5	/* PPR */
#define TP_RENEGOTIATE		BIT_8	/* Renegotiate on error. */
#define TP_STOP_QUEUE           BIT_9	/* Stop que on check condition */
#define TP_AUTO_REQUEST_SENSE   BIT_10	/* Automatic request sense. */
#define TP_TAGGED_QUEUE         BIT_11	/* Tagged queuing. */
#define TP_SYNC                 BIT_12	/* Synchronous data transfers. */
#define TP_WIDE                 BIT_13	/* Wide data transfers. */
#define TP_PARITY               BIT_14	/* Parity checking. */
#define TP_DISCONNECT           BIT_15	/* Disconnect privilege. */

/*
 * NVRAM Command values.
 */
#define NV_START_BIT		BIT_2
#define NV_WRITE_OP		(BIT_26 | BIT_24)
#define NV_READ_OP		(BIT_26 | BIT_25)
#define NV_ERASE_OP		(BIT_26 | BIT_25 | BIT_24)
#define NV_MASK_OP		(BIT_26 | BIT_25 | BIT_24)
#define NV_DELAY_COUNT		10

/*
 *  QLogic ISP1280/ISP12160 NVRAM structure definition.
 */
struct nvram {
	uint8_t id0;		/* 0 */
	uint8_t id1;		/* 1 */
	uint8_t id2;		/* 2 */
	uint8_t id3;		/* 3 */
	uint8_t version;	/* 4 */

	struct {
		uint8_t bios_configuration_mode:2;
		uint8_t bios_disable:1;
		uint8_t selectable_scsi_boot_enable:1;
		uint8_t cd_rom_boot_enable:1;
		uint8_t disable_loading_risc_code:1;
		uint8_t enable_64bit_addressing:1;
		uint8_t unused_7:1;
	} cntr_flags_1;		/* 5 */

	struct {
		uint8_t boot_lun_number:5;