3w-xxxx.h

linux 内核源代码

#define TW_MAX_CMDS_PER_LUN		      254 /* 254 for io, 1 for
                                                     chrdev ioctl, one for
                                                     internal aen post */
#define TW_BLOCK_SIZE			      0x200 /* 512-byte blocks */
#define TW_IOCTL                              0x80
#define TW_UNIT_ONLINE                        1
#define TW_IN_INTR                            1
#define TW_IN_RESET                           2
#define TW_IN_CHRDEV_IOCTL                    3
#define TW_MAX_SECTORS                        256
#define TW_MAX_IOCTL_SECTORS		      512
#define TW_AEN_WAIT_TIME                      1000
#define TW_IOCTL_WAIT_TIME                    (1 * HZ) /* 1 second */
#define TW_ISR_DONT_COMPLETE                  2
#define TW_ISR_DONT_RESULT                    3
#define TW_IOCTL_TIMEOUT                      25 /* 25 seconds */
#define TW_IOCTL_CHRDEV_TIMEOUT               60 /* 60 seconds */
#define TW_IOCTL_CHRDEV_FREE                  -1
#define TW_DMA_MASK			      DMA_32BIT_MASK
#define TW_MAX_CDB_LEN			      16

/* Bitmask macros to eliminate bitfields */

/* opcode: 5, sgloffset: 3 */
#define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
#define TW_SGL_OUT(x) ((x >> 5) & 0x7)

/* reserved_1: 4, response_id: 8, reserved_2: 20 */
#define TW_RESID_OUT(x) ((x >> 4) & 0xff)

/* unit: 4, host_id: 4 */
#define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf))
#define TW_UNIT_OUT(x) (x & 0xf)

/* Macros */
#define TW_CONTROL_REG_ADDR(x) (x->base_addr)
#define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)
#define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)
#define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)
#define TW_CLEAR_ALL_INTERRUPTS(x) (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_CLEAR_ATTENTION_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_CLEAR_HOST_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_DISABLE_INTERRUPTS(x) (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_MASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_UNMASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
#define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET | \
			TW_CONTROL_CLEAR_HOST_INTERRUPT | \
			TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
			TW_CONTROL_MASK_COMMAND_INTERRUPT | \
			TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
			TW_CONTROL_CLEAR_ERROR_STATUS | \
			TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
#define TW_STATUS_ERRORS(x) \
	(((x & TW_STATUS_PCI_ABORT) || \
	(x & TW_STATUS_PCI_PARITY_ERROR) || \
	(x & TW_STATUS_QUEUE_ERROR) || \
	(x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
	(x & TW_STATUS_MICROCONTROLLER_READY))

#ifdef TW_DEBUG
#define dprintk(msg...) printk(msg)
#else
#define dprintk(msg...) do { } while(0)
#endif

#pragma pack(1)

/* Scatter Gather List Entry */
typedef struct TAG_TW_SG_Entry {
	u32 address;
	u32 length;
} TW_SG_Entry;

typedef unsigned char TW_Sector[512];

/* Command Packet */
typedef struct TW_Command {
	unsigned char opcode__sgloffset;
	unsigned char size;
	unsigned char request_id;
	unsigned char unit__hostid;
	/* Second DWORD */
	unsigned char status;
	unsigned char flags;
	union {
		unsigned short block_count;
		unsigned short parameter_count;
		unsigned short message_credits;
	} byte6;
	union {
		struct {
			u32 lba;
			TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
			u32 padding;	/* pad to 512 bytes */
		} io;
		struct {
			TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
			u32 padding[2];
		} param;
		struct {
			u32 response_queue_pointer;
			u32 padding[125];
		} init_connection;
		struct {
			char version[504];
		} ioctl_miniport_version;
	} byte8;
} TW_Command;

#pragma pack()

typedef struct TAG_TW_Ioctl {
	unsigned char opcode;
	unsigned short table_id;
	unsigned char parameter_id;
	unsigned char parameter_size_bytes;
	unsigned char unit_index;
	unsigned char data[1];
} TW_Ioctl;

#pragma pack(1)

/* Structure for new chardev ioctls */
typedef struct TAG_TW_New_Ioctl {
	unsigned int data_buffer_length;
	unsigned char padding [508];
	TW_Command firmware_command;
	char data_buffer[1];
} TW_New_Ioctl;

/* GetParam descriptor */
typedef struct {
	unsigned short	table_id;
	unsigned char	parameter_id;
	unsigned char	parameter_size_bytes;
	unsigned char	data[1];
} TW_Param, *PTW_Param;

/* Response queue */
typedef union TAG_TW_Response_Queue {
	u32 response_id;
	u32 value;
} TW_Response_Queue;

typedef int TW_Cmd_State;

#define TW_S_INITIAL   0x1  /* Initial state */
#define TW_S_STARTED   0x2  /* Id in use */
#define TW_S_POSTED    0x4  /* Posted to the controller */
#define TW_S_PENDING   0x8  /* Waiting to be posted in isr */
#define TW_S_COMPLETED 0x10 /* Completed by isr */
#define TW_S_FINISHED  0x20 /* I/O completely done */
#define TW_START_MASK (TW_S_STARTED | TW_S_POSTED | TW_S_PENDING | TW_S_COMPLETED)

/* Command header for ATA pass-thru */
typedef struct TAG_TW_Passthru
{
	unsigned char opcode__sgloffset;
	unsigned char size;
	unsigned char request_id;
	unsigned char aport__hostid;
	unsigned char status;
	unsigned char flags;
	unsigned short param;
	unsigned short features;
	unsigned short sector_count;
	unsigned short sector_num;
	unsigned short cylinder_lo;
	unsigned short cylinder_hi;
	unsigned char drive_head;
	unsigned char command;
	TW_SG_Entry sg_list[TW_ATA_PASS_SGL_MAX];
	unsigned char padding[12];
} TW_Passthru;

typedef struct TAG_TW_Device_Extension {
	u32			base_addr;
	unsigned long		*alignment_virtual_address[TW_Q_LENGTH];
	unsigned long		alignment_physical_address[TW_Q_LENGTH];
	int			is_unit_present[TW_MAX_UNITS];
	unsigned long		*command_packet_virtual_address[TW_Q_LENGTH];
	unsigned long		command_packet_physical_address[TW_Q_LENGTH];
	struct pci_dev		*tw_pci_dev;
	struct scsi_cmnd	*srb[TW_Q_LENGTH];
	unsigned char		free_queue[TW_Q_LENGTH];
	unsigned char		free_head;
	unsigned char		free_tail;
	unsigned char		pending_queue[TW_Q_LENGTH];
	unsigned char		pending_head;
	unsigned char		pending_tail;
	TW_Cmd_State		state[TW_Q_LENGTH];
	u32			posted_request_count;
	u32			max_posted_request_count;
	u32			request_count_marked_pending;
	u32			pending_request_count;
	u32			max_pending_request_count;
	u32			max_sgl_entries;
	u32			sgl_entries;
	u32			num_resets;
	u32			sector_count;
	u32			max_sector_count;
	u32			aen_count;
	struct Scsi_Host	*host;
	struct mutex		ioctl_lock;
	unsigned short		aen_queue[TW_Q_LENGTH];
	unsigned char		aen_head;
	unsigned char		aen_tail;
	volatile long		flags; /* long req'd for set_bit --RR */
	int			reset_print;
	volatile int		chrdev_request_id;
	wait_queue_head_t	ioctl_wqueue;
} TW_Device_Extension;

#pragma pack()

#endif /* _3W_XXXX_H */