aic94xx_dump.c

linux 内核源代码

/*
 * Aic94xx SAS/SATA driver dump interface.
 *
 * Copyright (C) 2004 Adaptec, Inc.  All rights reserved.
 * Copyright (C) 2004 David Chaw <[e-mail]>
 * Copyright (C) 2005 Luben Tuikov <[e-mail]>
 *
 * This file is licensed under GPLv2.
 *
 * This file is part of the aic94xx driver.
 *
 * The aic94xx driver is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; version 2 of the
 * License.
 *
 * The aic94xx driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with the aic94xx driver; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 *
 * 2005/07/14/LT  Complete overhaul of this file.  Update pages, register
 * locations, names, etc.  Make use of macros.  Print more information.
 * Print all cseq and lseq mip and mdp.
 *
 */

#include "linux/pci.h"
#include "aic94xx.h"
#include "aic94xx_reg.h"
#include "aic94xx_reg_def.h"
#include "aic94xx_sas.h"

#include "aic94xx_dump.h"

#ifdef ASD_DEBUG

#define MD(x)	    (1 << (x))
#define MODE_COMMON (1 << 31)
#define MODE_0_7    (0xFF)

static const struct lseq_cio_regs {
	char	*name;
	u32	offs;
	u8	width;
	u32	mode;
} LSEQmCIOREGS[] = {
	{"LmMnSCBPTR",    0x20, 16, MD(0)|MD(1)|MD(2)|MD(3)|MD(4) },
	{"LmMnDDBPTR",    0x22, 16, MD(0)|MD(1)|MD(2)|MD(3)|MD(4) },
	{"LmREQMBX",      0x30, 32, MODE_COMMON },
	{"LmRSPMBX",      0x34, 32, MODE_COMMON },
	{"LmMnINT",       0x38, 32, MODE_0_7 },
	{"LmMnINTEN",     0x3C, 32, MODE_0_7 },
	{"LmXMTPRIMD",    0x40, 32, MODE_COMMON },
	{"LmXMTPRIMCS",   0x44,  8, MODE_COMMON },
	{"LmCONSTAT",     0x45,  8, MODE_COMMON },
	{"LmMnDMAERRS",   0x46,  8, MD(0)|MD(1) },
	{"LmMnSGDMAERRS", 0x47,  8, MD(0)|MD(1) },
	{"LmMnEXPHDRP",   0x48,  8, MD(0) },
	{"LmMnSASAALIGN", 0x48,  8, MD(1) },
	{"LmMnMSKHDRP",   0x49,  8, MD(0) },
	{"LmMnSTPALIGN",  0x49,  8, MD(1) },
	{"LmMnRCVHDRP",   0x4A,  8, MD(0) },
	{"LmMnXMTHDRP",   0x4A,  8, MD(1) },
	{"LmALIGNMODE",   0x4B,  8, MD(1) },
	{"LmMnEXPRCVCNT", 0x4C, 32, MD(0) },
	{"LmMnXMTCNT",    0x4C, 32, MD(1) },
	{"LmMnCURRTAG",   0x54, 16, MD(0) },
	{"LmMnPREVTAG",   0x56, 16, MD(0) },
	{"LmMnACKOFS",    0x58,  8, MD(1) },
	{"LmMnXFRLVL",    0x59,  8, MD(0)|MD(1) },
	{"LmMnSGDMACTL",  0x5A,  8, MD(0)|MD(1) },
	{"LmMnSGDMASTAT", 0x5B,  8, MD(0)|MD(1) },
	{"LmMnDDMACTL",   0x5C,  8, MD(0)|MD(1) },
	{"LmMnDDMASTAT",  0x5D,  8, MD(0)|MD(1) },
	{"LmMnDDMAMODE",  0x5E, 16, MD(0)|MD(1) },
	{"LmMnPIPECTL",   0x61,  8, MD(0)|MD(1) },
	{"LmMnACTSCB",    0x62, 16, MD(0)|MD(1) },
	{"LmMnSGBHADR",   0x64,  8, MD(0)|MD(1) },
	{"LmMnSGBADR",    0x65,  8, MD(0)|MD(1) },
	{"LmMnSGDCNT",    0x66,  8, MD(0)|MD(1) },
	{"LmMnSGDMADR",   0x68, 32, MD(0)|MD(1) },
	{"LmMnSGDMADR",   0x6C, 32, MD(0)|MD(1) },
	{"LmMnXFRCNT",    0x70, 32, MD(0)|MD(1) },
	{"LmMnXMTCRC",    0x74, 32, MD(1) },
	{"LmCURRTAG",     0x74, 16, MD(0) },
	{"LmPREVTAG",     0x76, 16, MD(0) },
	{"LmMnDPSEL",     0x7B,  8, MD(0)|MD(1) },
	{"LmDPTHSTAT",    0x7C,  8, MODE_COMMON },
	{"LmMnHOLDLVL",   0x7D,  8, MD(0) },
	{"LmMnSATAFS",    0x7E,  8, MD(1) },
	{"LmMnCMPLTSTAT", 0x7F,  8, MD(0)|MD(1) },
	{"LmPRMSTAT0",    0x80, 32, MODE_COMMON },
	{"LmPRMSTAT1",    0x84, 32, MODE_COMMON },
	{"LmGPRMINT",     0x88,  8, MODE_COMMON },
        {"LmMnCURRSCB",   0x8A, 16, MD(0) },
	{"LmPRMICODE",    0x8C, 32, MODE_COMMON },
	{"LmMnRCVCNT",    0x90, 16, MD(0) },
	{"LmMnBUFSTAT",   0x92, 16, MD(0) },
	{"LmMnXMTHDRSIZE",0x92,  8, MD(1) },
	{"LmMnXMTSIZE",   0x93,  8, MD(1) },
	{"LmMnTGTXFRCNT", 0x94, 32, MD(0) },
	{"LmMnEXPROFS",   0x98, 32, MD(0) },
	{"LmMnXMTROFS",   0x98, 32, MD(1) },
	{"LmMnRCVROFS",   0x9C, 32, MD(0) },
	{"LmCONCTL",      0xA0, 16, MODE_COMMON },
	{"LmBITLTIMER",   0xA2, 16, MODE_COMMON },
	{"LmWWNLOW",      0xA8, 32, MODE_COMMON },
	{"LmWWNHIGH",     0xAC, 32, MODE_COMMON },
	{"LmMnFRMERR",    0xB0, 32, MD(0) },
	{"LmMnFRMERREN",  0xB4, 32, MD(0) },
	{"LmAWTIMER",     0xB8, 16, MODE_COMMON },
	{"LmAWTCTL",      0xBA,  8, MODE_COMMON },
	{"LmMnHDRCMPS",   0xC0, 32, MD(0) },
	{"LmMnXMTSTAT",   0xC4,  8, MD(1) },
	{"LmHWTSTATEN",   0xC5,  8, MODE_COMMON },
	{"LmMnRRDYRC",    0xC6,  8, MD(0) },
        {"LmMnRRDYTC",    0xC6,  8, MD(1) },
	{"LmHWTSTAT",     0xC7,  8, MODE_COMMON },
	{"LmMnDATABUFADR",0xC8, 16, MD(0)|MD(1) },
	{"LmDWSSTATUS",   0xCB,  8, MODE_COMMON },
	{"LmMnACTSTAT",   0xCE, 16, MD(0)|MD(1) },
	{"LmMnREQSCB",    0xD2, 16, MD(0)|MD(1) },
	{"LmXXXPRIM",     0xD4, 32, MODE_COMMON },
	{"LmRCVASTAT",    0xD9,  8, MODE_COMMON },
	{"LmINTDIS1",     0xDA,  8, MODE_COMMON },
	{"LmPSTORESEL",   0xDB,  8, MODE_COMMON },
	{"LmPSTORE",      0xDC, 32, MODE_COMMON },
	{"LmPRIMSTAT0EN", 0xE0, 32, MODE_COMMON },
	{"LmPRIMSTAT1EN", 0xE4, 32, MODE_COMMON },
	{"LmDONETCTL",    0xF2, 16, MODE_COMMON },
	{NULL, 0, 0, 0 }
};
/*
static struct lseq_cio_regs LSEQmOOBREGS[] = {
   {"OOB_BFLTR"        ,0x100, 8, MD(5)},
   {"OOB_INIT_MIN"     ,0x102,16, MD(5)},
   {"OOB_INIT_MAX"     ,0x104,16, MD(5)},
   {"OOB_INIT_NEG"     ,0x106,16, MD(5)},
   {"OOB_SAS_MIN"      ,0x108,16, MD(5)},
   {"OOB_SAS_MAX"      ,0x10A,16, MD(5)},
   {"OOB_SAS_NEG"      ,0x10C,16, MD(5)},
   {"OOB_WAKE_MIN"     ,0x10E,16, MD(5)},
   {"OOB_WAKE_MAX"     ,0x110,16, MD(5)},
   {"OOB_WAKE_NEG"     ,0x112,16, MD(5)},
   {"OOB_IDLE_MAX"     ,0x114,16, MD(5)},
   {"OOB_BURST_MAX"    ,0x116,16, MD(5)},
   {"OOB_XMIT_BURST"   ,0x118, 8, MD(5)},
   {"OOB_SEND_PAIRS"   ,0x119, 8, MD(5)},
   {"OOB_INIT_IDLE"    ,0x11A, 8, MD(5)},
   {"OOB_INIT_NEGO"    ,0x11C, 8, MD(5)},
   {"OOB_SAS_IDLE"     ,0x11E, 8, MD(5)},
   {"OOB_SAS_NEGO"     ,0x120, 8, MD(5)},
   {"OOB_WAKE_IDLE"    ,0x122, 8, MD(5)},
   {"OOB_WAKE_NEGO"    ,0x124, 8, MD(5)},
   {"OOB_DATA_KBITS"   ,0x126, 8, MD(5)},
   {"OOB_BURST_DATA"   ,0x128,32, MD(5)},
   {"OOB_ALIGN_0_DATA" ,0x12C,32, MD(5)},
   {"OOB_ALIGN_1_DATA" ,0x130,32, MD(5)},
   {"OOB_SYNC_DATA"    ,0x134,32, MD(5)},
   {"OOB_D10_2_DATA"   ,0x138,32, MD(5)},
   {"OOB_PHY_RST_CNT"  ,0x13C,32, MD(5)},
   {"OOB_SIG_GEN"      ,0x140, 8, MD(5)},
   {"OOB_XMIT"         ,0x141, 8, MD(5)},
   {"FUNCTION_MAKS"    ,0x142, 8, MD(5)},
   {"OOB_MODE"         ,0x143, 8, MD(5)},
   {"CURRENT_STATUS"   ,0x144, 8, MD(5)},
   {"SPEED_MASK"       ,0x145, 8, MD(5)},
   {"PRIM_COUNT"       ,0x146, 8, MD(5)},
   {"OOB_SIGNALS"      ,0x148, 8, MD(5)},
   {"OOB_DATA_DET"     ,0x149, 8, MD(5)},
   {"OOB_TIME_OUT"     ,0x14C, 8, MD(5)},
   {"OOB_TIMER_ENABLE" ,0x14D, 8, MD(5)},
   {"OOB_STATUS"       ,0x14E, 8, MD(5)},
   {"HOT_PLUG_DELAY"   ,0x150, 8, MD(5)},
   {"RCD_DELAY"        ,0x151, 8, MD(5)},
   {"COMSAS_TIMER"     ,0x152, 8, MD(5)},
   {"SNTT_DELAY"       ,0x153, 8, MD(5)},
   {"SPD_CHNG_DELAY"   ,0x154, 8, MD(5)},
   {"SNLT_DELAY"       ,0x155, 8, MD(5)},
   {"SNWT_DELAY"       ,0x156, 8, MD(5)},
   {"ALIGN_DELAY"      ,0x157, 8, MD(5)},
   {"INT_ENABLE_0"     ,0x158, 8, MD(5)},
   {"INT_ENABLE_1"     ,0x159, 8, MD(5)},
   {"INT_ENABLE_2"     ,0x15A, 8, MD(5)},
   {"INT_ENABLE_3"     ,0x15B, 8, MD(5)},
   {"OOB_TEST_REG"     ,0x15C, 8, MD(5)},
   {"PHY_CONTROL_0"    ,0x160, 8, MD(5)},
   {"PHY_CONTROL_1"    ,0x161, 8, MD(5)},
   {"PHY_CONTROL_2"    ,0x162, 8, MD(5)},
   {"PHY_CONTROL_3"    ,0x163, 8, MD(5)},
   {"PHY_OOB_CAL_TX"   ,0x164, 8, MD(5)},
   {"PHY_OOB_CAL_RX"   ,0x165, 8, MD(5)},
   {"OOB_PHY_CAL_TX"   ,0x166, 8, MD(5)},
   {"OOB_PHY_CAL_RX"   ,0x167, 8, MD(5)},
   {"PHY_CONTROL_4"    ,0x168, 8, MD(5)},
   {"PHY_TEST"         ,0x169, 8, MD(5)},
   {"PHY_PWR_CTL"      ,0x16A, 8, MD(5)},
   {"PHY_PWR_DELAY"    ,0x16B, 8, MD(5)},
   {"OOB_SM_CON"       ,0x16C, 8, MD(5)},
   {"ADDR_TRAP_1"      ,0x16D, 8, MD(5)},
   {"ADDR_NEXT_1"      ,0x16E, 8, MD(5)},
   {"NEXT_ST_1"        ,0x16F, 8, MD(5)},
   {"OOB_SM_STATE"     ,0x170, 8, MD(5)},
   {"ADDR_TRAP_2"      ,0x171, 8, MD(5)},
   {"ADDR_NEXT_2"      ,0x172, 8, MD(5)},
   {"NEXT_ST_2"        ,0x173, 8, MD(5)},
   {NULL, 0, 0, 0 }
};
*/
#define STR_8BIT   "   %30s[0x%04x]:0x%02x\n"
#define STR_16BIT  "   %30s[0x%04x]:0x%04x\n"
#define STR_32BIT  "   %30s[0x%04x]:0x%08x\n"
#define STR_64BIT  "   %30s[0x%04x]:0x%llx\n"

#define PRINT_REG_8bit(_ha, _n, _r) asd_printk(STR_8BIT, #_n, _n,      \
					     asd_read_reg_byte(_ha, _r))
#define PRINT_REG_16bit(_ha, _n, _r) asd_printk(STR_16BIT, #_n, _n,     \
					      asd_read_reg_word(_ha, _r))
#define PRINT_REG_32bit(_ha, _n, _r) asd_printk(STR_32BIT, #_n, _n,      \
					      asd_read_reg_dword(_ha, _r))

#define PRINT_CREG_8bit(_ha, _n) asd_printk(STR_8BIT, #_n, _n,      \
					     asd_read_reg_byte(_ha, C##_n))
#define PRINT_CREG_16bit(_ha, _n) asd_printk(STR_16BIT, #_n, _n,     \
					      asd_read_reg_word(_ha, C##_n))
#define PRINT_CREG_32bit(_ha, _n) asd_printk(STR_32BIT, #_n, _n,      \
					      asd_read_reg_dword(_ha, C##_n))

#define MSTR_8BIT   "   Mode:%02d %30s[0x%04x]:0x%02x\n"
#define MSTR_16BIT  "   Mode:%02d %30s[0x%04x]:0x%04x\n"
#define MSTR_32BIT  "   Mode:%02d %30s[0x%04x]:0x%08x\n"

#define PRINT_MREG_8bit(_ha, _m, _n, _r) asd_printk(MSTR_8BIT, _m, #_n, _n,   \
					     asd_read_reg_byte(_ha, _r))
#define PRINT_MREG_16bit(_ha, _m, _n, _r) asd_printk(MSTR_16BIT, _m, #_n, _n, \
					      asd_read_reg_word(_ha, _r))
#define PRINT_MREG_32bit(_ha, _m, _n, _r) asd_printk(MSTR_32BIT, _m, #_n, _n, \
					      asd_read_reg_dword(_ha, _r))

/* can also be used for MD when the register is mode aware already */
#define PRINT_MIS_byte(_ha, _n) asd_printk(STR_8BIT, #_n,CSEQ_##_n-CMAPPEDSCR,\
                                           asd_read_reg_byte(_ha, CSEQ_##_n))
#define PRINT_MIS_word(_ha, _n) asd_printk(STR_16BIT,#_n,CSEQ_##_n-CMAPPEDSCR,\
                                           asd_read_reg_word(_ha, CSEQ_##_n))
#define PRINT_MIS_dword(_ha, _n)                      \
        asd_printk(STR_32BIT,#_n,CSEQ_##_n-CMAPPEDSCR,\
                   asd_read_reg_dword(_ha, CSEQ_##_n))
#define PRINT_MIS_qword(_ha, _n)                                       \
        asd_printk(STR_64BIT, #_n,CSEQ_##_n-CMAPPEDSCR,                \
                   (unsigned long long)(((u64)asd_read_reg_dword(_ha, CSEQ_##_n))     \
                 | (((u64)asd_read_reg_dword(_ha, (CSEQ_##_n)+4))<<32)))

#define CMDP_REG(_n, _m) (_m*(CSEQ_PAGE_SIZE*2)+CSEQ_##_n)
#define PRINT_CMDP_word(_ha, _n) \
asd_printk("%20s 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", \
	#_n, \
	asd_read_reg_word(_ha, CMDP_REG(_n, 0)), \
	asd_read_reg_word(_ha, CMDP_REG(_n, 1)), \
	asd_read_reg_word(_ha, CMDP_REG(_n, 2)), \
	asd_read_reg_word(_ha, CMDP_REG(_n, 3)), \
	asd_read_reg_word(_ha, CMDP_REG(_n, 4)), \
	asd_read_reg_word(_ha, CMDP_REG(_n, 5)), \
	asd_read_reg_word(_ha, CMDP_REG(_n, 6)), \
	asd_read_reg_word(_ha, CMDP_REG(_n, 7)))

#define PRINT_CMDP_byte(_ha, _n) \
asd_printk("%20s 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", \
	#_n, \
	asd_read_reg_byte(_ha, CMDP_REG(_n, 0)), \
	asd_read_reg_byte(_ha, CMDP_REG(_n, 1)), \
	asd_read_reg_byte(_ha, CMDP_REG(_n, 2)), \
	asd_read_reg_byte(_ha, CMDP_REG(_n, 3)), \
	asd_read_reg_byte(_ha, CMDP_REG(_n, 4)), \
	asd_read_reg_byte(_ha, CMDP_REG(_n, 5)), \
	asd_read_reg_byte(_ha, CMDP_REG(_n, 6)), \
	asd_read_reg_byte(_ha, CMDP_REG(_n, 7)))

static void asd_dump_cseq_state(struct asd_ha_struct *asd_ha)
{
	int mode;

	asd_printk("CSEQ STATE\n");

	asd_printk("ARP2 REGISTERS\n");

	PRINT_CREG_32bit(asd_ha, ARP2CTL);
	PRINT_CREG_32bit(asd_ha, ARP2INT);
	PRINT_CREG_32bit(asd_ha, ARP2INTEN);
	PRINT_CREG_8bit(asd_ha, MODEPTR);
	PRINT_CREG_8bit(asd_ha, ALTMODE);
	PRINT_CREG_8bit(asd_ha, FLAG);
	PRINT_CREG_8bit(asd_ha, ARP2INTCTL);
	PRINT_CREG_16bit(asd_ha, STACK);
	PRINT_CREG_16bit(asd_ha, PRGMCNT);
	PRINT_CREG_16bit(asd_ha, ACCUM);
	PRINT_CREG_16bit(asd_ha, SINDEX);
	PRINT_CREG_16bit(asd_ha, DINDEX);
	PRINT_CREG_8bit(asd_ha, SINDIR);
	PRINT_CREG_8bit(asd_ha, DINDIR);
	PRINT_CREG_8bit(asd_ha, JUMLDIR);
	PRINT_CREG_8bit(asd_ha, ARP2HALTCODE);
	PRINT_CREG_16bit(asd_ha, CURRADDR);
	PRINT_CREG_16bit(asd_ha, LASTADDR);
	PRINT_CREG_16bit(asd_ha, NXTLADDR);

	asd_printk("IOP REGISTERS\n");

	PRINT_REG_32bit(asd_ha, BISTCTL1, CBISTCTL);
	PRINT_CREG_32bit(asd_ha, MAPPEDSCR);

	asd_printk("CIO REGISTERS\n");

	for (mode = 0; mode < 9; mode++)
		PRINT_MREG_16bit(asd_ha, mode, MnSCBPTR, CMnSCBPTR(mode));
	PRINT_MREG_16bit(asd_ha, 15, MnSCBPTR, CMnSCBPTR(15));