aic94xx_reg_def.h

linux 内核源代码

#define 	REWIND_DIS		0x0800
#define		SC_TMR_DIS		0x04000000

#define PCIC_MBAR0_MASK	0xA8
#define		PCIC_MBAR0_SIZE_MASK 	0x1FFFE000
#define		PCIC_MBAR0_SIZE_SHIFT 	13
#define		PCIC_MBAR0_SIZE(val)	\
		    (((val) & PCIC_MBAR0_SIZE_MASK) >> PCIC_MBAR0_SIZE_SHIFT)

#define PCIC_FLASH_MBAR	0xB8

#define PCIC_INTRPT_STAT 0xD4

#define PCIC_TP_CTRL	0xFC

/*
 * EXSI Registers, Addresss Range: (0x00-0xFC)
 */
#define EXSI_REG_BASE_ADR		REG_BASE_ADDR_EXSI

#define	EXSICNFGR	(EXSI_REG_BASE_ADR + 0x00)

#define		OCMINITIALIZED		0x80000000
#define		ASIEN			0x00400000
#define		HCMODE			0x00200000
#define		PCIDEF			0x00100000
#define		COMSTOCK		0x00080000
#define		SEEPROMEND		0x00040000
#define		MSTTIMEN		0x00020000
#define		XREGEX			0x00000200
#define		NVRAMW			0x00000100
#define		NVRAMEX			0x00000080
#define		SRAMW			0x00000040
#define		SRAMEX			0x00000020
#define		FLASHW			0x00000010
#define		FLASHEX			0x00000008
#define		SEEPROMCFG		0x00000004
#define		SEEPROMTYP		0x00000002
#define		SEEPROMEX		0x00000001


#define EXSICNTRLR	(EXSI_REG_BASE_ADR + 0x04)

#define		MODINT_EN		0x00000001


#define PMSTATR		(EXSI_REG_BASE_ADR + 0x10)

#define		FLASHRST		0x00000002
#define		FLASHRDY		0x00000001


#define FLCNFGR		(EXSI_REG_BASE_ADR + 0x14)

#define		FLWEH_MASK		0x30000000
#define		FLWESU_MASK		0x0C000000
#define		FLWEPW_MASK		0x03F00000
#define		FLOEH_MASK		0x000C0000
#define 	FLOESU_MASK		0x00030000
#define 	FLOEPW_MASK		0x0000FC00
#define 	FLCSH_MASK		0x00000300
#define 	FLCSSU_MASK		0x000000C0
#define 	FLCSPW_MASK		0x0000003F

#define SRCNFGR		(EXSI_REG_BASE_ADR + 0x18)

#define		SRWEH_MASK		0x30000000
#define		SRWESU_MASK		0x0C000000
#define		SRWEPW_MASK		0x03F00000

#define		SROEH_MASK		0x000C0000
#define 	SROESU_MASK		0x00030000
#define 	SROEPW_MASK		0x0000FC00
#define		SRCSH_MASK		0x00000300
#define		SRCSSU_MASK		0x000000C0
#define		SRCSPW_MASK		0x0000003F

#define NVCNFGR		(EXSI_REG_BASE_ADR + 0x1C)

#define 	NVWEH_MASK		0x30000000
#define 	NVWESU_MASK		0x0C000000
#define 	NVWEPW_MASK		0x03F00000
#define 	NVOEH_MASK		0x000C0000
#define 	NVOESU_MASK		0x00030000
#define 	NVOEPW_MASK		0x0000FC00
#define 	NVCSH_MASK		0x00000300
#define 	NVCSSU_MASK		0x000000C0
#define 	NVCSPW_MASK		0x0000003F

#define XRCNFGR		(EXSI_REG_BASE_ADR + 0x20)

#define 	XRWEH_MASK		0x30000000
#define 	XRWESU_MASK		0x0C000000
#define 	XRWEPW_MASK		0x03F00000
#define 	XROEH_MASK		0x000C0000
#define 	XROESU_MASK		0x00030000
#define 	XROEPW_MASK		0x0000FC00
#define 	XRCSH_MASK		0x00000300
#define 	XRCSSU_MASK		0x000000C0
#define		XRCSPW_MASK		0x0000003F

#define XREGADDR	(EXSI_REG_BASE_ADR + 0x24)

#define 	XRADDRINCEN		0x80000000
#define 	XREGADD_MASK		0x007FFFFF


#define XREGDATAR	(EXSI_REG_BASE_ADR + 0x28)

#define		XREGDATA_MASK 		0x0000FFFF

#define GPIOOER		(EXSI_REG_BASE_ADR + 0x40)

#define GPIOODENR	(EXSI_REG_BASE_ADR + 0x44)

#define GPIOINVR	(EXSI_REG_BASE_ADR + 0x48)

#define GPIODATAOR	(EXSI_REG_BASE_ADR + 0x4C)

#define GPIODATAIR	(EXSI_REG_BASE_ADR + 0x50)

#define GPIOCNFGR	(EXSI_REG_BASE_ADR + 0x54)

#define		GPIO_EXTSRC		0x00000001

#define SCNTRLR		(EXSI_REG_BASE_ADR + 0xA0)

#define 	SXFERDONE		0x00000100
#define 	SXFERCNT_MASK		0x000000E0
#define 	SCMDTYP_MASK		0x0000001C
#define 	SXFERSTART		0x00000002
#define 	SXFEREN			0x00000001

#define	SRATER		(EXSI_REG_BASE_ADR + 0xA4)

#define	SADDRR		(EXSI_REG_BASE_ADR + 0xA8)

#define 	SADDR_MASK		0x0000FFFF

#define SDATAOR		(EXSI_REG_BASE_ADR + 0xAC)

#define	SDATAOR0	(EXSI_REG_BASE_ADR + 0xAC)
#define SDATAOR1	(EXSI_REG_BASE_ADR + 0xAD)
#define SDATAOR2	(EXSI_REG_BASE_ADR + 0xAE)
#define SDATAOR3	(EXSI_REG_BASE_ADR + 0xAF)

#define SDATAIR		(EXSI_REG_BASE_ADR + 0xB0)

#define SDATAIR0	(EXSI_REG_BASE_ADR + 0xB0)
#define SDATAIR1	(EXSI_REG_BASE_ADR + 0xB1)
#define SDATAIR2	(EXSI_REG_BASE_ADR + 0xB2)
#define SDATAIR3	(EXSI_REG_BASE_ADR + 0xB3)

#define ASISTAT0R	(EXSI_REG_BASE_ADR + 0xD0)
#define 	ASIFMTERR		0x00000400
#define 	ASISEECHKERR		0x00000200
#define 	ASIERR			0x00000100

#define ASISTAT1R	(EXSI_REG_BASE_ADR + 0xD4)
#define 	CHECKSUM_MASK		0x0000FFFF

#define ASIERRADDR	(EXSI_REG_BASE_ADR + 0xD8)
#define ASIERRDATAR	(EXSI_REG_BASE_ADR + 0xDC)
#define ASIERRSTATR	(EXSI_REG_BASE_ADR + 0xE0)
#define 	CPI2ASIBYTECNT_MASK	0x00070000
#define 	CPI2ASIBYTEEN_MASK      0x0000F000
#define 	CPI2ASITARGERR_MASK	0x00000F00
#define 	CPI2ASITARGMID_MASK	0x000000F0
#define 	CPI2ASIMSTERR_MASK	0x0000000F

/*
 * XSRAM, External SRAM (DWord and any BE pattern accessible)
 */
#define XSRAM_REG_BASE_ADDR             0xB8100000
#define XSRAM_SIZE                        0x100000

/*
 * NVRAM Registers, Address Range: (0x00000 - 0x3FFFF).
 */
#define		NVRAM_REG_BASE_ADR	0xBF800000
#define		NVRAM_MAX_BASE_ADR	0x003FFFFF

/* OCM base address */
#define		OCM_BASE_ADDR		0xA0000000
#define		OCM_MAX_SIZE		0x20000

/*
 * Sequencers (Central and Link) Scratch RAM page definitions.
 */

/*
 * The Central Management Sequencer (CSEQ) Scratch Memory is a 1024
 * byte memory.  It is dword accessible and has byte parity
 * protection. The CSEQ accesses it in 32 byte windows, either as mode
 * dependent or mode independent memory. Each mode has 96 bytes,
 * (three 32 byte pages 0-2, not contiguous), leaving 128 bytes of
 * Mode Independent memory (four 32 byte pages 3-7). Note that mode
 * dependent scratch memory, Mode 8, page 0-3 overlaps mode
 * independent scratch memory, pages 0-3.
 * - 896 bytes of mode dependent scratch, 96 bytes per Modes 0-7, and
 * 128 bytes in mode 8,
 * - 259 bytes of mode independent scratch, common to modes 0-15.
 *
 * Sequencer scratch RAM is 1024 bytes.  This scratch memory is
 * divided into mode dependent and mode independent scratch with this
 * memory further subdivided into pages of size 32 bytes. There are 5
 * pages (160 bytes) of mode independent scratch and 3 pages of
 * dependent scratch memory for modes 0-7 (768 bytes). Mode 8 pages
 * 0-2 dependent scratch overlap with pages 0-2 of mode independent
 * scratch memory.
 *
 * The host accesses this scratch in a different manner from the
 * central sequencer. The sequencer has to use CSEQ registers CSCRPAGE
 * and CMnSCRPAGE to access the scratch memory. A flat mapping of the
 * scratch memory is available for software convenience and to prevent
 * corruption while the sequencer is running. This memory is mapped
 * onto addresses 800h - BFFh, total of 400h bytes.
 *
 * These addresses are mapped as follows:
 *
 *        800h-83Fh   Mode Dependent Scratch Mode 0 Pages 0-1
 *        840h-87Fh   Mode Dependent Scratch Mode 1 Pages 0-1
 *        880h-8BFh   Mode Dependent Scratch Mode 2 Pages 0-1
 *        8C0h-8FFh   Mode Dependent Scratch Mode 3 Pages 0-1
 *        900h-93Fh   Mode Dependent Scratch Mode 4 Pages 0-1
 *        940h-97Fh   Mode Dependent Scratch Mode 5 Pages 0-1
 *        980h-9BFh   Mode Dependent Scratch Mode 6 Pages 0-1
 *        9C0h-9FFh   Mode Dependent Scratch Mode 7 Pages 0-1
 *        A00h-A5Fh   Mode Dependent Scratch Mode 8 Pages 0-2
 *                    Mode Independent Scratch Pages 0-2
 *        A60h-A7Fh   Mode Dependent Scratch Mode 8 Page 3
 *                    Mode Independent Scratch Page 3
 *        A80h-AFFh   Mode Independent Scratch Pages 4-7
 *        B00h-B1Fh   Mode Dependent Scratch Mode 0 Page 2
 *        B20h-B3Fh   Mode Dependent Scratch Mode 1 Page 2
 *        B40h-B5Fh   Mode Dependent Scratch Mode 2 Page 2
 *        B60h-B7Fh   Mode Dependent Scratch Mode 3 Page 2
 *        B80h-B9Fh   Mode Dependent Scratch Mode 4 Page 2
 *        BA0h-BBFh   Mode Dependent Scratch Mode 5 Page 2
 *        BC0h-BDFh   Mode Dependent Scratch Mode 6 Page 2
 *        BE0h-BFFh   Mode Dependent Scratch Mode 7 Page 2
 */

/* General macros */
#define CSEQ_PAGE_SIZE			32  /* Scratch page size (in bytes) */

/* All macros start with offsets from base + 0x800 (CMAPPEDSCR).
 * Mode dependent scratch page 0, mode 0.
 * For modes 1-7 you have to do arithmetic. */
#define CSEQ_LRM_SAVE_SINDEX		(CMAPPEDSCR + 0x0000)
#define CSEQ_LRM_SAVE_SCBPTR		(CMAPPEDSCR + 0x0002)
#define CSEQ_Q_LINK_HEAD		(CMAPPEDSCR + 0x0004)
#define CSEQ_Q_LINK_TAIL		(CMAPPEDSCR + 0x0006)
#define CSEQ_LRM_SAVE_SCRPAGE		(CMAPPEDSCR + 0x0008)

/* Mode dependent scratch page 0 mode 8 macros. */
#define CSEQ_RET_ADDR			(CMAPPEDSCR + 0x0200)
#define CSEQ_RET_SCBPTR			(CMAPPEDSCR + 0x0202)
#define CSEQ_SAVE_SCBPTR		(CMAPPEDSCR + 0x0204)
#define CSEQ_EMPTY_TRANS_CTX		(CMAPPEDSCR + 0x0206)
#define CSEQ_RESP_LEN			(CMAPPEDSCR + 0x0208)
#define CSEQ_TMF_SCBPTR			(CMAPPEDSCR + 0x020A)
#define CSEQ_GLOBAL_PREV_SCB		(CMAPPEDSCR + 0x020C)
#define CSEQ_GLOBAL_HEAD		(CMAPPEDSCR + 0x020E)
#define CSEQ_CLEAR_LU_HEAD		(CMAPPEDSCR + 0x0210)
#define CSEQ_TMF_OPCODE			(CMAPPEDSCR + 0x0212)
#define CSEQ_SCRATCH_FLAGS		(CMAPPEDSCR + 0x0213)
#define CSEQ_HSB_SITE                   (CMAPPEDSCR + 0x021A)
#define CSEQ_FIRST_INV_SCB_SITE		(CMAPPEDSCR + 0x021C)
#define CSEQ_FIRST_INV_DDB_SITE		(CMAPPEDSCR + 0x021E)

/* Mode dependent scratch page 1 mode 8 macros. */
#define CSEQ_LUN_TO_CLEAR		(CMAPPEDSCR + 0x0220)
#define CSEQ_LUN_TO_CHECK		(CMAPPEDSCR + 0x0228)

/* Mode dependent scratch page 2 mode 8 macros */
#define CSEQ_HQ_NEW_POINTER		(CMAPPEDSCR + 0x0240)
#define CSEQ_HQ_DONE_BASE		(CMAPPEDSCR + 0x0248)
#define CSEQ_HQ_DONE_POINTER		(CMAPPEDSCR + 0x0250)
#define CSEQ_HQ_DONE_PASS		(CMAPPEDSCR + 0x0254)

/* Mode independent scratch page 4 macros. */
#define CSEQ_Q_EXE_HEAD			(CMAPPEDSCR + 0x0280)
#define CSEQ_Q_EXE_TAIL			(CMAPPEDSCR + 0x0282)
#define CSEQ_Q_DONE_HEAD                (CMAPPEDSCR + 0x0284)
#define CSEQ_Q_DONE_TAIL                (CMAPPEDSCR + 0x0286)
#define CSEQ_Q_SEND_HEAD		(CMAPPEDSCR + 0x0288)
#define CSEQ_Q_SEND_TAIL		(CMAPPEDSCR + 0x028A)
#define CSEQ_Q_DMA2CHIM_HEAD		(CMAPPEDSCR + 0x028C)
#define CSEQ_Q_DMA2CHIM_TAIL		(CMAPPEDSCR + 0x028E)
#define CSEQ_Q_COPY_HEAD		(CMAPPEDSCR + 0x0290)
#define CSEQ_Q_COPY_TAIL		(CMAPPEDSCR + 0x0292)
#define CSEQ_REG0			(CMAPPEDSCR + 0x0294)
#define CSEQ_REG1			(CMAPPEDSCR + 0x0296)
#define CSEQ_REG2			(CMAPPEDSCR + 0x0298)
#define CSEQ_LINK_CTL_Q_MAP		(CMAPPEDSCR + 0x029C)
#define CSEQ_MAX_CSEQ_MODE		(CMAPPEDSCR + 0x029D)
#define CSEQ_FREE_LIST_HACK_COUNT	(CMAPPEDSCR + 0x029E)

/* Mode independent scratch page 5 macros. */
#define CSEQ_EST_NEXUS_REQ_QUEUE	(CMAPPEDSCR + 0x02A0)
#define CSEQ_EST_NEXUS_REQ_COUNT	(CMAPPEDSCR + 0x02A8)
#define CSEQ_Q_EST_NEXUS_HEAD		(CMAPPEDSCR + 0x02B0)
#define CSEQ_Q_EST_NEXUS_TAIL		(CMAPPEDSCR + 0x02B2)
#define CSEQ_NEED_EST_NEXUS_SCB		(CMAPPEDSCR + 0x02B4)
#define CSEQ_EST_NEXUS_REQ_HEAD		(CMAPPEDSCR + 0x02B6)
#define CSEQ_EST_NEXUS_REQ_TAIL		(CMAPPEDSCR + 0x02B7)
#define CSEQ_EST_NEXUS_SCB_OFFSET	(CMAPPEDSCR + 0x02B8)

/* Mode independent scratch page 6 macros. */
#define CSEQ_INT_ROUT_RET_ADDR0		(CMAPPEDSCR + 0x02C0)
#define CSEQ_INT_ROUT_RET_ADDR1		(CMAPPEDSCR + 0x02C2)
#define CSEQ_INT_ROUT_SCBPTR		(CMAPPEDSCR + 0x02C4)
#define CSEQ_INT_ROUT_MODE		(CMAPPEDSCR + 0x02C6)
#define CSEQ_ISR_SCRATCH_FLAGS		(CMAPPEDSCR + 0x02C7)
#define CSEQ_ISR_SAVE_SINDEX		(CMAPPEDSCR + 0x02C8)
#define CSEQ_ISR_SAVE_DINDEX		(CMAPPEDSCR + 0x02CA)
#define CSEQ_Q_MONIRTT_HEAD		(CMAPPEDSCR + 0x02D0)
#define CSEQ_Q_MONIRTT_TAIL		(CMAPPEDSCR + 0x02D2)
#define CSEQ_FREE_SCB_MASK		(CMAPPEDSCR + 0x02D5)
#define CSEQ_BUILTIN_FREE_SCB_HEAD	(CMAPPEDSCR + 0x02D6)
#define CSEQ_BUILTIN_FREE_SCB_TAIL	(CMAPPEDSCR + 0x02D8)
#define CSEQ_EXTENDED_FREE_SCB_HEAD	(CMAPPEDSCR + 0x02DA)
#define CSEQ_EXTENDED_FREE_SCB_TAIL	(CMAPPEDSCR + 0x02DC)

/* Mode independent scratch page 7 macros. */
#define CSEQ_EMPTY_REQ_QUEUE		(CMAPPEDSCR + 0x02E0)
#define CSEQ_EMPTY_REQ_COUNT		(CMAPPEDSCR + 0x02E8)
#define CSEQ_Q_EMPTY_HEAD		(CMAPPEDSCR + 0x02F0)
#define CSEQ_Q_EMPTY_TAIL		(CMAPPEDSCR + 0x02F2)
#define CSEQ_NEED_EMPTY_SCB		(CMAPPEDSCR + 0x02F4)
#define CSEQ_EMPTY_REQ_HEAD		(CMAPPEDSCR + 0x02F6)
#define CSEQ_EMPTY_REQ_TAIL		(CMAPPEDSCR + 0x02F7)
#define CSEQ_EMPTY_SCB_OFFSET		(CMAPPEDSCR + 0x02F8)
#define CSEQ_PRIMITIVE_DATA		(CMAPPEDSCR + 0x02FA)
#define CSEQ_TIMEOUT_CONST		(CMAPPEDSCR + 0x02FC)

/***************************************************************************
* Link m Sequencer scratch RAM is 512 bytes.
* This scratch memory is divided into mode dependent and mode
* independent scratch with this memory further subdivided into
* pages of size 32 bytes. There are 4 pages (128 bytes) of
* mode independent scratch and 4 pages of dependent scratch
* memory for modes 0-2 (384 bytes).
*
* The host accesses this scratch in a different manner from the
* link sequencer. The sequencer has to use LSEQ registers
* LmSCRPAGE and LmMnSCRPAGE to access the scratch memory. A flat
* mapping of the scratch memory is avaliable for software
* convenience and to prevent corruption while the sequencer is
* running. This memory is mapped onto addresses 800h - 9FFh.
*
* These addresses are mapped as follows:
*
*        800h-85Fh   Mode Dependent Scratch Mode 0 Pages 0-2
*        860h-87Fh   Mode Dependent Scratch Mode 0 Page 3
*                    Mode Dependent Scratch Mode 5 Page 0
*        880h-8DFh   Mode Dependent Scratch Mode 1 Pages 0-2
*        8E0h-8FFh   Mode Dependent Scratch Mode 1 Page 3
*                    Mode Dependent Scratch Mode 5 Page 1
*        900h-95Fh   Mode Dependent Scratch Mode 2 Pages 0-2
*        960h-97Fh   Mode Dependent Scratch Mode 2 Page 3
*                    Mode Dependent Scratch Mode 5 Page 2
*        980h-9DFh   Mode Independent Scratch Pages 0-3
*        9E0h-9FFh   Mode Independent Scratch Page 3
*                    Mode Dependent Scratch Mode 5 Page 3
*
****************************************************************************/
/* General macros */
#define LSEQ_MODE_SCRATCH_SIZE		0x80 /* Size of scratch RAM per mode */
#define LSEQ_PAGE_SIZE			0x20 /* Scratch page size (in bytes) */
#define LSEQ_MODE5_PAGE0_OFFSET 	0x60

/* Common mode dependent scratch page 0 macros for modes 0,1,2, and 5 */
/* Indexed using LSEQ_MODE_SCRATCH_SIZE * mode, for modes 0,1,2. */
#define LmSEQ_RET_ADDR(LinkNum)		(LmSCRATCH(LinkNum) + 0x0000)
#define LmSEQ_REG0_MODE(LinkNum)	(LmSCRATCH(LinkNum) + 0x0002)
#define LmSEQ_MODE_FLAGS(LinkNum)	(LmSCRATCH(LinkNum) + 0x0004)

/* Mode flag macros (byte 0) */
#define		SAS_SAVECTX_OCCURRED		0x80
#define		SAS_OOBSVC_OCCURRED		0x40
#define		SAS_OOB_DEVICE_PRESENT		0x20
#define		SAS_CFGHDR_OCCURRED		0x10
#define		SAS_RCV_INTS_ARE_DISABLED	0x08
#define		SAS_OOB_HOT_PLUG_CNCT		0x04
#define		SAS_AWAIT_OPEN_CONNECTION	0x02
#define		SAS_CFGCMPLT_OCCURRED		0x01

/* Mode flag macros (byte 1) */
#define		SAS_RLSSCB_OCCURRED		0x80
#define		SAS_FORCED_HEADER_MISS		0x40

#define LmSEQ_RET_ADDR2(LinkNum)	(LmSCRATCH(LinkNum) + 0x0006)
#define LmSEQ_RET_ADDR1(LinkNum)	(LmSCRATCH(LinkNum) + 0x0008)
#define LmSEQ_OPCODE_TO_CSEQ(LinkNum)	(LmSCRATCH(LinkNum) + 0x000B)
#define LmSEQ_DATA_TO_CSEQ(LinkNum)	(LmSCRATCH(LinkNum) + 0x000C)

/* Mode dependent scratch page 0 macros for mode 0 (non-common) */
/* Absolute offsets */
#define LmSEQ_FIRST_INV_DDB_SITE(LinkNum)	(LmSCRATCH(LinkNum) + 0x000E)
#define LmSEQ_EMPTY_TRANS_CTX(LinkNum)		(LmSCRATCH(LinkNum) + 0x0010)
#define LmSEQ_RESP_LEN(LinkNum)			(LmSCRATCH(LinkNum) + 0x0012)
#define LmSEQ_FIRST_INV_SCB_SITE(LinkNum)	(LmSCRATCH(LinkNum) + 0x0014)
#define LmSEQ_INTEN_SAVE(LinkNum)		(LmSCRATCH(LinkNum) + 0x0016)
#define LmSEQ_LINK_RST_FRM_LEN(LinkNum)		(LmSCRATCH(LinkNum) + 0x001A)
#define LmSEQ_LINK_RST_PROTOCOL(LinkNum)	(LmSCRATCH(LinkNum) + 0x001B)
#define LmSEQ_RESP_STATUS(LinkNum)		(LmSCRATCH(LinkNum) + 0x001C)
#define LmSEQ_LAST_LOADED_SGE(LinkNum)		(LmSCRATCH(LinkNum) + 0x001D)
#define LmSEQ_SAVE_SCBPTR(LinkNum)		(LmSCRATCH(LinkNum) + 0x001E)

/* Mode dependent scratch page 0 macros for mode 1 (non-common) */
/* Absolute offsets */
#define LmSEQ_Q_XMIT_HEAD(LinkNum)		(LmSCRATCH(LinkNum) + 0x008E)
#define LmSEQ_M1_EMPTY_TRANS_CTX(LinkNum)	(LmSCRATCH(LinkNum) + 0x0090)
#define LmSEQ_INI_CONN_TAG(LinkNum)		(LmSCRATCH(LinkNum) + 0x0092)
#define LmSEQ_FAILED_OPEN_STATUS(LinkNum)	(LmSCRATCH(LinkNum) + 0x009A)
#define LmSEQ_XMIT_REQUEST_TYPE(LinkNum)	(LmSCRATCH(LinkNum) + 0x009B)
#define LmSEQ_M1_RESP_STATUS(LinkNum)		(LmSCRATCH(LinkNum) + 0x009C)
#define LmSEQ_M1_LAST_LOADED_SGE(LinkNum)	(LmSCRATCH(LinkNum) + 0x009D)
#define LmSEQ_M1_SAVE_SCBPTR(LinkNum)		(LmSCRATCH(LinkNum) + 0x009E)

/* Mode dependent scratch page 0 macros for mode 2 (non-common) */
#define LmSEQ_PORT_COUNTER(LinkNum)		(LmSCRATCH(LinkNum) + 0x010E)
#define LmSEQ_PM_TABLE_PTR(LinkNum)		(LmSCRATCH(LinkNum) + 0x0110)
#define LmSEQ_SATA_INTERLOCK_TMR_SAVE(LinkNum)	(LmSCRATCH(LinkNum) + 0x0112)
#define LmSEQ_IP_BITL(LinkNum)			(LmSCRATCH(LinkNum) + 0x0114)
#define LmSEQ_COPY_SMP_CONN_TAG(LinkNum)	(LmSCRATCH(LinkNum) + 0x0116)
#define LmSEQ_P0M2_OFFS1AH(LinkNum)		(LmSCRATCH(LinkNum) + 0x011A)

/* Mode dependent scratch page 0 macros for modes 4/5 (non-common) */
/* Absolute offsets */
#define LmSEQ_SAVED_OOB_STATUS(LinkNum)		(LmSCRATCH(LinkNum) + 0x006E)
#define LmSEQ_SAVED_OOB_MODE(LinkNum)		(LmSCRATCH(LinkNum) + 0x006F)
#define LmSEQ_Q_LINK_HEAD(LinkNum)		(LmSCRATCH(LinkNum) + 0x0070)
#define LmSEQ_LINK_RST_ERR(LinkNum)		(LmSCRATCH(LinkNum) + 0x0072)
#define LmSEQ_SAVED_OOB_SIGNALS(LinkNum)	(LmSCRATCH(LinkNum) + 0x0073)
#define LmSEQ_SAS_RESET_MODE(LinkNum)		(LmSCRATCH(LinkNum) + 0x0074)
#define LmSEQ_LINK_RESET_RETRY_COUNT(LinkNum)	(LmSCRATCH(LinkNum) + 0x0075)
#define LmSEQ_NUM_LINK_RESET_RETRIES(LinkNum)	(LmSCRATCH(LinkNum) + 0x0076)
#define LmSEQ_OOB_INT_ENABLES(LinkNum)		(LmSCRATCH(LinkNum) + 0x0078)
#define LmSEQ_NOTIFY_TIMER_DOWN_COUNT(LinkNum)	(LmSCRATCH(LinkNum) + 0x007A)
#define LmSE