aic94xx_reg_def.h

linux 内核源代码

#define 	EN_LmPMREQP		0x00000010
#define 	EN_LmPMREQS		0x00000008
#define 	EN_LmPMACK		0x00000004
#define 	EN_LmPMNAK		0x00000002
#define 	EN_LmDMAT		0x00000001

#define LmPRIMSTAT1EN_MASK		(EN_LmHARDRST | \
					 EN_LmSYNCSRST | \
					 EN_LmPMREQP | EN_LmPMREQS | \
					 EN_LmPMACK | EN_LmPMNAK)

#define LmSMSTATE(LinkNum) 		LmSEQ_PHY_REG(0, LinkNum, 0xE8)

#define LmSMSTATEBRK(LinkNum) 		LmSEQ_PHY_REG(0, LinkNum, 0xEC)

#define LmSMDBGCTL(LinkNum) 		LmSEQ_PHY_REG(0, LinkNum, 0xF0)


/*
 * LmSEQ CIO Bus Mode 3 Register.
 * Mode 3: Configuration and Setup, IOP Context SCB.
 */
#define LmM3SATATIMER(LinkNum) 		LmSEQ_PHY_REG(3, LinkNum, 0x48)

#define LmM3INTVEC0(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0x90)

#define LmM3INTVEC1(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0x92)

#define LmM3INTVEC2(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0x94)

#define LmM3INTVEC3(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0x96)

#define LmM3INTVEC4(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0x98)

#define LmM3INTVEC5(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0x9A)

#define LmM3INTVEC6(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0x9C)

#define LmM3INTVEC7(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0x9E)

#define LmM3INTVEC8(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0xA4)

#define LmM3INTVEC9(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0xA6)

#define LmM3INTVEC10(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0xB0)

#define LmM3FRMGAP(LinkNum)		LmSEQ_PHY_REG(3, LinkNum, 0xB4)

#define LmBITL_TIMER(LinkNum) 		LmSEQ_PHY_REG(0, LinkNum, 0xA2)

#define LmWWN(LinkNum) 			LmSEQ_PHY_REG(0, LinkNum, 0xA8)


/*
 * LmSEQ CIO Bus Mode 5 Registers.
 * Mode 5: Phy/OOB Control and Status.
 */
#define LmSEQ_OOB_REG(phy_id, reg)	LmSEQ_PHY_REG(5, (phy_id), (reg))

#define OOB_BFLTR	0x100

#define		BFLTR_THR_MASK		0xF0
#define		BFLTR_TC_MASK		0x0F

#define OOB_INIT_MIN	0x102

#define OOB_INIT_MAX	0x104

#define OOB_INIT_NEG	0x106

#define	OOB_SAS_MIN	0x108

#define OOB_SAS_MAX	0x10A

#define OOB_SAS_NEG	0x10C

#define OOB_WAKE_MIN	0x10E

#define OOB_WAKE_MAX	0x110

#define OOB_WAKE_NEG	0x112

#define OOB_IDLE_MAX	0x114

#define OOB_BURST_MAX	0x116

#define OOB_DATA_KBITS	0x126

#define OOB_ALIGN_0_DATA	0x12C

#define OOB_ALIGN_1_DATA	0x130

#define D10_2_DATA_k		0x00
#define SYNC_DATA_k		0x02
#define ALIGN_1_DATA_k		0x04
#define ALIGN_0_DATA_k		0x08
#define BURST_DATA_k		0x10

#define OOB_PHY_RESET_COUNT	0x13C

#define OOB_SIG_GEN	0x140

#define		START_OOB		0x80
#define		START_DWS		0x40
#define		ALIGN_CNT3		0x30
#define 	ALIGN_CNT2		0x20
#define 	ALIGN_CNT1		0x10
#define 	ALIGN_CNT4		0x00
#define		STOP_DWS		0x08
#define		SEND_COMSAS		0x04
#define		SEND_COMINIT		0x02
#define		SEND_COMWAKE		0x01

#define OOB_XMIT	0x141

#define		TX_ENABLE		0x80
#define		XMIT_OOB_BURST		0x10
#define		XMIT_D10_2		0x08
#define		XMIT_SYNC		0x04
#define		XMIT_ALIGN_1		0x02
#define		XMIT_ALIGN_0		0x01

#define FUNCTION_MASK	0x142

#define		SAS_MODE_DIS		0x80
#define		SATA_MODE_DIS		0x40
#define		SPINUP_HOLD_DIS		0x20
#define		HOT_PLUG_DIS		0x10
#define		SATA_PS_DIS		0x08
#define		FUNCTION_MASK_DEFAULT	(SPINUP_HOLD_DIS | SATA_PS_DIS)

#define OOB_MODE	0x143

#define		SAS_MODE		0x80
#define		SATA_MODE		0x40
#define		SLOW_CLK		0x20
#define		FORCE_XMIT_15		0x08
#define		PHY_SPEED_60		0x04
#define		PHY_SPEED_30		0x02
#define		PHY_SPEED_15		0x01

#define	CURRENT_STATUS	0x144

#define		CURRENT_OOB_DONE	0x80
#define		CURRENT_LOSS_OF_SIGNAL	0x40
#define		CURRENT_SPINUP_HOLD	0x20
#define		CURRENT_HOT_PLUG_CNCT	0x10
#define		CURRENT_GTO_TIMEOUT	0x08
#define		CURRENT_OOB_TIMEOUT	0x04
#define		CURRENT_DEVICE_PRESENT	0x02
#define		CURRENT_OOB_ERROR	0x01

#define 	CURRENT_OOB1_ERROR	(CURRENT_HOT_PLUG_CNCT | \
					 CURRENT_GTO_TIMEOUT)

#define 	CURRENT_OOB2_ERROR	(CURRENT_HOT_PLUG_CNCT | \
					 CURRENT_OOB_ERROR)

#define		DEVICE_ADDED_W_CNT	(CURRENT_OOB_DONE | \
					 CURRENT_HOT_PLUG_CNCT | \
					 CURRENT_DEVICE_PRESENT)

#define		DEVICE_ADDED_WO_CNT	(CURRENT_OOB_DONE | \
					 CURRENT_DEVICE_PRESENT)

#define 	DEVICE_REMOVED		CURRENT_LOSS_OF_SIGNAL

#define		CURRENT_PHY_MASK	(CURRENT_OOB_DONE | \
					 CURRENT_LOSS_OF_SIGNAL | \
					 CURRENT_SPINUP_HOLD | \
					 CURRENT_HOT_PLUG_CNCT | \
					 CURRENT_GTO_TIMEOUT | \
					 CURRENT_DEVICE_PRESENT | \
					 CURRENT_OOB_ERROR )

#define		CURRENT_ERR_MASK	(CURRENT_LOSS_OF_SIGNAL | \
					 CURRENT_GTO_TIMEOUT | \
					 CURRENT_OOB_TIMEOUT | \
					 CURRENT_OOB_ERROR )

#define SPEED_MASK	0x145

#define		SATA_SPEED_30_DIS	0x10
#define		SATA_SPEED_15_DIS	0x08
#define		SAS_SPEED_60_DIS	0x04
#define		SAS_SPEED_30_DIS	0x02
#define		SAS_SPEED_15_DIS	0x01
#define		SAS_SPEED_MASK_DEFAULT	0x00

#define OOB_TIMER_ENABLE	0x14D

#define		HOT_PLUG_EN		0x80
#define		RCD_EN			0x40
#define 	COMTIMER_EN		0x20
#define		SNTT_EN			0x10
#define		SNLT_EN			0x04
#define		SNWT_EN			0x02
#define		ALIGN_EN		0x01

#define OOB_STATUS		0x14E

#define		OOB_DONE		0x80
#define		LOSS_OF_SIGNAL		0x40		/* ro */
#define		SPINUP_HOLD		0x20
#define		HOT_PLUG_CNCT		0x10		/* ro */
#define		GTO_TIMEOUT		0x08		/* ro */
#define		OOB_TIMEOUT		0x04		/* ro */
#define		DEVICE_PRESENT		0x02		/* ro */
#define		OOB_ERROR		0x01		/* ro */

#define		OOB_STATUS_ERROR_MASK	(LOSS_OF_SIGNAL | GTO_TIMEOUT | \
					 OOB_TIMEOUT | OOB_ERROR)

#define OOB_STATUS_CLEAR	0x14F

#define		OOB_DONE_CLR		0x80
#define		LOSS_OF_SIGNAL_CLR 	0x40
#define		SPINUP_HOLD_CLR		0x20
#define		HOT_PLUG_CNCT_CLR     	0x10
#define		GTO_TIMEOUT_CLR		0x08
#define		OOB_TIMEOUT_CLR		0x04
#define		OOB_ERROR_CLR		0x01

#define HOT_PLUG_DELAY		0x150
/* In 5 ms units. 20 = 100 ms. */
#define	HOTPLUG_DELAY_TIMEOUT		20


#define INT_ENABLE_2		0x15A

#define		OOB_DONE_EN		0x80
#define		LOSS_OF_SIGNAL_EN	0x40
#define		SPINUP_HOLD_EN		0x20
#define		HOT_PLUG_CNCT_EN	0x10
#define		GTO_TIMEOUT_EN		0x08
#define		OOB_TIMEOUT_EN		0x04
#define		DEVICE_PRESENT_EN	0x02
#define		OOB_ERROR_EN		0x01

#define PHY_CONTROL_0		0x160

#define		PHY_LOWPWREN_TX		0x80
#define		PHY_LOWPWREN_RX		0x40
#define		SPARE_REG_160_B5	0x20
#define		OFFSET_CANCEL_RX	0x10

/* bits 3:2 */
#define		PHY_RXCOMCENTER_60V	0x00
#define		PHY_RXCOMCENTER_70V	0x04
#define		PHY_RXCOMCENTER_80V	0x08
#define		PHY_RXCOMCENTER_90V	0x0C
#define 	PHY_RXCOMCENTER_MASK	0x0C

#define		PHY_RESET		0x02
#define		SAS_DEFAULT_SEL		0x01

#define PHY_CONTROL_1		0x161

/* bits 2:0 */
#define		SATA_PHY_DETLEVEL_50mv	0x00
#define		SATA_PHY_DETLEVEL_75mv	0x01
#define		SATA_PHY_DETLEVEL_100mv	0x02
#define		SATA_PHY_DETLEVEL_125mv	0x03
#define		SATA_PHY_DETLEVEL_150mv	0x04
#define		SATA_PHY_DETLEVEL_175mv	0x05
#define		SATA_PHY_DETLEVEL_200mv	0x06
#define		SATA_PHY_DETLEVEL_225mv	0x07
#define		SATA_PHY_DETLEVEL_MASK	0x07

/* bits 5:3 */
#define		SAS_PHY_DETLEVEL_50mv	0x00
#define		SAS_PHY_DETLEVEL_75mv	0x08
#define		SAS_PHY_DETLEVEL_100mv	0x10
#define		SAS_PHY_DETLEVEL_125mv	0x11
#define		SAS_PHY_DETLEVEL_150mv	0x20
#define		SAS_PHY_DETLEVEL_175mv	0x21
#define		SAS_PHY_DETLEVEL_200mv	0x30
#define		SAS_PHY_DETLEVEL_225mv	0x31
#define		SAS_PHY_DETLEVEL_MASK	0x38

#define PHY_CONTROL_2		0x162

/* bits 7:5 */
#define 	SATA_PHY_DRV_400mv	0x00
#define 	SATA_PHY_DRV_450mv	0x20
#define 	SATA_PHY_DRV_500mv	0x40
#define 	SATA_PHY_DRV_550mv	0x60
#define 	SATA_PHY_DRV_600mv	0x80
#define 	SATA_PHY_DRV_650mv	0xA0
#define 	SATA_PHY_DRV_725mv	0xC0
#define 	SATA_PHY_DRV_800mv	0xE0
#define		SATA_PHY_DRV_MASK	0xE0

/* bits 4:3 */
#define 	SATA_PREEMP_0		0x00
#define 	SATA_PREEMP_1		0x08
#define 	SATA_PREEMP_2		0x10
#define 	SATA_PREEMP_3		0x18
#define 	SATA_PREEMP_MASK	0x18

#define 	SATA_CMSH1P5		0x04

/* bits 1:0 */
#define 	SATA_SLEW_0		0x00
#define 	SATA_SLEW_1		0x01
#define 	SATA_SLEW_2		0x02
#define 	SATA_SLEW_3		0x03
#define 	SATA_SLEW_MASK		0x03

#define PHY_CONTROL_3		0x163

/* bits 7:5 */
#define 	SAS_PHY_DRV_400mv	0x00
#define 	SAS_PHY_DRV_450mv	0x20
#define 	SAS_PHY_DRV_500mv	0x40
#define 	SAS_PHY_DRV_550mv	0x60
#define 	SAS_PHY_DRV_600mv	0x80
#define 	SAS_PHY_DRV_650mv	0xA0
#define 	SAS_PHY_DRV_725mv	0xC0
#define 	SAS_PHY_DRV_800mv	0xE0
#define		SAS_PHY_DRV_MASK	0xE0

/* bits 4:3 */
#define 	SAS_PREEMP_0		0x00
#define 	SAS_PREEMP_1		0x08
#define 	SAS_PREEMP_2		0x10
#define 	SAS_PREEMP_3		0x18
#define 	SAS_PREEMP_MASK		0x18

#define 	SAS_CMSH1P5		0x04

/* bits 1:0 */
#define 	SAS_SLEW_0		0x00
#define 	SAS_SLEW_1		0x01
#define 	SAS_SLEW_2		0x02
#define 	SAS_SLEW_3		0x03
#define 	SAS_SLEW_MASK		0x03

#define PHY_CONTROL_4		0x168

#define		PHY_DONE_CAL_TX		0x80
#define		PHY_DONE_CAL_RX		0x40
#define		RX_TERM_LOAD_DIS	0x20
#define		TX_TERM_LOAD_DIS	0x10
#define		AUTO_TERM_CAL_DIS	0x08
#define		PHY_SIGDET_FLTR_EN	0x04
#define		OSC_FREQ		0x02
#define		PHY_START_CAL		0x01

/*
 * HST_PCIX2 Registers, Addresss Range: (0x00-0xFC)
 */
#define PCIX_REG_BASE_ADR		0xB8040000

#define PCIC_VENDOR_ID	0x00

#define PCIC_DEVICE_ID	0x02

#define PCIC_COMMAND	0x04

#define		INT_DIS			0x0400
#define		FBB_EN			0x0200		/* ro */
#define		SERR_EN			0x0100
#define		STEP_EN			0x0080		/* ro */
#define		PERR_EN			0x0040
#define		VGA_EN			0x0020		/* ro */
#define		MWI_EN			0x0010
#define		SPC_EN			0x0008
#define		MST_EN			0x0004
#define		MEM_EN			0x0002
#define		IO_EN			0x0001

#define	PCIC_STATUS	0x06

#define		PERR_DET		0x8000
#define		SERR_GEN		0x4000
#define		MABT_DET		0x2000
#define		TABT_DET		0x1000
#define		TABT_GEN		0x0800
#define		DPERR_DET		0x0100
#define		CAP_LIST		0x0010
#define		INT_STAT		0x0008

#define	PCIC_DEVREV_ID	0x08

#define	PCIC_CLASS_CODE	0x09

#define	PCIC_CACHELINE_SIZE	0x0C

#define	PCIC_MBAR0	0x10

#define 	PCIC_MBAR0_OFFSET	0

#define	PCIC_MBAR1	0x18

#define 	PCIC_MBAR1_OFFSET	2

#define	PCIC_IOBAR	0x20

#define 	PCIC_IOBAR_OFFSET	4

#define	PCIC_SUBVENDOR_ID	0x2C

#define PCIC_SUBSYTEM_ID	0x2E

#define PCIX_STATUS		0x44
#define 	RCV_SCE		0x20000000
#define 	UNEXP_SC	0x00080000
#define 	SC_DISCARD	0x00040000

#define ECC_CTRL_STAT		0x48
#define 	UNCOR_ECCERR	0x00000008

#define PCIC_PM_CSR		0x5C

#define		PWR_STATE_D0		0
#define		PWR_STATE_D1		1	/* not supported */
#define		PWR_STATE_D2		2 	/* not supported */
#define		PWR_STATE_D3		3

#define PCIC_BASE1	0x6C	/* internal use only */

#define		BASE1_RSVD		0xFFFFFFF8

#define PCIC_BASEA	0x70	/* internal use only */

#define		BASEA_RSVD		0xFFFFFFC0
#define 	BASEA_START		0

#define PCIC_BASEB	0x74	/* internal use only */

#define		BASEB_RSVD		0xFFFFFF80
#define		BASEB_IOMAP_MASK	0x7F
#define 	BASEB_START		0x80

#define PCIC_BASEC	0x78	/* internal use only */

#define		BASEC_RSVD		0xFFFFFFFC
#define 	BASEC_MASK		0x03
#define 	BASEC_START		0x58

#define PCIC_MBAR_KEY	0x7C	/* internal use only */

#define 	MBAR_KEY_MASK		0xFFFFFFFF

#define PCIC_HSTPCIX_CNTRL	0xA0