aic94xx_reg_def.h

linux 内核源代码

#define SCRATCHPAGESV	0x26

#define MnSCRATCHPAGESV	0x27

#define MnDMAERRS	0x46

#define MnSGDMAERRS	0x47

#define MnSGBUF		0x53

#define MnSGDMASTAT	0x5b

#define MnDDMACTL	0x5c	/* RAZOR.rspec.fm rev 1.5 is wrong */

#define MnDDMASTAT	0x5d	/* RAZOR.rspec.fm rev 1.5 is wrong */

#define MnDDMAMODE	0x5e	/* RAZOR.rspec.fm rev 1.5 is wrong */

#define MnDMAENG	0x60

#define MnPIPECTL	0x61

#define MnSGBADR	0x65

#define MnSCB_SITE	0x100

#define MnDDB_SITE	0x180

/*
 * The common definitions below have the same address offset for both
 * CSEQ and LmSEQ.
 */
#define BISTCTL0	0x4C

#define BISTCTL1	0x50

#define MAPPEDSCR	0x800

/*
 * CSEQ Host Register, Address Range : (0x000-0xFFC)
 */
#define CSEQ_HOST_REG_BASE_ADR		0xB8001000

#define CARP2CTL			(CSEQ_HOST_REG_BASE_ADR	+ ARP2CTL)

#define CARP2INT			(CSEQ_HOST_REG_BASE_ADR	+ ARP2INT)

#define CARP2INTEN			(CSEQ_HOST_REG_BASE_ADR	+ ARP2INTEN)

#define CARP2BREAKADR01			(CSEQ_HOST_REG_BASE_ADR+ARP2BREAKADR01)

#define CARP2BREAKADR23			(CSEQ_HOST_REG_BASE_ADR+ARP2BREAKADR23)

#define CBISTCTL			(CSEQ_HOST_REG_BASE_ADR	+ BISTCTL1)

#define		CSEQRAMBISTEN		0x00000040
#define		CSEQRAMBISTDN		0x00000020	/* ro */
#define		CSEQRAMBISTFAIL		0x00000010	/* ro */
#define		CSEQSCRBISTEN		0x00000004
#define		CSEQSCRBISTDN		0x00000002	/* ro */
#define		CSEQSCRBISTFAIL		0x00000001	/* ro */

#define CMAPPEDSCR			(CSEQ_HOST_REG_BASE_ADR	+ MAPPEDSCR)

/*
 * CSEQ CIO Bus Registers, Address Range : (0x0000-0x1FFC)
 * 16 modes, each mode is 512 bytes.
 * Unless specified, the register should valid for all modes.
 */
#define CSEQ_CIO_REG_BASE_ADR		REG_BASE_ADDR_CSEQCIO

#define CSEQm_CIO_REG(Mode, Reg) \
		(CSEQ_CIO_REG_BASE_ADR  + \
		((u32) (Mode) * CSEQ_MODE_PAGE_SIZE) + (u32) (Reg))

#define CMODEPTR	(CSEQ_CIO_REG_BASE_ADR + MODEPTR)

#define CALTMODE	(CSEQ_CIO_REG_BASE_ADR + ALTMODE)

#define CATOMICXCHG	(CSEQ_CIO_REG_BASE_ADR + ATOMICXCHG)

#define CFLAG		(CSEQ_CIO_REG_BASE_ADR + FLAG)

#define CARP2INTCTL	(CSEQ_CIO_REG_BASE_ADR + ARP2INTCTL)

#define CSTACK		(CSEQ_CIO_REG_BASE_ADR + STACK)

#define CFUNCTION1	(CSEQ_CIO_REG_BASE_ADR + FUNCTION1)

#define CPRGMCNT	(CSEQ_CIO_REG_BASE_ADR + PRGMCNT)

#define CACCUM		(CSEQ_CIO_REG_BASE_ADR + ACCUM)

#define CSINDEX		(CSEQ_CIO_REG_BASE_ADR + SINDEX)

#define CDINDEX		(CSEQ_CIO_REG_BASE_ADR + DINDEX)

#define CALLONES	(CSEQ_CIO_REG_BASE_ADR + ALLONES)

#define CALLZEROS	(CSEQ_CIO_REG_BASE_ADR + ALLZEROS)

#define CSINDIR		(CSEQ_CIO_REG_BASE_ADR + SINDIR)

#define CDINDIR		(CSEQ_CIO_REG_BASE_ADR + DINDIR)

#define CJUMLDIR	(CSEQ_CIO_REG_BASE_ADR + JUMLDIR)

#define CARP2HALTCODE	(CSEQ_CIO_REG_BASE_ADR + ARP2HALTCODE)

#define CCURRADDR	(CSEQ_CIO_REG_BASE_ADR + CURRADDR)

#define CLASTADDR	(CSEQ_CIO_REG_BASE_ADR + LASTADDR)

#define CNXTLADDR	(CSEQ_CIO_REG_BASE_ADR + NXTLADDR)

#define CDBGPORTPTR	(CSEQ_CIO_REG_BASE_ADR + DBGPORTPTR)

#define CDBGPORT	(CSEQ_CIO_REG_BASE_ADR + DBGPORT)

#define CSCRATCHPAGE	(CSEQ_CIO_REG_BASE_ADR + SCRATCHPAGE)

#define CMnSCBPTR(Mode)       CSEQm_CIO_REG(Mode, MnSCBPTR)

#define CMnDDBPTR(Mode)       CSEQm_CIO_REG(Mode, MnDDBPTR)

#define CMnSCRATCHPAGE(Mode)		CSEQm_CIO_REG(Mode, MnSCRATCHPAGE)

#define CLINKCON	(CSEQ_CIO_REG_BASE_ADR + 0x28)

#define	CCIOAACESS	(CSEQ_CIO_REG_BASE_ADR + 0x2C)

/* mode 0-7 */
#define MnREQMBX 0x30
#define CMnREQMBX(Mode)			CSEQm_CIO_REG(Mode, 0x30)

/* mode 8 */
#define CSEQCON				CSEQm_CIO_REG(8, 0x30)

/* mode 0-7 */
#define MnRSPMBX 0x34
#define CMnRSPMBX(Mode)			CSEQm_CIO_REG(Mode, 0x34)

/* mode 8 */
#define CSEQCOMCTL			CSEQm_CIO_REG(8, 0x34)

/* mode 8 */
#define CSEQCOMSTAT			CSEQm_CIO_REG(8, 0x35)

/* mode 8 */
#define CSEQCOMINTEN			CSEQm_CIO_REG(8, 0x36)

/* mode 8 */
#define CSEQCOMDMACTL			CSEQm_CIO_REG(8, 0x37)

#define		CSHALTERR		0x10
#define		RESETCSDMA		0x08		/* wo */
#define		STARTCSDMA		0x04
#define		STOPCSDMA		0x02		/* wo */
#define		CSDMAACT		0x01		/* ro */

/* mode 0-7 */
#define MnINT 0x38
#define CMnINT(Mode)			CSEQm_CIO_REG(Mode, 0x38)

#define		CMnREQMBXE		0x02
#define		CMnRSPMBXF		0x01
#define		CMnINT_MASK		0x00000003

/* mode 8 */
#define CSEQREQMBX			CSEQm_CIO_REG(8, 0x38)

/* mode 0-7 */
#define MnINTEN 0x3C
#define CMnINTEN(Mode)			CSEQm_CIO_REG(Mode, 0x3C)

#define		EN_CMnRSPMBXF		0x01

/* mode 8 */
#define CSEQRSPMBX			CSEQm_CIO_REG(8, 0x3C)

/* mode 8 */
#define CSDMAADR			CSEQm_CIO_REG(8, 0x40)

/* mode 8 */
#define CSDMACNT			CSEQm_CIO_REG(8, 0x48)

/* mode 8 */
#define CSEQDLCTL			CSEQm_CIO_REG(8, 0x4D)

#define		DONELISTEND		0x10
#define 	DONELISTSIZE_MASK	0x0F
#define		DONELISTSIZE_8ELEM	0x01
#define		DONELISTSIZE_16ELEM	0x02
#define		DONELISTSIZE_32ELEM	0x03
#define		DONELISTSIZE_64ELEM	0x04
#define		DONELISTSIZE_128ELEM	0x05
#define		DONELISTSIZE_256ELEM	0x06
#define		DONELISTSIZE_512ELEM	0x07
#define		DONELISTSIZE_1024ELEM	0x08
#define		DONELISTSIZE_2048ELEM	0x09
#define		DONELISTSIZE_4096ELEM	0x0A
#define		DONELISTSIZE_8192ELEM	0x0B
#define		DONELISTSIZE_16384ELEM	0x0C

/* mode 8 */
#define CSEQDLOFFS			CSEQm_CIO_REG(8, 0x4E)

/* mode 11 */
#define CM11INTVEC0			CSEQm_CIO_REG(11, 0x50)

/* mode 11 */
#define CM11INTVEC1			CSEQm_CIO_REG(11, 0x52)

/* mode 11 */
#define CM11INTVEC2			CSEQm_CIO_REG(11, 0x54)

#define	CCONMSK	  			(CSEQ_CIO_REG_BASE_ADR + 0x60)

#define	CCONEXIST			(CSEQ_CIO_REG_BASE_ADR + 0x61)

#define	CCONMODE			(CSEQ_CIO_REG_BASE_ADR + 0x62)

#define CTIMERCALC			(CSEQ_CIO_REG_BASE_ADR + 0x64)

#define CINTDIS				(CSEQ_CIO_REG_BASE_ADR + 0x68)

/* mode 8, 32x32 bits, 128 bytes of mapped buffer */
#define CSBUFFER			CSEQm_CIO_REG(8, 0x80)

#define	CSCRATCH			(CSEQ_CIO_REG_BASE_ADR + 0x1C0)

/* mode 0-8 */
#define CMnSCRATCH(Mode)		CSEQm_CIO_REG(Mode, 0x1E0)

/*
 * CSEQ Mapped Instruction RAM Page, Address Range : (0x0000-0x1FFC)
 */
#define CSEQ_RAM_REG_BASE_ADR		0xB8004000

/*
 * The common definitions below have the same address offset for all the Link
 * sequencers.
 */
#define MODECTL		0x40

#define DBGMODE		0x44

#define CONTROL		0x48
#define LEDTIMER		0x00010000
#define LEDTIMERS_10us		0x00000000
#define LEDTIMERS_1ms		0x00000800
#define LEDTIMERS_100ms		0x00001000
#define LEDMODE_TXRX		0x00000000
#define LEDMODE_CONNECTED	0x00000200
#define LEDPOL			0x00000100

#define LSEQRAM		0x1000

/*
 * LmSEQ Host Registers, Address Range : (0x0000-0x3FFC)
 */
#define LSEQ0_HOST_REG_BASE_ADR		0xB8020000
#define LSEQ1_HOST_REG_BASE_ADR		0xB8024000
#define LSEQ2_HOST_REG_BASE_ADR		0xB8028000
#define LSEQ3_HOST_REG_BASE_ADR		0xB802C000
#define LSEQ4_HOST_REG_BASE_ADR		0xB8030000
#define LSEQ5_HOST_REG_BASE_ADR		0xB8034000
#define LSEQ6_HOST_REG_BASE_ADR		0xB8038000
#define LSEQ7_HOST_REG_BASE_ADR		0xB803C000

#define LmARP2CTL(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	  \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
					ARP2CTL)

#define LmARP2INT(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	  \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
					ARP2INT)

#define LmARP2INTEN(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	  \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
					ARP2INTEN)

#define LmDBGMODE(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	  \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
					DBGMODE)

#define LmCONTROL(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	  \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
					CONTROL)

#define LmARP2BREAKADR01(LinkNum)	(LSEQ0_HOST_REG_BASE_ADR +	  \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
					ARP2BREAKADR01)

#define LmARP2BREAKADR23(LinkNum)	(LSEQ0_HOST_REG_BASE_ADR +	  \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
					ARP2BREAKADR23)

#define LmMODECTL(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	  \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
					MODECTL)

#define		LmAUTODISCI		0x08000000
#define		LmDSBLBITLT		0x04000000
#define		LmDSBLANTT		0x02000000
#define		LmDSBLCRTT		0x01000000
#define		LmDSBLCONT		0x00000100
#define		LmPRIMODE		0x00000080
#define		LmDSBLHOLD		0x00000040
#define		LmDISACK		0x00000020
#define		LmBLIND48		0x00000010
#define		LmRCVMODE_MASK		0x0000000C
#define		LmRCVMODE_PLD		0x00000000
#define		LmRCVMODE_HPC		0x00000004

#define LmDBGMODE(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	  \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
					DBGMODE)

#define		LmFRCPERR		0x80000000
#define		LmMEMSEL_MASK		0x30000000
#define		LmFRCRBPERR		0x00000000
#define		LmFRCTBPERR		0x10000000
#define		LmFRCSGBPERR		0x20000000
#define		LmFRCARBPERR		0x30000000
#define		LmRCVIDW		0x00080000
#define		LmINVDWERR		0x00040000
#define		LmRCVDISP		0x00004000
#define		LmDISPERR		0x00002000
#define		LmDSBLDSCR		0x00000800
#define		LmDSBLSCR		0x00000400
#define		LmFRCNAK		0x00000200
#define		LmFRCROFS		0x00000100
#define		LmFRCCRC		0x00000080
#define		LmFRMTYPE_MASK		0x00000070
#define		LmSG_DATA		0x00000000
#define		LmSG_COMMAND		0x00000010
#define		LmSG_TASK		0x00000020
#define		LmSG_TGTXFER		0x00000030
#define		LmSG_RESPONSE		0x00000040
#define		LmSG_IDENADDR		0x00000050
#define		LmSG_OPENADDR		0x00000060
#define		LmDISCRCGEN		0x00000008
#define		LmDISCRCCHK		0x00000004
#define		LmSSXMTFRM		0x00000002
#define		LmSSRCVFRM		0x00000001

#define LmCONTROL(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	  \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
					CONTROL)

#define		LmSTEPXMTFRM		0x00000002
#define		LmSTEPRCVFRM		0x00000001

#define LmBISTCTL0(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	  \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
					BISTCTL0)

#define		ARBBISTEN		0x40000000
#define		ARBBISTDN		0x20000000	/* ro */
#define		ARBBISTFAIL		0x10000000	/* ro */
#define		TBBISTEN		0x00000400
#define		TBBISTDN		0x00000200	/* ro */
#define		TBBISTFAIL		0x00000100	/* ro */
#define		RBBISTEN		0x00000040
#define		RBBISTDN		0x00000020	/* ro */
#define		RBBISTFAIL		0x00000010	/* ro */
#define		SGBISTEN		0x00000004
#define		SGBISTDN		0x00000002	/* ro */
#define		SGBISTFAIL		0x00000001	/* ro */

#define LmBISTCTL1(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	 \
					((LinkNum)*LmSEQ_HOST_REG_SIZE) +\
					BISTCTL1)

#define		LmRAMPAGE1		0x00000200
#define		LmRAMPAGE0		0x00000100
#define		LmIMEMBISTEN		0x00000040
#define		LmIMEMBISTDN		0x00000020	/* ro */
#define		LmIMEMBISTFAIL		0x00000010	/* ro */
#define		LmSCRBISTEN		0x00000004
#define		LmSCRBISTDN		0x00000002	/* ro */
#define		LmSCRBISTFAIL		0x00000001	/* ro */
#define		LmRAMPAGE		(LmRAMPAGE1 + LmRAMPAGE0)
#define		LmRAMPAGE_LSHIFT	0x8

#define LmSCRATCH(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	   \
					((LinkNum) * LmSEQ_HOST_REG_SIZE) +\
					MAPPEDSCR)

#define LmSEQRAM(LinkNum)		(LSEQ0_HOST_REG_BASE_ADR +	   \
					((LinkNum) * LmSEQ_HOST_REG_SIZE) +\
					LSEQRAM)

/*
 * LmSEQ CIO Bus Register, Address Range : (0x0000-0xFFC)
 * 8 modes, each mode is 512 bytes.
 * Unless specified, the register should valid for all modes.
 */
#define LmSEQ_CIOBUS_REG_BASE		0x2000

#define  LmSEQ_PHY_BASE(Mode, LinkNum) \
		(LSEQ0_HOST_REG_BASE_ADR + \
		(LmSEQ_HOST_REG_SIZE * (u32) (LinkNum)) + \
		LmSEQ_CIOBUS_REG_BASE + \
		((u32) (Mode) * LmSEQ_MODE_PAGE_SIZE))

#define  LmSEQ_PHY_REG(Mode, LinkNum, Reg) \
                 (LmSEQ_PHY_BASE(Mode, LinkNum) + (u32) (Reg))

#define LmMODEPTR(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, MODEPTR)

#define LmALTMODE(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, ALTMODE)

#define LmATOMICXCHG(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, ATOMICXCHG)

#define LmFLAG(LinkNum)			LmSEQ_PHY_REG(0, LinkNum, FLAG)

#define LmARP2INTCTL(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, ARP2INTCTL)

#define LmSTACK(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, STACK)

#define LmFUNCTION1(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, FUNCTION1)

#define LmPRGMCNT(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, PRGMCNT)

#define LmACCUM(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, ACCUM)

#define LmSINDEX(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, SINDEX)

#define LmDINDEX(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, DINDEX)

#define LmALLONES(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, ALLONES)

#define LmALLZEROS(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, ALLZEROS)

#define LmSINDIR(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, SINDIR)

#define LmDINDIR(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, DINDIR)

#define LmJUMLDIR(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, JUMLDIR)

#define LmARP2HALTCODE(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, ARP2HALTCODE)

#define LmCURRADDR(LinkNum)		LmSEQ_PHY_REG(0, LinkNum, CURRADDR)