aic94xx_reg_def.h

linux 内核源代码

/*
 * Aic94xx SAS/SATA driver hardware registers defintions.
 *
 * Copyright (C) 2004 Adaptec, Inc.  All rights reserved.
 * Copyright (C) 2004 David Chaw <[e-mail]>
 * Copyright (C) 2005 Luben Tuikov <[e-mail]>
 *
 * Luben Tuikov: Some register value updates to make it work with the window
 * agnostic register r/w functions.  Some register corrections, sizes,
 * etc.
 *
 * This file is licensed under GPLv2.
 *
 * This file is part of the aic94xx driver.
 *
 * The aic94xx driver is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; version 2 of the
 * License.
 *
 * The aic94xx driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with the aic94xx driver; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 *
 * $Id: //depot/aic94xx/aic94xx_reg_def.h#27 $
 *
 */

#ifndef _ADP94XX_REG_DEF_H_
#define _ADP94XX_REG_DEF_H_

/*
 * Common definitions.
 */
#define CSEQ_MODE_PAGE_SIZE	0x200		/* CSEQ mode page size */
#define LmSEQ_MODE_PAGE_SIZE	0x200		/* LmSEQ mode page size */
#define LmSEQ_HOST_REG_SIZE   	0x4000		/* LmSEQ Host Register size */

/********************* COM_SAS registers definition *************************/

/* The base is REG_BASE_ADDR, defined in aic94xx_reg.h.
 */

/*
 * CHIM Registers, Address Range : (0x00-0xFF)
 */
#define COMBIST		(REG_BASE_ADDR + 0x00)

/* bits 31:24 */
#define		L7BLKRST		0x80000000
#define		L6BLKRST		0x40000000
#define		L5BLKRST		0x20000000
#define		L4BLKRST		0x10000000
#define		L3BLKRST		0x08000000
#define		L2BLKRST		0x04000000
#define		L1BLKRST		0x02000000
#define		L0BLKRST		0x01000000
#define		LmBLKRST		0xFF000000
#define LmBLKRST_COMBIST(phyid)		(1 << (24 + phyid))

#define		OCMBLKRST		0x00400000
#define		CTXMEMBLKRST		0x00200000
#define		CSEQBLKRST		0x00100000
#define		EXSIBLKRST		0x00040000
#define		DPIBLKRST		0x00020000
#define		DFIFBLKRST		0x00010000
#define		HARDRST			0x00000200
#define		COMBLKRST		0x00000100
#define		FRCDFPERR		0x00000080
#define		FRCCIOPERR		0x00000020
#define		FRCBISTERR		0x00000010
#define		COMBISTEN		0x00000004
#define		COMBISTDONE		0x00000002	/* ro */
#define 	COMBISTFAIL		0x00000001	/* ro */

#define COMSTAT		(REG_BASE_ADDR + 0x04)

#define		REQMBXREAD		0x00000040
#define 	RSPMBXAVAIL		0x00000020
#define 	CSBUFPERR		0x00000008
#define		OVLYERR			0x00000004
#define 	CSERR			0x00000002
#define		OVLYDMADONE		0x00000001

#define		COMSTAT_MASK		(REQMBXREAD | RSPMBXAVAIL | \
					 CSBUFPERR | OVLYERR | CSERR |\
					 OVLYDMADONE)

#define COMSTATEN	(REG_BASE_ADDR + 0x08)

#define		EN_REQMBXREAD		0x00000040
#define		EN_RSPMBXAVAIL		0x00000020
#define		EN_CSBUFPERR		0x00000008
#define		EN_OVLYERR		0x00000004
#define		EN_CSERR		0x00000002
#define		EN_OVLYDONE		0x00000001

#define SCBPRO		(REG_BASE_ADDR + 0x0C)

#define		SCBCONS_MASK		0xFFFF0000
#define		SCBPRO_MASK		0x0000FFFF

#define CHIMREQMBX	(REG_BASE_ADDR + 0x10)

#define CHIMRSPMBX	(REG_BASE_ADDR + 0x14)

#define CHIMINT		(REG_BASE_ADDR + 0x18)

#define		EXT_INT0		0x00000800
#define		EXT_INT1		0x00000400
#define		PORRSTDET		0x00000200
#define		HARDRSTDET		0x00000100
#define		DLAVAILQ		0x00000080	/* ro */
#define		HOSTERR			0x00000040
#define		INITERR			0x00000020
#define		DEVINT			0x00000010
#define		COMINT			0x00000008
#define		DEVTIMER2		0x00000004
#define		DEVTIMER1		0x00000002
#define		DLAVAIL			0x00000001

#define		CHIMINT_MASK		(HOSTERR | INITERR | DEVINT | COMINT |\
					 DEVTIMER2 | DEVTIMER1 | DLAVAIL)

#define 	DEVEXCEPT_MASK		(HOSTERR | INITERR | DEVINT | COMINT)

#define CHIMINTEN	(REG_BASE_ADDR + 0x1C)

#define		RST_EN_EXT_INT1		0x01000000
#define		RST_EN_EXT_INT0		0x00800000
#define		RST_EN_HOSTERR		0x00400000
#define		RST_EN_INITERR		0x00200000
#define		RST_EN_DEVINT		0x00100000
#define		RST_EN_COMINT		0x00080000
#define		RST_EN_DEVTIMER2	0x00040000
#define		RST_EN_DEVTIMER1	0x00020000
#define		RST_EN_DLAVAIL		0x00010000
#define		SET_EN_EXT_INT1		0x00000100
#define		SET_EN_EXT_INT0		0x00000080
#define		SET_EN_HOSTERR		0x00000040
#define		SET_EN_INITERR		0x00000020
#define		SET_EN_DEVINT		0x00000010
#define		SET_EN_COMINT		0x00000008
#define		SET_EN_DEVTIMER2	0x00000004
#define		SET_EN_DEVTIMER1	0x00000002
#define		SET_EN_DLAVAIL		0x00000001

#define		RST_CHIMINTEN		(RST_EN_HOSTERR | RST_EN_INITERR | \
					 RST_EN_DEVINT | RST_EN_COMINT | \
					 RST_EN_DEVTIMER2 | RST_EN_DEVTIMER1 |\
					 RST_EN_DLAVAIL)

#define		SET_CHIMINTEN		(SET_EN_HOSTERR | SET_EN_INITERR |\
					 SET_EN_DEVINT | SET_EN_COMINT |\
					 SET_EN_DLAVAIL)

#define OVLYDMACTL	(REG_BASE_ADDR + 0x20)

#define		OVLYADR_MASK		0x07FF0000
#define		OVLYLSEQ_MASK		0x0000FF00
#define		OVLYCSEQ		0x00000080
#define		OVLYHALTERR		0x00000040
#define		PIOCMODE		0x00000020
#define		RESETOVLYDMA		0x00000008	/* wo */
#define		STARTOVLYDMA		0x00000004
#define		STOPOVLYDMA		0x00000002	/* wo */
#define		OVLYDMAACT		0x00000001	/* ro */

#define OVLYDMACNT	(REG_BASE_ADDR + 0x24)

#define		OVLYDOMAIN1		0x20000000	/* ro */
#define		OVLYDOMAIN0		0x10000000
#define		OVLYBUFADR_MASK		0x007F0000
#define		OVLYDMACNT_MASK		0x00003FFF

#define OVLYDMAADR	(REG_BASE_ADDR + 0x28)

#define DMAERR		(REG_BASE_ADDR + 0x30)

#define		OVLYERRSTAT_MASK	0x0000FF00	/* ro */
#define		CSERRSTAT_MASK		0x000000FF	/* ro */

#define SPIODATA	(REG_BASE_ADDR + 0x34)

/* 0x38 - 0x3C are reserved  */

#define T1CNTRLR	(REG_BASE_ADDR + 0x40)

#define		T1DONE			0x00010000	/* ro */
#define		TIMER64			0x00000400
#define		T1ENABLE		0x00000200
#define		T1RELOAD		0x00000100
#define		T1PRESCALER_MASK	0x00000003

#define	T1CMPR		(REG_BASE_ADDR + 0x44)

#define T1CNTR		(REG_BASE_ADDR + 0x48)

#define T2CNTRLR	(REG_BASE_ADDR + 0x4C)

#define		T2DONE			0x00010000	/* ro */
#define		T2ENABLE		0x00000200
#define		T2RELOAD		0x00000100
#define		T2PRESCALER_MASK	0x00000003

#define	T2CMPR		(REG_BASE_ADDR + 0x50)

#define T2CNTR		(REG_BASE_ADDR + 0x54)

/* 0x58h - 0xFCh are reserved */

/*
 * DCH_SAS Registers, Address Range : (0x800-0xFFF)
 */
#define CMDCTXBASE	(REG_BASE_ADDR + 0x800)

#define DEVCTXBASE	(REG_BASE_ADDR + 0x808)

#define CTXDOMAIN	(REG_BASE_ADDR + 0x810)

#define		DEVCTXDOMAIN1		0x00000008	/* ro */
#define		DEVCTXDOMAIN0		0x00000004
#define		CMDCTXDOMAIN1		0x00000002	/* ro */
#define		CMDCTXDOMAIN0		0x00000001

#define DCHCTL		(REG_BASE_ADDR + 0x814)

#define		OCMBISTREPAIR		0x00080000
#define		OCMBISTEN		0x00040000
#define		OCMBISTDN		0x00020000	/* ro */
#define		OCMBISTFAIL		0x00010000	/* ro */
#define		DDBBISTEN		0x00004000
#define		DDBBISTDN		0x00002000	/* ro */
#define		DDBBISTFAIL		0x00001000	/* ro */
#define		SCBBISTEN		0x00000400
#define		SCBBISTDN		0x00000200	/* ro */
#define		SCBBISTFAIL		0x00000100	/* ro */

#define		MEMSEL_MASK		0x000000E0
#define		MEMSEL_CCM_LSEQ		0x00000000
#define		MEMSEL_CCM_IOP		0x00000020
#define		MEMSEL_CCM_SASCTL	0x00000040
#define		MEMSEL_DCM_LSEQ		0x00000060
#define		MEMSEL_DCM_IOP		0x00000080
#define		MEMSEL_OCM		0x000000A0

#define		FRCERR			0x00000010
#define		AUTORLS			0x00000001

#define DCHREVISION	(REG_BASE_ADDR + 0x818)

#define		DCHREVISION_MASK	0x000000FF

#define DCHSTATUS	(REG_BASE_ADDR + 0x81C)

#define		EN_CFIFTOERR		0x00020000
#define		CFIFTOERR		0x00000200
#define		CSEQINT			0x00000100	/* ro */
#define		LSEQ7INT		0x00000080	/* ro */
#define		LSEQ6INT		0x00000040	/* ro */
#define		LSEQ5INT		0x00000020	/* ro */
#define		LSEQ4INT		0x00000010	/* ro */
#define		LSEQ3INT		0x00000008	/* ro */
#define		LSEQ2INT		0x00000004	/* ro */
#define		LSEQ1INT		0x00000002	/* ro */
#define		LSEQ0INT		0x00000001	/* ro */

#define		LSEQINT_MASK		(LSEQ7INT | LSEQ6INT | LSEQ5INT |\
					 LSEQ4INT | LSEQ3INT | LSEQ2INT	|\
					 LSEQ1INT | LSEQ0INT)

#define DCHDFIFDEBUG	(REG_BASE_ADDR + 0x820)
#define		ENFAIRMST		0x00FF0000
#define		DISWRMST9		0x00000200
#define		DISWRMST8		0x00000100
#define		DISRDMST		0x000000FF

#define ATOMICSTATCTL	(REG_BASE_ADDR + 0x824)
/* 8 bit wide */
#define		AUTOINC			0x80
#define		ATOMICERR		0x04
#define		ATOMICWIN		0x02
#define		ATOMICDONE		0x01


#define ALTCIOADR	(REG_BASE_ADDR + 0x828)
/* 16 bit; bits 8:0 define CIO addr space of CSEQ */

#define ASCBPTR		(REG_BASE_ADDR + 0x82C)
/* 16 bit wide */

#define ADDBPTR		(REG_BASE_ADDR + 0x82E)
/* 16 bit wide */

#define ANEWDATA	(REG_BASE_ADDR + 0x830)
/* 16 bit */

#define AOLDDATA	(REG_BASE_ADDR + 0x834)
/* 16 bit */

#define CTXACCESS	(REG_BASE_ADDR + 0x838)
/* 32 bit */

/* 0x83Ch - 0xFFCh are reserved */

/*
 * ARP2 External Processor Registers, Address Range : (0x00-0x1F)
 */
#define ARP2CTL		0x00

#define		FRCSCRPERR		0x00040000
#define		FRCARP2PERR		0x00020000
#define		FRCARP2ILLOPC		0x00010000
#define		ENWAITTO		0x00008000
#define		PERRORDIS		0x00004000
#define		FAILDIS			0x00002000
#define		CIOPERRDIS		0x00001000
#define		BREAKEN3		0x00000800
#define		BREAKEN2		0x00000400
#define		BREAKEN1		0x00000200
#define		BREAKEN0		0x00000100
#define		EPAUSE			0x00000008
#define		PAUSED			0x00000004	/* ro */
#define		STEP			0x00000002
#define		ARP2RESET		0x00000001	/* wo */

#define ARP2INT		0x04

#define		HALTCODE_MASK		0x00FF0000	/* ro */
#define		ARP2WAITTO		0x00000100
#define		ARP2HALTC		0x00000080
#define		ARP2ILLOPC		0x00000040
#define		ARP2PERR		0x00000020
#define		ARP2CIOPERR		0x00000010
#define		ARP2BREAK3		0x00000008
#define		ARP2BREAK2		0x00000004
#define		ARP2BREAK1		0x00000002
#define		ARP2BREAK0		0x00000001

#define ARP2INTEN	0x08

#define		EN_ARP2WAITTO		0x00000100
#define		EN_ARP2HALTC		0x00000080
#define		EN_ARP2ILLOPC		0x00000040
#define		EN_ARP2PERR		0x00000020
#define		EN_ARP2CIOPERR		0x00000010
#define		EN_ARP2BREAK3		0x00000008
#define		EN_ARP2BREAK2		0x00000004
#define		EN_ARP2BREAK1		0x00000002
#define		EN_ARP2BREAK0		0x00000001

#define ARP2BREAKADR01	0x0C

#define		BREAKADR1_MASK		0x0FFF0000
#define		BREAKADR0_MASK		0x00000FFF

#define	ARP2BREAKADR23	0x10

#define		BREAKADR3_MASK		0x0FFF0000
#define		BREAKADR2_MASK		0x00000FFF

/* 0x14h - 0x1Ch are reserved */

/*
 * ARP2 Registers, Address Range : (0x00-0x1F)
 * The definitions have the same address offset for CSEQ and LmSEQ
 * CIO Bus Registers.
 */
#define MODEPTR		0x00

#define		DSTMODE			0xF0
#define		SRCMODE			0x0F

#define ALTMODE		0x01

#define		ALTDMODE		0xF0
#define		ALTSMODE		0x0F

#define ATOMICXCHG	0x02

#define FLAG		0x04

#define		INTCODE_MASK		0xF0
#define		ALTMODEV2		0x04
#define		CARRY_INT		0x02
#define		CARRY			0x01

#define ARP2INTCTL	0x05

#define 	PAUSEDIS		0x80
#define		RSTINTCTL		0x40
#define		POPALTMODE		0x08
#define		ALTMODEV		0x04
#define		INTMASK			0x02
#define		IRET			0x01

#define STACK		0x06

#define FUNCTION1	0x07

#define PRGMCNT		0x08

#define ACCUM		0x0A

#define SINDEX		0x0C

#define DINDEX		0x0E

#define ALLONES		0x10

#define ALLZEROS	0x11

#define SINDIR		0x12

#define DINDIR		0x13

#define JUMLDIR		0x14

#define ARP2HALTCODE	0x15

#define CURRADDR	0x16

#define LASTADDR	0x18

#define NXTLADDR	0x1A

#define DBGPORTPTR	0x1C

#define DBGPORT		0x1D

/*
 * CIO Registers.
 * The definitions have the same address offset for CSEQ and LmSEQ
 * CIO Bus Registers.
 */
#define MnSCBPTR      	0x20

#define MnDDBPTR      	0x22

#define SCRATCHPAGE	0x24

#define MnSCRATCHPAGE	0x25