af9005.h

linux 内核源代码

/* Common header-file of the Linux driver for the Afatech 9005
 * USB1.1 DVB-T receiver.
 *
 * Copyright (C) 2007 Luca Olivetti ([e-mail])
 *
 * Thanks to Afatech who kindly provided information.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * see Documentation/dvb/README.dvb-usb for more information
 */
#ifndef _DVB_USB_AF9005_H_
#define _DVB_USB_AF9005_H_

#define DVB_USB_LOG_PREFIX "af9005"
#include "dvb-usb.h"

extern int dvb_usb_af9005_debug;
#define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args)
#define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args)
#define deb_rc(args...)   dprintk(dvb_usb_af9005_debug,0x04,args)
#define deb_reg(args...)  dprintk(dvb_usb_af9005_debug,0x08,args)
#define deb_i2c(args...)  dprintk(dvb_usb_af9005_debug,0x10,args)
#define deb_fw(args...)   dprintk(dvb_usb_af9005_debug,0x20,args)

extern int dvb_usb_af9005_led;

/* firmware */
#define FW_BULKOUT_SIZE 250
enum {
	FW_CONFIG,
	FW_CONFIRM,
	FW_BOOT
};

/* af9005 commands */
#define AF9005_OFDM_REG  0
#define AF9005_TUNER_REG 1

#define AF9005_REGISTER_RW     0x20
#define AF9005_REGISTER_RW_ACK 0x21

#define AF9005_CMD_OFDM_REG 0x00
#define AF9005_CMD_TUNER    0x80
#define AF9005_CMD_BURST    0x02
#define AF9005_CMD_AUTOINC  0x04
#define AF9005_CMD_READ     0x00
#define AF9005_CMD_WRITE    0x01

/* af9005 registers */
#define APO_REG_RESET					0xAEFF

#define APO_REG_I2C_RW_CAN_TUNER            0xF000
#define APO_REG_I2C_RW_SILICON_TUNER        0xF001
#define APO_REG_GPIO_RW_SILICON_TUNER       0xFFFE	/*  also for OFSM */
#define APO_REG_TRIGGER_OFSM                0xFFFF	/*  also for OFSM */

/***********************************************************************
 *  Apollo Registers from VLSI					       *
 ***********************************************************************/
#define xd_p_reg_aagc_inverted_agc	0xA000
#define	reg_aagc_inverted_agc_pos 0
#define	reg_aagc_inverted_agc_len 1
#define	reg_aagc_inverted_agc_lsb 0
#define xd_p_reg_aagc_sign_only	0xA000
#define	reg_aagc_sign_only_pos 1
#define	reg_aagc_sign_only_len 1
#define	reg_aagc_sign_only_lsb 0
#define xd_p_reg_aagc_slow_adc_en	0xA000
#define	reg_aagc_slow_adc_en_pos 2
#define	reg_aagc_slow_adc_en_len 1
#define	reg_aagc_slow_adc_en_lsb 0
#define xd_p_reg_aagc_slow_adc_scale	0xA000
#define	reg_aagc_slow_adc_scale_pos 3
#define	reg_aagc_slow_adc_scale_len 5
#define	reg_aagc_slow_adc_scale_lsb 0
#define xd_p_reg_aagc_check_slow_adc_lock	0xA001
#define	reg_aagc_check_slow_adc_lock_pos 0
#define	reg_aagc_check_slow_adc_lock_len 1
#define	reg_aagc_check_slow_adc_lock_lsb 0
#define xd_p_reg_aagc_init_control	0xA001
#define	reg_aagc_init_control_pos 1
#define	reg_aagc_init_control_len 1
#define	reg_aagc_init_control_lsb 0
#define xd_p_reg_aagc_total_gain_sel	0xA001
#define	reg_aagc_total_gain_sel_pos 2
#define	reg_aagc_total_gain_sel_len 2
#define	reg_aagc_total_gain_sel_lsb 0
#define xd_p_reg_aagc_out_inv	0xA001
#define	reg_aagc_out_inv_pos 5
#define	reg_aagc_out_inv_len 1
#define	reg_aagc_out_inv_lsb 0
#define xd_p_reg_aagc_int_en	0xA001
#define	reg_aagc_int_en_pos 6
#define	reg_aagc_int_en_len 1
#define	reg_aagc_int_en_lsb 0
#define xd_p_reg_aagc_lock_change_flag	0xA001
#define	reg_aagc_lock_change_flag_pos 7
#define	reg_aagc_lock_change_flag_len 1
#define	reg_aagc_lock_change_flag_lsb 0
#define xd_p_reg_aagc_rf_loop_bw_scale_acquire	0xA002
#define	reg_aagc_rf_loop_bw_scale_acquire_pos 0
#define	reg_aagc_rf_loop_bw_scale_acquire_len 5
#define	reg_aagc_rf_loop_bw_scale_acquire_lsb 0
#define xd_p_reg_aagc_rf_loop_bw_scale_track	0xA003
#define	reg_aagc_rf_loop_bw_scale_track_pos 0
#define	reg_aagc_rf_loop_bw_scale_track_len 5
#define	reg_aagc_rf_loop_bw_scale_track_lsb 0
#define xd_p_reg_aagc_if_loop_bw_scale_acquire	0xA004
#define	reg_aagc_if_loop_bw_scale_acquire_pos 0
#define	reg_aagc_if_loop_bw_scale_acquire_len 5
#define	reg_aagc_if_loop_bw_scale_acquire_lsb 0
#define xd_p_reg_aagc_if_loop_bw_scale_track	0xA005
#define	reg_aagc_if_loop_bw_scale_track_pos 0
#define	reg_aagc_if_loop_bw_scale_track_len 5
#define	reg_aagc_if_loop_bw_scale_track_lsb 0
#define xd_p_reg_aagc_max_rf_agc_7_0	0xA006
#define	reg_aagc_max_rf_agc_7_0_pos 0
#define	reg_aagc_max_rf_agc_7_0_len 8
#define	reg_aagc_max_rf_agc_7_0_lsb 0
#define xd_p_reg_aagc_max_rf_agc_9_8	0xA007
#define	reg_aagc_max_rf_agc_9_8_pos 0
#define	reg_aagc_max_rf_agc_9_8_len 2
#define	reg_aagc_max_rf_agc_9_8_lsb 8
#define xd_p_reg_aagc_min_rf_agc_7_0	0xA008
#define	reg_aagc_min_rf_agc_7_0_pos 0
#define	reg_aagc_min_rf_agc_7_0_len 8
#define	reg_aagc_min_rf_agc_7_0_lsb 0
#define xd_p_reg_aagc_min_rf_agc_9_8	0xA009
#define	reg_aagc_min_rf_agc_9_8_pos 0
#define	reg_aagc_min_rf_agc_9_8_len 2
#define	reg_aagc_min_rf_agc_9_8_lsb 8
#define xd_p_reg_aagc_max_if_agc_7_0	0xA00A
#define	reg_aagc_max_if_agc_7_0_pos 0
#define	reg_aagc_max_if_agc_7_0_len 8
#define	reg_aagc_max_if_agc_7_0_lsb 0
#define xd_p_reg_aagc_max_if_agc_9_8	0xA00B
#define	reg_aagc_max_if_agc_9_8_pos 0
#define	reg_aagc_max_if_agc_9_8_len 2
#define	reg_aagc_max_if_agc_9_8_lsb 8
#define xd_p_reg_aagc_min_if_agc_7_0	0xA00C
#define	reg_aagc_min_if_agc_7_0_pos 0
#define	reg_aagc_min_if_agc_7_0_len 8
#define	reg_aagc_min_if_agc_7_0_lsb 0
#define xd_p_reg_aagc_min_if_agc_9_8	0xA00D
#define	reg_aagc_min_if_agc_9_8_pos 0
#define	reg_aagc_min_if_agc_9_8_len 2
#define	reg_aagc_min_if_agc_9_8_lsb 8
#define xd_p_reg_aagc_lock_sample_scale	0xA00E
#define	reg_aagc_lock_sample_scale_pos 0
#define	reg_aagc_lock_sample_scale_len 5
#define	reg_aagc_lock_sample_scale_lsb 0
#define xd_p_reg_aagc_rf_agc_lock_scale_acquire	0xA00F
#define	reg_aagc_rf_agc_lock_scale_acquire_pos 0
#define	reg_aagc_rf_agc_lock_scale_acquire_len 3
#define	reg_aagc_rf_agc_lock_scale_acquire_lsb 0
#define xd_p_reg_aagc_rf_agc_lock_scale_track	0xA00F
#define	reg_aagc_rf_agc_lock_scale_track_pos 3
#define	reg_aagc_rf_agc_lock_scale_track_len 3
#define	reg_aagc_rf_agc_lock_scale_track_lsb 0
#define xd_p_reg_aagc_if_agc_lock_scale_acquire	0xA010
#define	reg_aagc_if_agc_lock_scale_acquire_pos 0
#define	reg_aagc_if_agc_lock_scale_acquire_len 3
#define	reg_aagc_if_agc_lock_scale_acquire_lsb 0
#define xd_p_reg_aagc_if_agc_lock_scale_track	0xA010
#define	reg_aagc_if_agc_lock_scale_track_pos 3
#define	reg_aagc_if_agc_lock_scale_track_len 3
#define	reg_aagc_if_agc_lock_scale_track_lsb 0
#define xd_p_reg_aagc_rf_top_numerator_7_0	0xA011
#define	reg_aagc_rf_top_numerator_7_0_pos 0
#define	reg_aagc_rf_top_numerator_7_0_len 8
#define	reg_aagc_rf_top_numerator_7_0_lsb 0
#define xd_p_reg_aagc_rf_top_numerator_9_8	0xA012
#define	reg_aagc_rf_top_numerator_9_8_pos 0
#define	reg_aagc_rf_top_numerator_9_8_len 2
#define	reg_aagc_rf_top_numerator_9_8_lsb 8
#define xd_p_reg_aagc_if_top_numerator_7_0	0xA013
#define	reg_aagc_if_top_numerator_7_0_pos 0
#define	reg_aagc_if_top_numerator_7_0_len 8
#define	reg_aagc_if_top_numerator_7_0_lsb 0
#define xd_p_reg_aagc_if_top_numerator_9_8	0xA014
#define	reg_aagc_if_top_numerator_9_8_pos 0
#define	reg_aagc_if_top_numerator_9_8_len 2
#define	reg_aagc_if_top_numerator_9_8_lsb 8
#define xd_p_reg_aagc_adc_out_desired_7_0	0xA015
#define	reg_aagc_adc_out_desired_7_0_pos 0
#define	reg_aagc_adc_out_desired_7_0_len 8
#define	reg_aagc_adc_out_desired_7_0_lsb 0
#define xd_p_reg_aagc_adc_out_desired_8	0xA016
#define	reg_aagc_adc_out_desired_8_pos 0
#define	reg_aagc_adc_out_desired_8_len 1
#define	reg_aagc_adc_out_desired_8_lsb 0
#define xd_p_reg_aagc_fixed_gain	0xA016
#define	reg_aagc_fixed_gain_pos 3
#define	reg_aagc_fixed_gain_len 1
#define	reg_aagc_fixed_gain_lsb 0
#define xd_p_reg_aagc_lock_count_th	0xA016
#define	reg_aagc_lock_count_th_pos 4
#define	reg_aagc_lock_count_th_len 4
#define	reg_aagc_lock_count_th_lsb 0
#define xd_p_reg_aagc_fixed_rf_agc_control_7_0	0xA017
#define	reg_aagc_fixed_rf_agc_control_7_0_pos 0
#define	reg_aagc_fixed_rf_agc_control_7_0_len 8
#define	reg_aagc_fixed_rf_agc_control_7_0_lsb 0
#define xd_p_reg_aagc_fixed_rf_agc_control_15_8	0xA018
#define	reg_aagc_fixed_rf_agc_control_15_8_pos 0
#define	reg_aagc_fixed_rf_agc_control_15_8_len 8
#define	reg_aagc_fixed_rf_agc_control_15_8_lsb 8
#define xd_p_reg_aagc_fixed_rf_agc_control_23_16	0xA019
#define	reg_aagc_fixed_rf_agc_control_23_16_pos 0
#define	reg_aagc_fixed_rf_agc_control_23_16_len 8
#define	reg_aagc_fixed_rf_agc_control_23_16_lsb 16
#define xd_p_reg_aagc_fixed_rf_agc_control_30_24	0xA01A
#define	reg_aagc_fixed_rf_agc_control_30_24_pos 0
#define	reg_aagc_fixed_rf_agc_control_30_24_len 7
#define	reg_aagc_fixed_rf_agc_control_30_24_lsb 24
#define xd_p_reg_aagc_fixed_if_agc_control_7_0	0xA01B
#define	reg_aagc_fixed_if_agc_control_7_0_pos 0
#define	reg_aagc_fixed_if_agc_control_7_0_len 8
#define	reg_aagc_fixed_if_agc_control_7_0_lsb 0
#define xd_p_reg_aagc_fixed_if_agc_control_15_8	0xA01C
#define	reg_aagc_fixed_if_agc_control_15_8_pos 0
#define	reg_aagc_fixed_if_agc_control_15_8_len 8
#define	reg_aagc_fixed_if_agc_control_15_8_lsb 8
#define xd_p_reg_aagc_fixed_if_agc_control_23_16	0xA01D
#define	reg_aagc_fixed_if_agc_control_23_16_pos 0
#define	reg_aagc_fixed_if_agc_control_23_16_len 8
#define	reg_aagc_fixed_if_agc_control_23_16_lsb 16
#define xd_p_reg_aagc_fixed_if_agc_control_30_24	0xA01E
#define	reg_aagc_fixed_if_agc_control_30_24_pos 0
#define	reg_aagc_fixed_if_agc_control_30_24_len 7
#define	reg_aagc_fixed_if_agc_control_30_24_lsb 24
#define xd_p_reg_aagc_rf_agc_unlock_numerator	0xA01F
#define	reg_aagc_rf_agc_unlock_numerator_pos 0
#define	reg_aagc_rf_agc_unlock_numerator_len 6
#define	reg_aagc_rf_agc_unlock_numerator_lsb 0
#define xd_p_reg_aagc_if_agc_unlock_numerator	0xA020
#define	reg_aagc_if_agc_unlock_numerator_pos 0
#define	reg_aagc_if_agc_unlock_numerator_len 6
#define	reg_aagc_if_agc_unlock_numerator_lsb 0
#define xd_p_reg_unplug_th	0xA021
#define	reg_unplug_th_pos 0
#define	reg_unplug_th_len 8
#define	reg_aagc_rf_x0_lsb 0
#define xd_p_reg_weak_signal_rfagc_thr 0xA022
#define	reg_weak_signal_rfagc_thr_pos 0
#define	reg_weak_signal_rfagc_thr_len 8
#define	reg_weak_signal_rfagc_thr_lsb 0
#define xd_p_reg_unplug_rf_gain_th 0xA023
#define	reg_unplug_rf_gain_th_pos 0
#define	reg_unplug_rf_gain_th_len 8
#define	reg_unplug_rf_gain_th_lsb 0
#define xd_p_reg_unplug_dtop_rf_gain_th 0xA024
#define	reg_unplug_dtop_rf_gain_th_pos 0
#define	reg_unplug_dtop_rf_gain_th_len 8
#define	reg_unplug_dtop_rf_gain_th_lsb 0
#define xd_p_reg_unplug_dtop_if_gain_th 0xA025
#define	reg_unplug_dtop_if_gain_th_pos 0
#define	reg_unplug_dtop_if_gain_th_len 8
#define	reg_unplug_dtop_if_gain_th_lsb 0
#define xd_p_reg_top_recover_at_unplug_en 0xA026
#define	reg_top_recover_at_unplug_en_pos 0
#define	reg_top_recover_at_unplug_en_len 1
#define	reg_top_recover_at_unplug_en_lsb 0
#define xd_p_reg_aagc_rf_x6	0xA027
#define	reg_aagc_rf_x6_pos 0
#define	reg_aagc_rf_x6_len 8
#define	reg_aagc_rf_x6_lsb 0
#define xd_p_reg_aagc_rf_x7	0xA028
#define	reg_aagc_rf_x7_pos 0
#define	reg_aagc_rf_x7_len 8
#define	reg_aagc_rf_x7_lsb 0
#define xd_p_reg_aagc_rf_x8	0xA029
#define	reg_aagc_rf_x8_pos 0
#define	reg_aagc_rf_x8_len 8
#define	reg_aagc_rf_x8_lsb 0
#define xd_p_reg_aagc_rf_x9	0xA02A
#define	reg_aagc_rf_x9_pos 0
#define	reg_aagc_rf_x9_len 8
#define	reg_aagc_rf_x9_lsb 0
#define xd_p_reg_aagc_rf_x10	0xA02B
#define	reg_aagc_rf_x10_pos 0
#define	reg_aagc_rf_x10_len 8
#define	reg_aagc_rf_x10_lsb 0
#define xd_p_reg_aagc_rf_x11	0xA02C
#define	reg_aagc_rf_x11_pos 0
#define	reg_aagc_rf_x11_len 8
#define	reg_aagc_rf_x11_lsb 0
#define xd_p_reg_aagc_rf_x12	0xA02D
#define	reg_aagc_rf_x12_pos 0
#define	reg_aagc_rf_x12_len 8
#define	reg_aagc_rf_x12_lsb 0
#define xd_p_reg_aagc_rf_x13	0xA02E
#define	reg_aagc_rf_x13_pos 0
#define	reg_aagc_rf_x13_len 8
#define	reg_aagc_rf_x13_lsb 0
#define xd_p_reg_aagc_if_x0	0xA02F
#define	reg_aagc_if_x0_pos 0
#define	reg_aagc_if_x0_len 8
#define	reg_aagc_if_x0_lsb 0
#define xd_p_reg_aagc_if_x1	0xA030
#define	reg_aagc_if_x1_pos 0
#define	reg_aagc_if_x1_len 8
#define	reg_aagc_if_x1_lsb 0
#define xd_p_reg_aagc_if_x2	0xA031
#define	reg_aagc_if_x2_pos 0
#define	reg_aagc_if_x2_len 8
#define	reg_aagc_if_x2_lsb 0
#define xd_p_reg_aagc_if_x3	0xA032
#define	reg_aagc_if_x3_pos 0
#define	reg_aagc_if_x3_len 8
#define	reg_aagc_if_x3_lsb 0
#define xd_p_reg_aagc_if_x4	0xA033
#define	reg_aagc_if_x4_pos 0
#define	reg_aagc_if_x4_len 8
#define	reg_aagc_if_x4_lsb 0
#define xd_p_reg_aagc_if_x5	0xA034
#define	reg_aagc_if_x5_pos 0
#define	reg_aagc_if_x5_len 8
#define	reg_aagc_if_x5_lsb 0
#define xd_p_reg_aagc_if_x6	0xA035
#define	reg_aagc_if_x6_pos 0
#define	reg_aagc_if_x6_len 8
#define	reg_aagc_if_x6_lsb 0
#define xd_p_reg_aagc_if_x7	0xA036
#define	reg_aagc_if_x7_pos 0
#define	reg_aagc_if_x7_len 8
#define	reg_aagc_if_x7_lsb 0
#define xd_p_reg_aagc_if_x8	0xA037
#define	reg_aagc_if_x8_pos 0
#define	reg_aagc_if_x8_len 8
#define	reg_aagc_if_x8_lsb 0
#define xd_p_reg_aagc_if_x9	0xA038
#define	reg_aagc_if_x9_pos 0
#define	reg_aagc_if_x9_len 8
#define	reg_aagc_if_x9_lsb 0
#define xd_p_reg_aagc_if_x10	0xA039
#define	reg_aagc_if_x10_pos 0
#define	reg_aagc_if_x10_len 8
#define	reg_aagc_if_x10_lsb 0
#define xd_p_reg_aagc_if_x11	0xA03A
#define	reg_aagc_if_x11_pos 0
#define	reg_aagc_if_x11_len 8
#define	reg_aagc_if_x11_lsb 0
#define xd_p_reg_aagc_if_x12	0xA03B
#define	reg_aagc_if_x12_pos 0
#define	reg_aagc_if_x12_len 8
#define	reg_aagc_if_x12_lsb 0
#define xd_p_reg_aagc_if_x13	0xA03C
#define	reg_aagc_if_x13_pos 0
#define	reg_aagc_if_x13_len 8
#define	reg_aagc_if_x13_lsb 0
#define xd_p_reg_aagc_min_rf_ctl_8bit_for_dca	0xA03D
#define	reg_aagc_min_rf_ctl_8bit_for_dca_pos 0
#define	reg_aagc_min_rf_ctl_8bit_for_dca_len 8
#define	reg_aagc_min_rf_ctl_8bit_for_dca_lsb 0
#define xd_p_reg_aagc_min_if_ctl_8bit_for_dca	0xA03E
#define	reg_aagc_min_if_ctl_8bit_for_dca_pos 0
#define	reg_aagc_min_if_ctl_8bit_for_dca_len 8
#define	reg_aagc_min_if_ctl_8bit_for_dca_lsb 0