kconfig

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config BFIN_SCRATCH_REG_RETE
	bool "RETE"
	help
	  Use the RETE register in the Blackfin exception handler
	  as a stack scratch register.  This means you cannot
	  safely use a JTAG ICE while debugging a Blackfin board,
	  but you can safely use the CYCLES performance registers
	  and the NMI.

	  If you are unsure, please select "RETN".

config BFIN_SCRATCH_REG_CYCLES
	bool "CYCLES"
	help
	  Use the CYCLES register in the Blackfin exception handler
	  as a stack scratch register.  This means you cannot
	  safely use the CYCLES performance registers on a Blackfin
	  board at anytime, but you can debug the system with a JTAG
	  ICE and use the NMI.

	  If you are unsure, please select "RETN".

endchoice

#
# Sorry - but you need to put the hex address here -
#

# Flag Data register
config BFIN_ALIVE_LED_PORT
	hex
	default 0xFFC00700 if (BFIN533_STAMP)

# Peripheral Flag Direction Register
config BFIN_ALIVE_LED_DPORT
	hex
	default 0xFFC00730 if (BFIN533_STAMP)

config BFIN_ALIVE_LED_PIN
	hex
	default 0x04 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 1)
	default 0x08 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 2)
	default 0x10 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 3)

config BFIN_IDLE_LED_PORT
	hex
	default 0xFFC00700 if (BFIN533_STAMP)

# Peripheral Flag Direction Register
config BFIN_IDLE_LED_DPORT
	hex
	default 0xFFC00730 if (BFIN533_STAMP)

config BFIN_IDLE_LED_PIN
	hex
	default 0x04 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 1)
	default 0x08 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 2)
	default 0x10 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 3)

endmenu


menu "Blackfin Kernel Optimizations"

comment "Memory Optimizations"

config I_ENTRY_L1
	bool "Locate interrupt entry code in L1 Memory"
	default y
	help
	  If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
	  into L1 instruction memory. (less latency)

config EXCPT_IRQ_SYSC_L1
	bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
	default y
	help
	  If enabled, the entire ASM lowlevel exception and interrupt entry code
	  (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. 
	  (less latency)

config DO_IRQ_L1
	bool "Locate frequently called do_irq dispatcher function in L1 Memory"
	default y
	help
	  If enabled, the frequently called do_irq dispatcher function is linked
	  into L1 instruction memory. (less latency)

config CORE_TIMER_IRQ_L1
	bool "Locate frequently called timer_interrupt() function in L1 Memory"
	default y
	help
	  If enabled, the frequently called timer_interrupt() function is linked
	  into L1 instruction memory. (less latency)

config IDLE_L1
	bool "Locate frequently idle function in L1 Memory"
	default y
	help
	  If enabled, the frequently called idle function is linked
	  into L1 instruction memory. (less latency)

config SCHEDULE_L1
	bool "Locate kernel schedule function in L1 Memory"
	default y
	help
	  If enabled, the frequently called kernel schedule is linked
	  into L1 instruction memory. (less latency)

config ARITHMETIC_OPS_L1
	bool "Locate kernel owned arithmetic functions in L1 Memory"
	default y
	help
	  If enabled, arithmetic functions are linked
	  into L1 instruction memory. (less latency)

config ACCESS_OK_L1
	bool "Locate access_ok function in L1 Memory"
	default y
	help
	  If enabled, the access_ok function is linked
	  into L1 instruction memory. (less latency)

config MEMSET_L1
	bool "Locate memset function in L1 Memory"
	default y
	help
	  If enabled, the memset function is linked
	  into L1 instruction memory. (less latency)

config MEMCPY_L1
	bool "Locate memcpy function in L1 Memory"
	default y
	help
	  If enabled, the memcpy function is linked
	  into L1 instruction memory. (less latency)

config SYS_BFIN_SPINLOCK_L1
	bool "Locate sys_bfin_spinlock function in L1 Memory"
	default y
	help
	  If enabled, sys_bfin_spinlock function is linked
	  into L1 instruction memory. (less latency)

config IP_CHECKSUM_L1
	bool "Locate IP Checksum function in L1 Memory"
	default n
	help
	  If enabled, the IP Checksum function is linked
	  into L1 instruction memory. (less latency)

config CACHELINE_ALIGNED_L1
	bool "Locate cacheline_aligned data to L1 Data Memory"
	default y if !BF54x
	default n if BF54x
	depends on !BF531
	help
	  If enabled, cacheline_anligned data is linked
	  into L1 data memory. (less latency)

config SYSCALL_TAB_L1
	bool "Locate Syscall Table L1 Data Memory"
	default n
	depends on !BF531
	help
	  If enabled, the Syscall LUT is linked
	  into L1 data memory. (less latency)

config CPLB_SWITCH_TAB_L1
	bool "Locate CPLB Switch Tables L1 Data Memory"
	default n
	depends on !BF531
	help
	  If enabled, the CPLB Switch Tables are linked
	  into L1 data memory. (less latency)

endmenu


choice
	prompt "Kernel executes from"
	help
	  Choose the memory type that the kernel will be running in.

config RAMKERNEL
	bool "RAM"
	help
	  The kernel will be resident in RAM when running.

config ROMKERNEL
	bool "ROM"
	help
	  The kernel will be resident in FLASH/ROM when running.

endchoice

source "mm/Kconfig"

config LARGE_ALLOCS
	bool "Allow allocating large blocks (> 1MB) of memory"
	help
	  Allow the slab memory allocator to keep chains for very large
	  memory sizes - upto 32MB. You may need this if your system has
	  a lot of RAM, and you need to able to allocate very large
	  contiguous chunks. If unsure, say N.

config BFIN_GPTIMERS
	tristate "Enable Blackfin General Purpose Timers API"
	default n
	help
	  Enable support for the General Purpose Timers API.  If you
	  are unsure, say N.

	  To compile this driver as a module, choose M here: the module
	  will be called gptimers.ko.

config BFIN_DMA_5XX
	bool "Enable DMA Support"
	depends on (BF52x || BF53x || BF561 || BF54x)
	default y
	help
	  DMA driver for BF5xx.

choice
	prompt "Uncached SDRAM region"
	default DMA_UNCACHED_1M
	depends on BFIN_DMA_5XX
config DMA_UNCACHED_2M
	bool "Enable 2M DMA region"
config DMA_UNCACHED_1M
	bool "Enable 1M DMA region"
config DMA_UNCACHED_NONE
	bool "Disable DMA region"
endchoice


comment "Cache Support"
config BFIN_ICACHE
	bool "Enable ICACHE"
config BFIN_DCACHE
	bool "Enable DCACHE"
config BFIN_DCACHE_BANKA
	bool "Enable only 16k BankA DCACHE - BankB is SRAM"
	depends on BFIN_DCACHE && !BF531
	default n
config BFIN_ICACHE_LOCK
	bool "Enable Instruction Cache Locking"

choice
	prompt "Policy"
	depends on BFIN_DCACHE
	default BFIN_WB
config BFIN_WB
	bool "Write back"
	help
	  Write Back Policy:
	    Cached data will be written back to SDRAM only when needed.
	    This can give a nice increase in performance, but beware of
	    broken drivers that do not properly invalidate/flush their
	    cache.

	  Write Through Policy:
	    Cached data will always be written back to SDRAM when the
	    cache is updated.  This is a completely safe setting, but
	    performance is worse than Write Back.

	  If you are unsure of the options and you want to be safe,
	  then go with Write Through.

config BFIN_WT
	bool "Write through"
	help
	  Write Back Policy:
	    Cached data will be written back to SDRAM only when needed.
	    This can give a nice increase in performance, but beware of
	    broken drivers that do not properly invalidate/flush their
	    cache.

	  Write Through Policy:
	    Cached data will always be written back to SDRAM when the
	    cache is updated.  This is a completely safe setting, but
	    performance is worse than Write Back.

	  If you are unsure of the options and you want to be safe,
	  then go with Write Through.

endchoice

config L1_MAX_PIECE
	int "Set the max L1 SRAM pieces"
	default 16
	help
	  Set the max memory pieces for the L1 SRAM allocation algorithm.
	  Min value is 16. Max value is 1024.

comment "Asynchonous Memory Configuration"

menu "EBIU_AMGCTL Global Control"
config C_AMCKEN
	bool "Enable CLKOUT"
	default y

config C_CDPRIO
	bool "DMA has priority over core for ext. accesses"
	depends on !BF54x
	default n

config C_B0PEN
	depends on BF561
	bool "Bank 0 16 bit packing enable"
	default y

config C_B1PEN
	depends on BF561
	bool "Bank 1 16 bit packing enable"
	default y

config C_B2PEN
	depends on BF561
	bool "Bank 2 16 bit packing enable"
	default y

config C_B3PEN
	depends on BF561
	bool "Bank 3 16 bit packing enable"
	default n

choice
	prompt"Enable Asynchonous Memory Banks"
	default C_AMBEN_ALL

config C_AMBEN
	bool "Disable All Banks"

config C_AMBEN_B0
	bool "Enable Bank 0"

config C_AMBEN_B0_B1
	bool "Enable Bank 0 & 1"

config C_AMBEN_B0_B1_B2
	bool "Enable Bank 0 & 1 & 2"

config C_AMBEN_ALL
	bool "Enable All Banks"
endchoice
endmenu

menu "EBIU_AMBCTL Control"
config BANK_0
	hex "Bank 0"
	default 0x7BB0

config BANK_1
	hex "Bank 1"
	default 0x7BB0

config BANK_2
	hex "Bank 2"
	default 0x7BB0

config BANK_3
	hex "Bank 3"
	default 0x99B3
endmenu

config EBIU_MBSCTLVAL
	hex "EBIU Bank Select Control Register"
	depends on BF54x
	default 0

config EBIU_MODEVAL
	hex "Flash Memory Mode Control Register"
	depends on BF54x
	default 1

config EBIU_FCTLVAL
	hex "Flash Memory Bank Control Register"
	depends on BF54x
	default 6
endmenu

#############################################################################
menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"

config PCI
	bool "PCI support"
	help
	  Support for PCI bus.

source "drivers/pci/Kconfig"

config HOTPLUG
	bool "Support for hot-pluggable device"
	  help
	  Say Y here if you want to plug devices into your computer while
	  the system is running, and be able to use them quickly.  In many
	  cases, the devices can likewise be unplugged at any time too.

	  One well known example of this is PCMCIA- or PC-cards, credit-card
	  size devices such as network cards, modems or hard drives which are
	  plugged into slots found on all modern laptop computers.  Another
	  example, used on modern desktops as well as laptops, is USB.

	  Enable HOTPLUG and KMOD, and build a modular kernel.  Get agent
	  software (at <http://linux-hotplug.sourceforge.net/>) and install it.
	  Then your kernel will automatically call out to a user mode "policy
	  agent" (/sbin/hotplug) to load modules and set up software needed
	  to use devices as you hotplug them.

source "drivers/pcmcia/Kconfig"

source "drivers/pci/hotplug/Kconfig"

endmenu

menu "Executable file formats"

source "fs/Kconfig.binfmt"

endmenu

menu "Power management options"
source "kernel/power/Kconfig"

choice
	prompt "Select PM Wakeup Event Source"
	default PM_WAKEUP_GPIO_BY_SIC_IWR
	depends on PM
	help
	  If you have a GPIO already configured as input with the corresponding PORTx_MASK
	  bit set - "Specify Wakeup Event by SIC_IWR value"

config PM_WAKEUP_GPIO_BY_SIC_IWR
	bool "Specify Wakeup Event by SIC_IWR value"
config PM_WAKEUP_BY_GPIO
	bool "Cause Wakeup Event by GPIO"
config PM_WAKEUP_GPIO_API
	bool "Configure Wakeup Event by PM GPIO API"

endchoice

config PM_WAKEUP_SIC_IWR
	hex "Wakeup Events (SIC_IWR)"
	depends on PM_WAKEUP_GPIO_BY_SIC_IWR
	default 0x80000000 if (BF537 || BF536 || BF534)
	default 0x100000 if (BF533 || BF532 || BF531)

config PM_WAKEUP_GPIO_NUMBER
	int "Wakeup GPIO number"
	range 0 47
	depends on PM_WAKEUP_BY_GPIO
	default 2 if BFIN537_STAMP

choice
	prompt "GPIO Polarity"
	depends on PM_WAKEUP_BY_GPIO
	default PM_WAKEUP_GPIO_POLAR_H
config  PM_WAKEUP_GPIO_POLAR_H
	bool "Active High"
config  PM_WAKEUP_GPIO_POLAR_L
	bool "Active Low"
config  PM_WAKEUP_GPIO_POLAR_EDGE_F
	bool "Falling EDGE"
config  PM_WAKEUP_GPIO_POLAR_EDGE_R
	bool "Rising EDGE"
config  PM_WAKEUP_GPIO_POLAR_EDGE_B
	bool "Both EDGE"
endchoice

endmenu

if (BF537 || BF533 || BF54x)

menu "CPU Frequency scaling"

source "drivers/cpufreq/Kconfig"

config CPU_FREQ
	bool
	default n
	help
	  If you want to enable this option, you should select the
	  DPMC driver from Character Devices.
endmenu

endif

source "net/Kconfig"

source "drivers/Kconfig"

source "fs/Kconfig"

source "kernel/Kconfig.instrumentation"

source "arch/blackfin/Kconfig.debug"

source "security/Kconfig"

source "crypto/Kconfig"

source "lib/Kconfig"