📄 prcm-regs.h

📁 linux 内核源代码
💻 H
📖 第 1 页 / 共 2 页
字号:
上一页 12
#if defined(CONFIG_ARCH_OMAP243X)#define GPIO5_SYSCONFIG		__REG32((OMAP24XX_GPIO5_BASE + 0x10))#endif/* GP TIMER 1 */#define GPTIMER1_TISTAT		GPT1_REG32(0x014)#define GPTIMER1_TISR		GPT1_REG32(0x018)#define GPTIMER1_TIER		GPT1_REG32(0x01C)#define GPTIMER1_TWER		GPT1_REG32(0x020)#define GPTIMER1_TCLR		GPT1_REG32(0x024)#define GPTIMER1_TCRR		GPT1_REG32(0x028)#define GPTIMER1_TLDR		GPT1_REG32(0x02C)#define GPTIMER1_TTGR		GPT1_REG32(0x030)#define GPTIMER1_TWPS		GPT1_REG32(0x034)#define GPTIMER1_TMAR		GPT1_REG32(0x038)#define GPTIMER1_TCAR1		GPT1_REG32(0x03C)#define GPTIMER1_TSICR		GPT1_REG32(0x040)#define GPTIMER1_TCAR2		GPT1_REG32(0x044)/* rkw -- base fix up please... */#define GPTIMER3_TISR		__REG32(OMAP24XX_L4_IO_BASE + 0x78018)/* SDRC */#define SDRC_DLLA_CTRL		__REG32(OMAP24XX_SDRC_BASE + 0x060)#define SDRC_DLLA_STATUS	__REG32(OMAP24XX_SDRC_BASE + 0x064)#define SDRC_DLLB_CTRL		__REG32(OMAP24XX_SDRC_BASE + 0x068)#define SDRC_DLLB_STATUS	__REG32(OMAP24XX_SDRC_BASE + 0x06C)#define SDRC_POWER		__REG32(OMAP24XX_SDRC_BASE + 0x070)#define SDRC_MR_0		__REG32(OMAP24XX_SDRC_BASE + 0x084)/* GPIO 1 */#define GPIO1_BASE		GPIOX_BASE(1)#define GPIO1_REG32(offset)	__REG32(GPIO1_BASE + (offset))#define GPIO1_IRQENABLE1	GPIO1_REG32(0x01C)#define GPIO1_IRQSTATUS1	GPIO1_REG32(0x018)#define GPIO1_IRQENABLE2	GPIO1_REG32(0x02C)#define GPIO1_IRQSTATUS2	GPIO1_REG32(0x028)#define GPIO1_WAKEUPENABLE	GPIO1_REG32(0x020)#define GPIO1_RISINGDETECT	GPIO1_REG32(0x048)#define GPIO1_DATAIN		GPIO1_REG32(0x038)#define GPIO1_OE		GPIO1_REG32(0x034)#define GPIO1_DATAOUT		GPIO1_REG32(0x03C)/* GPIO2 */#define GPIO2_BASE		GPIOX_BASE(2)#define GPIO2_REG32(offset)	__REG32(GPIO2_BASE + (offset))#define GPIO2_IRQENABLE1	GPIO2_REG32(0x01C)#define GPIO2_IRQSTATUS1	GPIO2_REG32(0x018)#define GPIO2_IRQENABLE2	GPIO2_REG32(0x02C)#define GPIO2_IRQSTATUS2	GPIO2_REG32(0x028)#define GPIO2_WAKEUPENABLE	GPIO2_REG32(0x020)#define GPIO2_RISINGDETECT	GPIO2_REG32(0x048)#define GPIO2_DATAIN		GPIO2_REG32(0x038)#define GPIO2_OE		GPIO2_REG32(0x034)#define GPIO2_DATAOUT		GPIO2_REG32(0x03C)#define GPIO2_DEBOUNCENABLE	GPIO2_REG32(0x050)#define GPIO2_DEBOUNCINGTIME	GPIO2_REG32(0x054)/* GPIO 3 */#define GPIO3_BASE		GPIOX_BASE(3)#define GPIO3_REG32(offset)	__REG32(GPIO3_BASE + (offset))#define GPIO3_IRQENABLE1	GPIO3_REG32(0x01C)#define GPIO3_IRQSTATUS1	GPIO3_REG32(0x018)#define GPIO3_IRQENABLE2	GPIO3_REG32(0x02C)#define GPIO3_IRQSTATUS2	GPIO3_REG32(0x028)#define GPIO3_WAKEUPENABLE	GPIO3_REG32(0x020)#define GPIO3_RISINGDETECT	GPIO3_REG32(0x048)#define GPIO3_FALLINGDETECT	GPIO3_REG32(0x04C)#define GPIO3_DATAIN		GPIO3_REG32(0x038)#define GPIO3_OE		GPIO3_REG32(0x034)#define GPIO3_DATAOUT		GPIO3_REG32(0x03C)#define GPIO3_DEBOUNCENABLE	GPIO3_REG32(0x050)#define GPIO3_DEBOUNCINGTIME	GPIO3_REG32(0x054)#define GPIO3_DEBOUNCENABLE	GPIO3_REG32(0x050)#define GPIO3_DEBOUNCINGTIME	GPIO3_REG32(0x054)/* GPIO 4 */#define GPIO4_BASE		GPIOX_BASE(4)#define GPIO4_REG32(offset)	__REG32(GPIO4_BASE + (offset))#define GPIO4_IRQENABLE1	GPIO4_REG32(0x01C)#define GPIO4_IRQSTATUS1	GPIO4_REG32(0x018)#define GPIO4_IRQENABLE2	GPIO4_REG32(0x02C)#define GPIO4_IRQSTATUS2	GPIO4_REG32(0x028)#define GPIO4_WAKEUPENABLE	GPIO4_REG32(0x020)#define GPIO4_RISINGDETECT	GPIO4_REG32(0x048)#define GPIO4_FALLINGDETECT	GPIO4_REG32(0x04C)#define GPIO4_DATAIN		GPIO4_REG32(0x038)#define GPIO4_OE		GPIO4_REG32(0x034)#define GPIO4_DATAOUT		GPIO4_REG32(0x03C)#define GPIO4_DEBOUNCENABLE	GPIO4_REG32(0x050)#define GPIO4_DEBOUNCINGTIME	GPIO4_REG32(0x054)#if defined(CONFIG_ARCH_OMAP243X)/* GPIO 5 */#define GPIO5_REG32(offset)	__REG32((OMAP24XX_GPIO5_BASE + (offset)))#define GPIO5_IRQENABLE1	GPIO5_REG32(0x01C)#define GPIO5_IRQSTATUS1	GPIO5_REG32(0x018)#define GPIO5_IRQENABLE2	GPIO5_REG32(0x02C)#define GPIO5_IRQSTATUS2	GPIO5_REG32(0x028)#define GPIO5_WAKEUPENABLE	GPIO5_REG32(0x020)#define GPIO5_RISINGDETECT	GPIO5_REG32(0x048)#define GPIO5_FALLINGDETECT	GPIO5_REG32(0x04C)#define GPIO5_DATAIN		GPIO5_REG32(0x038)#define GPIO5_OE		GPIO5_REG32(0x034)#define GPIO5_DATAOUT		GPIO5_REG32(0x03C)#define GPIO5_DEBOUNCENABLE	GPIO5_REG32(0x050)#define GPIO5_DEBOUNCINGTIME	GPIO5_REG32(0x054)#endif/* IO CONFIG */#define OMAP24XX_CTRL_BASE		(L4_24XX_BASE)#define CONTROL_REG32(offset)		__REG32(OMAP24XX_CTRL_BASE + (offset))#define CONTROL_PADCONF_SPI1_NCS2	CONTROL_REG32(0x104)#define CONTROL_PADCONF_SYS_XTALOUT	CONTROL_REG32(0x134)#define CONTROL_PADCONF_UART1_RX	CONTROL_REG32(0x0C8)#define CONTROL_PADCONF_MCBSP1_DX	CONTROL_REG32(0x10C)#define CONTROL_PADCONF_GPMC_NCS4	CONTROL_REG32(0x090)#define CONTROL_PADCONF_DSS_D5		CONTROL_REG32(0x0B8)#define CONTROL_PADCONF_DSS_D9		CONTROL_REG32(0x0BC)	/* 2420 */#define CONTROL_PADCONF_DSS_D13		CONTROL_REG32(0x0C0)#define CONTROL_PADCONF_DSS_VSYNC	CONTROL_REG32(0x0CC)#define CONTROL_PADCONF_SYS_NIRQW0	CONTROL_REG32(0x0BC)	/* 2430 */#define CONTROL_PADCONF_SSI1_FLAG_TX	CONTROL_REG32(0x108)	/* 2430 *//* CONTROL */#define CONTROL_DEVCONF		CONTROL_REG32(0x274)#define CONTROL_DEVCONF1	CONTROL_REG32(0x2E8)/* INTERRUPT CONTROLLER */#define INTC_BASE		((L4_24XX_BASE) + 0xfe000)#define INTC_REG32(offset)	__REG32(INTC_BASE + (offset))#define INTC1_U_BASE		INTC_REG32(0x000)#define INTC_MIR0		INTC_REG32(0x084)#define INTC_MIR_SET0		INTC_REG32(0x08C)#define INTC_MIR_CLEAR0		INTC_REG32(0x088)#define INTC_ISR_CLEAR0		INTC_REG32(0x094)#define INTC_MIR1		INTC_REG32(0x0A4)#define INTC_MIR_SET1		INTC_REG32(0x0AC)#define INTC_MIR_CLEAR1		INTC_REG32(0x0A8)#define INTC_ISR_CLEAR1		INTC_REG32(0x0B4)#define INTC_MIR2		INTC_REG32(0x0C4)#define INTC_MIR_SET2		INTC_REG32(0x0CC)#define INTC_MIR_CLEAR2		INTC_REG32(0x0C8)#define INTC_ISR_CLEAR2		INTC_REG32(0x0D4)#define INTC_SIR_IRQ		INTC_REG32(0x040)#define INTC_CONTROL		INTC_REG32(0x048)#define INTC_ILR11		INTC_REG32(0x12C)	/* PRCM on MPU PIC */#define INTC_ILR30		INTC_REG32(0x178)#define INTC_ILR31		INTC_REG32(0x17C)#define INTC_ILR32		INTC_REG32(0x180)#define INTC_ILR37		INTC_REG32(0x194)	/* GPIO4 on MPU PIC */#define INTC_SYSCONFIG		INTC_REG32(0x010)	/* GPT1 on MPU PIC *//* RAM FIREWALL */#define RAMFW_BASE		(0x68005000)#define RAMFW_REG32(offset)	__REG32(RAMFW_BASE + (offset))#define RAMFW_REQINFOPERM0	RAMFW_REG32(0x048)#define RAMFW_READPERM0		RAMFW_REG32(0x050)#define RAMFW_WRITEPERM0	RAMFW_REG32(0x058)/* GPMC CS1 FPGA ON USER INTERFACE MODULE *///#define DEBUG_BOARD_LED_REGISTER 0x04000014/* GPMC CS0 */#define GPMC_CONFIG1_0		GPMC_REG32(0x060)#define GPMC_CONFIG2_0		GPMC_REG32(0x064)#define GPMC_CONFIG3_0		GPMC_REG32(0x068)#define GPMC_CONFIG4_0		GPMC_REG32(0x06C)#define GPMC_CONFIG5_0		GPMC_REG32(0x070)#define GPMC_CONFIG6_0		GPMC_REG32(0x074)#define GPMC_CONFIG7_0		GPMC_REG32(0x078)/* GPMC CS1 */#define GPMC_CONFIG1_1		GPMC_REG32(0x090)#define GPMC_CONFIG2_1		GPMC_REG32(0x094)#define GPMC_CONFIG3_1		GPMC_REG32(0x098)#define GPMC_CONFIG4_1		GPMC_REG32(0x09C)#define GPMC_CONFIG5_1		GPMC_REG32(0x0a0)#define GPMC_CONFIG6_1		GPMC_REG32(0x0a4)#define GPMC_CONFIG7_1		GPMC_REG32(0x0a8)/* GPMC CS3 */#define GPMC_CONFIG1_3		GPMC_REG32(0x0F0)#define GPMC_CONFIG2_3		GPMC_REG32(0x0F4)#define GPMC_CONFIG3_3		GPMC_REG32(0x0F8)#define GPMC_CONFIG4_3		GPMC_REG32(0x0FC)#define GPMC_CONFIG5_3		GPMC_REG32(0x100)#define GPMC_CONFIG6_3		GPMC_REG32(0x104)#define GPMC_CONFIG7_3		GPMC_REG32(0x108)/* DSS */#define DSS_CONTROL		DISP_REG32(0x040)#define DISPC_CONTROL		DISP_REG32(0x440)#define DISPC_SYSSTATUS		DISP_REG32(0x414)#define DISPC_IRQSTATUS		DISP_REG32(0x418)#define DISPC_IRQENABLE		DISP_REG32(0x41C)#define DISPC_CONFIG		DISP_REG32(0x444)#define DISPC_DEFAULT_COLOR0	DISP_REG32(0x44C)#define DISPC_DEFAULT_COLOR1	DISP_REG32(0x450)#define DISPC_TRANS_COLOR0	DISP_REG32(0x454)#define DISPC_TRANS_COLOR1	DISP_REG32(0x458)#define DISPC_LINE_NUMBER	DISP_REG32(0x460)#define DISPC_TIMING_H		DISP_REG32(0x464)#define DISPC_TIMING_V		DISP_REG32(0x468)#define DISPC_POL_FREQ		DISP_REG32(0x46C)#define DISPC_DIVISOR		DISP_REG32(0x470)#define DISPC_SIZE_DIG		DISP_REG32(0x478)#define DISPC_SIZE_LCD		DISP_REG32(0x47C)#define DISPC_GFX_BA0		DISP_REG32(0x480)#define DISPC_GFX_BA1		DISP_REG32(0x484)#define DISPC_GFX_POSITION	DISP_REG32(0x488)#define DISPC_GFX_SIZE		DISP_REG32(0x48C)#define DISPC_GFX_ATTRIBUTES	DISP_REG32(0x4A0)#define DISPC_GFX_FIFO_THRESHOLD	DISP_REG32(0x4A4)#define DISPC_GFX_ROW_INC	DISP_REG32(0x4AC)#define DISPC_GFX_PIXEL_INC	DISP_REG32(0x4B0)#define DISPC_GFX_WINDOW_SKIP	DISP_REG32(0x4B4)#define DISPC_GFX_TABLE_BA	DISP_REG32(0x4B8)#define DISPC_DATA_CYCLE1	DISP_REG32(0x5D4)#define DISPC_DATA_CYCLE2	DISP_REG32(0x5D8)#define DISPC_DATA_CYCLE3	DISP_REG32(0x5DC)/* HSUSB Suspend */#define HSUSB_CTRL		__REG8(0x480AC001)#define USBOTG_POWER		__REG32(0x480AC000)/* HS MMC */#define MMCHS1_SYSCONFIG	__REG32(0x4809C010)#define MMCHS2_SYSCONFIG	__REG32(0x480b4010)#endif	/* __ASSEMBLER__ */#endif
上一页 12
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -