clock.h

linux 内核源代码

	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
	.enable_bit	= 23,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk hdq_fck = {
	.name		= "hdq_fck",
	.parent		= &func_12m_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 23,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk i2c2_ick = {
	.name		= "i2c_ick",
	.id		= 2,
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
	.enable_bit	= 20,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk i2c2_fck = {
	.name		= "i2c_fck",
	.id		= 2,
	.parent		= &func_12m_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 20,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk i2chs2_fck = {
	.name		= "i2chs2_fck",
	.parent		= &func_96m_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
	.enable_bit	= 20,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk i2c1_ick = {
	.name		= "i2c_ick",
	.id		= 1,
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
	.enable_bit	= 19,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk i2c1_fck = {
	.name		= "i2c_fck",
	.id		= 1,
	.parent		= &func_12m_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 19,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk i2chs1_fck = {
	.name		= "i2chs1_fck",
	.parent		= &func_96m_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
	.enable_bit	= 19,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk vlynq_ick = {
	.name		= "vlynq_ick",
	.parent		= &core_l3_ck,
	.flags		= CLOCK_IN_OMAP242X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
	.enable_bit	= 3,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk vlynq_fck = {
	.name		= "vlynq_fck",
	.parent		= &func_96m_ck,
	.flags		= CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 3,
	.src_offset	= 15,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk sdrc_ick = {
	.name		= "sdrc_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN3_CORE,
	.enable_bit	= 2,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk des_ick = {
	.name		= "des_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN4_CORE,
	.enable_bit	= 0,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk sha_ick = {
	.name		= "sha_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN4_CORE,
	.enable_bit	= 1,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk rng_ick = {
	.name		= "rng_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN4_CORE,
	.enable_bit	= 2,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk aes_ick = {
	.name		= "aes_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN4_CORE,
	.enable_bit	= 3,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk pka_ick = {
	.name		= "pka_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN4_CORE,
	.enable_bit	= 4,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk usb_fck = {
	.name		= "usb_fck",
	.parent		= &func_48m_ck,
	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
	.enable_bit	= 0,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk usbhs_ick = {
	.name		= "usbhs_ick",
	.parent		= &core_l3_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
	.enable_bit	= 6,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk mmchs1_ick = {
	.name		= "mmchs1_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
	.enable_bit	= 7,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk mmchs1_fck = {
	.name		= "mmchs1_fck",
	.parent		= &func_96m_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
	.enable_bit	= 7,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk mmchs2_ick = {
	.name		= "mmchs2_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
	.enable_bit	= 8,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk mmchs2_fck = {
	.name		= "mmchs2_fck",
	.parent		= &func_96m_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
	.enable_bit	= 8,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpio5_ick = {
	.name		= "gpio5_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
	.enable_bit	= 10,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpio5_fck = {
	.name		= "gpio5_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
	.enable_bit	= 10,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk mdm_intc_ick = {
	.name		= "mdm_intc_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
	.enable_bit	= 11,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk mmchsdb1_fck = {
	.name		= "mmchsdb1_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
	.enable_bit	= 16,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk mmchsdb2_fck = {
	.name		= "mmchsdb2_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
	.enable_bit	= 17,
	.recalc		= &omap2_followparent_recalc,
};

/*
 * This clock is a composite clock which does entire set changes then
 * forces a rebalance. It keys on the MPU speed, but it really could
 * be any key speed part of a set in the rate table.
 *
 * to really change a set, you need memory table sets which get changed
 * in sram, pre-notifiers & post notifiers, changing the top set, without
 * having low level display recalc's won't work... this is why dpm notifiers
 * work, isr's off, walk a list of clocks already _off_ and not messing with
 * the bus.
 *
 * This clock should have no parent. It embodies the entire upper level
 * active set. A parent will mess up some of the init also.
 */
static struct clk virt_prcm_set = {
	.name		= "virt_prcm_set",
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
	.parent		= &mpu_ck,	/* Indexed by mpu speed, no parent */
	.recalc		= &omap2_mpu_recalc,	/* sets are keyed on mpu rate */
	.set_rate	= &omap2_select_table_rate,
	.round_rate	= &omap2_round_to_table_rate,
};

static struct clk *onchip_clks[] = {
	/* external root sources */
	&func_32k_ck,
	&osc_ck,
	&sys_ck,
	&alt_ck,
	/* internal analog sources */
	&dpll_ck,
	&apll96_ck,
	&apll54_ck,
	/* internal prcm root sources */
	&func_54m_ck,
	&core_ck,
	&sleep_ck,
	&func_96m_ck,
	&func_48m_ck,
	&func_12m_ck,
	&wdt1_osc_ck,
	&sys_clkout,
	&sys_clkout2,
	&emul_ck,
	/* mpu domain clocks */
	&mpu_ck,
	/* dsp domain clocks */
	&iva2_1_fck,		/* 2430 */
	&iva2_1_ick,
	&dsp_ick,		/* 2420 */
	&dsp_fck,
	&iva1_ifck,
	&iva1_mpu_int_ifck,
	/* GFX domain clocks */
	&gfx_3d_fck,
	&gfx_2d_fck,
	&gfx_ick,
	/* Modem domain clocks */
	&mdm_ick,
	&mdm_osc_ck,
	/* DSS domain clocks */
	&dss_ick,
	&dss1_fck,
	&dss2_fck,
	&dss_54m_fck,
	/* L3 domain clocks */
	&core_l3_ck,
	&ssi_ssr_sst_fck,
	&usb_l4_ick,
	/* L4 domain clocks */
	&l4_ck,			/* used as both core_l4 and wu_l4 */
	&ssi_l4_ick,
	/* virtual meta-group clock */
	&virt_prcm_set,
	/* general l4 interface ck, multi-parent functional clk */
	&gpt1_ick,
	&gpt1_fck,
	&gpt2_ick,
	&gpt2_fck,
	&gpt3_ick,
	&gpt3_fck,
	&gpt4_ick,
	&gpt4_fck,
	&gpt5_ick,
	&gpt5_fck,
	&gpt6_ick,
	&gpt6_fck,
	&gpt7_ick,
	&gpt7_fck,
	&gpt8_ick,
	&gpt8_fck,
	&gpt9_ick,
	&gpt9_fck,
	&gpt10_ick,
	&gpt10_fck,
	&gpt11_ick,
	&gpt11_fck,
	&gpt12_ick,
	&gpt12_fck,
	&mcbsp1_ick,
	&mcbsp1_fck,
	&mcbsp2_ick,
	&mcbsp2_fck,
	&mcbsp3_ick,
	&mcbsp3_fck,
	&mcbsp4_ick,
	&mcbsp4_fck,
	&mcbsp5_ick,
	&mcbsp5_fck,
	&mcspi1_ick,
	&mcspi1_fck,
	&mcspi2_ick,
	&mcspi2_fck,
	&mcspi3_ick,
	&mcspi3_fck,
	&uart1_ick,
	&uart1_fck,
	&uart2_ick,
	&uart2_fck,
	&uart3_ick,
	&uart3_fck,
	&gpios_ick,
	&gpios_fck,
	&mpu_wdt_ick,
	&mpu_wdt_fck,
	&sync_32k_ick,
	&wdt1_ick,
	&omapctrl_ick,
	&icr_ick,
	&cam_fck,
	&cam_ick,
	&mailboxes_ick,
	&wdt4_ick,
	&wdt4_fck,
	&wdt3_ick,
	&wdt3_fck,
	&mspro_ick,
	&mspro_fck,
	&mmc_ick,
	&mmc_fck,
	&fac_ick,
	&fac_fck,
	&eac_ick,
	&eac_fck,
	&hdq_ick,
	&hdq_fck,
	&i2c1_ick,
	&i2c1_fck,
	&i2chs1_fck,
	&i2c2_ick,
	&i2c2_fck,
	&i2chs2_fck,
	&vlynq_ick,
	&vlynq_fck,
	&sdrc_ick,
	&des_ick,
	&sha_ick,
	&rng_ick,
	&aes_ick,
	&pka_ick,
	&usb_fck,
	&usbhs_ick,
	&mmchs1_ick,
	&mmchs1_fck,
	&mmchs2_ick,
	&mmchs2_fck,
	&gpio5_ick,
	&gpio5_fck,
	&mdm_intc_ick,
	&mmchsdb1_fck,
	&mmchsdb2_fck,
};

#endif