clock.h

linux 内核源代码

	.parent		= &core_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
				DELAYED_APP | CONFIG_PARTICIPANT |
				RATE_PROPAGATES,
	.rate_offset	= 0,
	.recalc		= &omap2_clksel_recalc,
};

static struct clk usb_l4_ick = {	/* FS-USB interface clock */
	.name		= "usb_l4_ick",
	.parent		= &core_l3_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
				CONFIG_PARTICIPANT,
	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
	.enable_bit	= 0,
	.rate_offset = 25,
	.recalc		= &omap2_clksel_recalc,
};

/*
 * SSI is in L3 management domain, its direct parent is core not l3,
 * many core power domain entities are grouped into the L3 clock
 * domain.
 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
 *
 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 */
static struct clk ssi_ssr_sst_fck = {
	.name		= "ssi_fck",
	.parent		= &core_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,	/* bit 1 */
	.enable_bit	= 1,
	.rate_offset = 20,
	.recalc		= &omap2_clksel_recalc,
};

/*
 * GFX clock domain
 *	Clocks:
 * GFX_FCLK, GFX_ICLK
 * GFX_CG1(2d), GFX_CG2(3d)
 *
 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 * The 2d and 3d clocks run at a hardware determined
 * divided value of fclk.
 *
 */
static struct clk gfx_3d_fck = {
	.name		= "gfx_3d_fck",
	.parent		= &core_l3_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_CKCTL | CM_GFX_SEL1,
	.enable_reg	= (void __iomem *)&CM_FCLKEN_GFX,
	.enable_bit	= 2,
	.rate_offset= 0,
	.recalc		= &omap2_clksel_recalc,
};

static struct clk gfx_2d_fck = {
	.name		= "gfx_2d_fck",
	.parent		= &core_l3_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_CKCTL | CM_GFX_SEL1,
	.enable_reg	= (void __iomem *)&CM_FCLKEN_GFX,
	.enable_bit	= 1,
	.rate_offset= 0,
	.recalc		= &omap2_clksel_recalc,
};

static struct clk gfx_ick = {
	.name		= "gfx_ick",		/* From l3 */
	.parent		= &core_l3_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_CKCTL,
	.enable_reg	= (void __iomem *)&CM_ICLKEN_GFX,	/* bit 0 */
	.enable_bit	= 0,
	.recalc		= &omap2_followparent_recalc,
};

/*
 * Modem clock domain (2430)
 *	CLOCKS:
 *		MDM_OSC_CLK
 *		MDM_ICLK
 */
static struct clk mdm_ick = {		/* used both as a ick and fck */
	.name		= "mdm_ick",
	.parent		= &core_ck,
	.flags		= CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
				DELAYED_APP | CONFIG_PARTICIPANT,
	.rate_offset	= 0,
	.enable_reg	= (void __iomem *)&CM_ICLKEN_MDM,
	.enable_bit	= 0,
	.recalc		= &omap2_clksel_recalc,
};

static struct clk mdm_osc_ck = {
	.name		= "mdm_osc_ck",
	.rate		= 26000000,
	.parent		= &osc_ck,
	.flags		= CLOCK_IN_OMAP243X | RATE_FIXED,
	.enable_reg	= (void __iomem *)&CM_FCLKEN_MDM,
	.enable_bit	= 1,
	.recalc		= &omap2_followparent_recalc,
};

/*
 * L4 clock management domain
 *
 * This domain contains lots of interface clocks from the L4 interface, some
 * functional clocks.	Fixed APLL functional source clocks are managed in
 * this domain.
 */
static struct clk l4_ck = {		/* used both as an ick and fck */
	.name		= "l4_ck",
	.parent		= &core_l3_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
				DELAYED_APP | RATE_PROPAGATES,
	.rate_offset	= 5,
	.recalc		= &omap2_clksel_recalc,
};

static struct clk ssi_l4_ick = {
	.name		= "ssi_l4_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,	/* bit 1 */
	.enable_bit	= 1,
	.recalc		= &omap2_followparent_recalc,
};

/*
 * DSS clock domain
 * CLOCKs:
 * DSS_L4_ICLK, DSS_L3_ICLK,
 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
 *
 * DSS is both initiator and target.
 */
static struct clk dss_ick = {		/* Enables both L3,L4 ICLK's */
	.name		= "dss_ick",
	.parent		= &l4_ck,	/* really both l3 and l4 */
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
	.enable_bit	= 0,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk dss1_fck = {
	.name		= "dss1_fck",
	.parent		= &core_ck,		/* Core or sys */
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 0,
	.rate_offset	= 8,
	.src_offset	= 8,
	.recalc		= &omap2_clksel_recalc,
};

static struct clk dss2_fck = {		/* Alt clk used in power management */
	.name		= "dss2_fck",
	.parent		= &sys_ck,		/* fixed at sys_ck or 48MHz */
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
				DELAYED_APP,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 1,
	.src_offset	= 13,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk dss_54m_fck = {	/* Alt clk used in power management */
	.name		= "dss_54m_fck",	/* 54m tv clk */
	.parent		= &func_54m_ck,
	.rate		= 54000000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_FIXED | RATE_PROPAGATES,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 2,
	.recalc		= &omap2_propagate_rate,
};

/*
 * CORE power domain ICLK & FCLK defines.
 * Many of the these can have more than one possible parent. Entries
 * here will likely have an L4 interface parent, and may have multiple
 * functional clock parents.
 */
static struct clk gpt1_ick = {
	.name		= "gpt1_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN_WKUP,	/* Bit0 */
	.enable_bit	= 0,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt1_fck = {
	.name		= "gpt1_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				CM_WKUP_SEL1,
	.enable_reg	= (void __iomem *)&CM_FCLKEN_WKUP,	/* Bit0 */
	.enable_bit	= 0,
	.src_offset	= 0,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt2_ick = {
	.name		= "gpt2_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	/* Bit4 */
	.enable_bit	= 4,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt2_fck = {
	.name		= "gpt2_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				CM_CORE_SEL2,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 4,
	.src_offset	= 2,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt3_ick = {
	.name		= "gpt3_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	/* Bit5 */
	.enable_bit	= 5,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt3_fck = {
	.name		= "gpt3_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				CM_CORE_SEL2,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 5,
	.src_offset	= 4,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt4_ick = {
	.name		= "gpt4_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	/* Bit6 */
	.enable_bit	= 6,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt4_fck = {
	.name		= "gpt4_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				CM_CORE_SEL2,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 6,
	.src_offset	= 6,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt5_ick = {
	.name		= "gpt5_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	 /* Bit7 */
	.enable_bit	= 7,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt5_fck = {
	.name		= "gpt5_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				CM_CORE_SEL2,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 7,
	.src_offset	= 8,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt6_ick = {
	.name		= "gpt6_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_bit	= 8,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	 /* bit8 */
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt6_fck = {
	.name		= "gpt6_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				CM_CORE_SEL2,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 8,
	.src_offset	= 10,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt7_ick = {
	.name		= "gpt7_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	 /* bit9 */
	.enable_bit	= 9,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt7_fck = {
	.name		= "gpt7_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				CM_CORE_SEL2,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 9,
	.src_offset	= 12,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt8_ick = {
	.name		= "gpt8_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	 /* bit10 */
	.enable_bit	= 10,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt8_fck = {
	.name		= "gpt8_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				CM_CORE_SEL2,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 10,
	.src_offset	= 14,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt9_ick = {
	.name		= "gpt9_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
	.enable_bit	= 11,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt9_fck = {
	.name		= "gpt9_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
					CM_CORE_SEL2,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 11,
	.src_offset	= 16,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt10_ick = {
	.name		= "gpt10_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
	.enable_bit	= 12,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt10_fck = {
	.name		= "gpt10_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
					CM_CORE_SEL2,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 12,
	.src_offset	= 18,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt11_ick = {
	.name		= "gpt11_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
	.enable_bit	= 13,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt11_fck = {
	.name		= "gpt11_fck",
	.parent		= &func_32k_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
					CM_CORE_SEL2,
	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
	.enable_bit	= 13,
	.src_offset	= 20,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk gpt12_ick = {
	.name		= "gpt12_ick",
	.parent		= &l4_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	 /* bit14 */
	.enable_bit	= 14,
	.recalc		= &omap2_followparent_recalc,
};