clock.h

linux 内核源代码

	{S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,		/* 150MHz ARM */
		RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
		RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
		MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
		RATE_IN_242X},

	{S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,		/* 150MHz ARM */
		RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
		RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
		MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
		RATE_IN_242X},

	/* PRCM III - SLOW */
	{S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,		/* 133MHz ARM */
		RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
		RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
		MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
		RATE_IN_242X},

	{S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,		/* 133MHz ARM */
		RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
		RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
		MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
		RATE_IN_242X},

	/* PRCM-VII (boot-bypass) */
	{S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,		/* 12MHz ARM*/
		RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
		RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
		MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
		RATE_IN_242X},

	/* PRCM-VII (boot-bypass) */
	{S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,		/* 13MHz ARM */
		RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
		RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
		MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
		RATE_IN_242X},

	/* PRCM #3 - ratio2 (ES2) - FAST */
	{S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,		/* 330MHz ARM */
		R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
		R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
		MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
		V24XX_SDRC_RFR_CTRL_110MHz,
		RATE_IN_243X},

	/* PRCM #5a - ratio1 - FAST */
	{S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,		/* 266MHz ARM */
		R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
		R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
		MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
		V24XX_SDRC_RFR_CTRL_133MHz,
		RATE_IN_243X},

	/* PRCM #5b - ratio1 - FAST */
	{S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,		/* 200MHz ARM */
		R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
		R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
		MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
		V24XX_SDRC_RFR_CTRL_100MHz,
		RATE_IN_243X},

	/* PRCM #3 - ratio2 (ES2) - SLOW */
	{S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,		/* 165MHz ARM */
		R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
		R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
		MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
		V24XX_SDRC_RFR_CTRL_110MHz,
		RATE_IN_243X},

	/* PRCM #5a - ratio1 - SLOW */
	{S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,		/* 133MHz ARM */
		R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
		R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
		MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
		V24XX_SDRC_RFR_CTRL_133MHz,
		RATE_IN_243X},

	/* PRCM #5b - ratio1 - SLOW*/
	{S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,		/* 100MHz ARM */
		R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
		R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
		MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
		V24XX_SDRC_RFR_CTRL_100MHz,
		RATE_IN_243X},

	/* PRCM-boot/bypass */
	{S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,		/* 13Mhz */
		RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
		RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
		MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
		V24XX_SDRC_RFR_CTRL_BYPASS,
		RATE_IN_243X},

	/* PRCM-boot/bypass */
	{S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,		/* 12Mhz */
		RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
		RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
		MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
		V24XX_SDRC_RFR_CTRL_BYPASS,
		RATE_IN_243X},

	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};

/*-------------------------------------------------------------------------
 * 24xx clock tree.
 *
 * NOTE:In many cases here we are assigning a 'default' parent.	In many
 *	cases the parent is selectable.	The get/set parent calls will also
 *	switch sources.
 *
 *	Many some clocks say always_enabled, but they can be auto idled for
 *	power savings. They will always be available upon clock request.
 *
 *	Several sources are given initial rates which may be wrong, this will
 *	be fixed up in the init func.
 *
 *	Things are broadly separated below by clock domains. It is
 *	noteworthy that most periferals have dependencies on multiple clock
 *	domains. Many get their interface clocks from the L4 domain, but get
 *	functional clocks from fixed sources or other core domain derived
 *	clocks.
 *-------------------------------------------------------------------------*/

/* Base external input clocks */
static struct clk func_32k_ck = {
	.name		= "func_32k_ck",
	.rate		= 32000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_FIXED | ALWAYS_ENABLED,
};

/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
static struct clk osc_ck = {		/* (*12, *13, 19.2, *26, 38.4)MHz */
	.name		= "osc_ck",
	.rate		= 26000000,		/* fixed up in clock init */
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_FIXED | RATE_PROPAGATES,
};

/* With out modem likely 12MHz, with modem likely 13MHz */
static struct clk sys_ck = {		/* (*12, *13, 19.2, 26, 38.4)MHz */
	.name		= "sys_ck",		/* ~ ref_clk also */
	.parent		= &osc_ck,
	.rate		= 13000000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
	.rate_offset	= 6, /* sysclkdiv 1 or 2, already handled or no boot */
	.recalc		= &omap2_sys_clk_recalc,
};

static struct clk alt_ck = {		/* Typical 54M or 48M, may not exist */
	.name		= "alt_ck",
	.rate		= 54000000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
	.recalc		= &omap2_propagate_rate,
};

/*
 * Analog domain root source clocks
 */

/* dpll_ck, is broken out in to special cases through clksel */
static struct clk dpll_ck = {
	.name		= "dpll_ck",
	.parent		= &sys_ck,		/* Can be func_32k also */
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
	.recalc		= &omap2_clksel_recalc,
};

static struct clk apll96_ck = {
	.name		= "apll96_ck",
	.parent		= &sys_ck,
	.rate		= 96000000,
	.flags		= CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
				RATE_FIXED | RATE_PROPAGATES,
	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
	.enable_bit	= 0x2,
	.recalc		= &omap2_propagate_rate,
};

static struct clk apll54_ck = {
	.name		= "apll54_ck",
	.parent		= &sys_ck,
	.rate		= 54000000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_FIXED | RATE_PROPAGATES,
	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
	.enable_bit	= 0x6,
	.recalc		= &omap2_propagate_rate,
};

/*
 * PRCM digital base sources
 */
static struct clk func_54m_ck = {
	.name		= "func_54m_ck",
	.parent		= &apll54_ck,	/* can also be alt_clk */
	.rate		= 54000000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
	.src_offset	= 5,
	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
	.enable_bit	= 0xff,
	.recalc		= &omap2_propagate_rate,
};

static struct clk core_ck = {
	.name		= "core_ck",
	.parent		= &dpll_ck,		/* can also be 32k */
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				ALWAYS_ENABLED | RATE_PROPAGATES,
	.recalc		= &omap2_propagate_rate,
};

static struct clk sleep_ck = {		/* sys_clk or 32k */
	.name		= "sleep_ck",
	.parent		= &func_32k_ck,
	.rate		= 32000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.recalc		= &omap2_propagate_rate,
};

static struct clk func_96m_ck = {
	.name		= "func_96m_ck",
	.parent		= &apll96_ck,
	.rate		= 96000000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_FIXED | RATE_PROPAGATES,
	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
	.enable_bit	= 0xff,
	.recalc		= &omap2_propagate_rate,
};

static struct clk func_48m_ck = {
	.name		= "func_48m_ck",
	.parent		= &apll96_ck,	 /* 96M or Alt */
	.rate		= 48000000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
	.src_offset	= 3,
	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
	.enable_bit	= 0xff,
	.recalc		= &omap2_propagate_rate,
};

static struct clk func_12m_ck = {
	.name		= "func_12m_ck",
	.parent		= &func_48m_ck,
	.rate		= 12000000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				RATE_FIXED | RATE_PROPAGATES,
	.recalc		= &omap2_propagate_rate,
	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
	.enable_bit	= 0xff,
};

/* Secure timer, only available in secure mode */
static struct clk wdt1_osc_ck = {
	.name		= "ck_wdt1_osc",
	.parent		= &osc_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
	.recalc		= &omap2_followparent_recalc,
};

static struct clk sys_clkout = {
	.name		= "sys_clkout",
	.parent		= &func_54m_ck,
	.rate		= 54000000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
	.src_offset	= 0,
	.enable_reg	= (void __iomem *)&PRCM_CLKOUT_CTRL,
	.enable_bit	= 7,
	.rate_offset	= 3,
	.recalc		= &omap2_clksel_recalc,
};

/* In 2430, new in 2420 ES2 */
static struct clk sys_clkout2 = {
	.name		= "sys_clkout2",
	.parent		= &func_54m_ck,
	.rate		= 54000000,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
				CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
	.src_offset	= 8,
	.enable_reg	= (void __iomem *)&PRCM_CLKOUT_CTRL,
	.enable_bit	= 15,
	.rate_offset	= 11,
	.recalc		= &omap2_clksel_recalc,
};

static struct clk emul_ck = {
	.name		= "emul_ck",
	.parent		= &func_54m_ck,
	.flags		= CLOCK_IN_OMAP242X,
	.enable_reg	= (void __iomem *)&PRCM_CLKEMUL_CTRL,
	.enable_bit	= 0,
	.recalc		= &omap2_propagate_rate,

};

/*
 * MPU clock domain
 *	Clocks:
 *		MPU_FCLK, MPU_ICLK
 *		INT_M_FCLK, INT_M_I_CLK
 *
 * - Individual clocks are hardware managed.
 * - Base divider comes from: CM_CLKSEL_MPU
 *
 */
static struct clk mpu_ck = {	/* Control cpu */
	.name		= "mpu_ck",
	.parent		= &core_ck,
	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
				ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
				CONFIG_PARTICIPANT | RATE_PROPAGATES,
	.rate_offset	= 0,	/* bits 0-4 */
	.recalc		= &omap2_clksel_recalc,
};

/*
 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 * Clocks:
 *	2430: IVA2.1_FCLK, IVA2.1_ICLK
 *	2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 */
static struct clk iva2_1_fck = {
	.name		= "iva2_1_fck",
	.parent		= &core_ck,
	.flags		= CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
				DELAYED_APP | RATE_PROPAGATES |
				CONFIG_PARTICIPANT,
	.rate_offset	= 0,
	.enable_reg	= (void __iomem *)&CM_FCLKEN_DSP,
	.enable_bit	= 0,
	.recalc		= &omap2_clksel_recalc,
};

static struct clk iva2_1_ick = {
	.name		= "iva2_1_ick",
	.parent		= &iva2_1_fck,
	.flags		= CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
				DELAYED_APP | CONFIG_PARTICIPANT,
	.rate_offset	= 5,
	.recalc		= &omap2_clksel_recalc,
};

/*
 * Won't be too specific here. The core clock comes into this block
 * it is divided then tee'ed. One branch goes directly to xyz enable
 * controls. The other branch gets further divided by 2 then possibly
 * routed into a synchronizer and out of clocks abc.
 */
static struct clk dsp_fck = {
	.name		= "dsp_fck",
	.parent		= &core_ck,
	.flags		= CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
			DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
	.rate_offset	= 0,
	.enable_reg	= (void __iomem *)&CM_FCLKEN_DSP,
	.enable_bit	= 0,
	.recalc		= &omap2_clksel_recalc,
};

static struct clk dsp_ick = {
	.name		= "dsp_ick",	 /* apparently ipi and isp */
	.parent		= &dsp_fck,
	.flags		= CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
				DELAYED_APP | CONFIG_PARTICIPANT,
	.rate_offset = 5,
	.enable_reg	= (void __iomem *)&CM_ICLKEN_DSP,
	.enable_bit	= 1,		/* for ipi */
	.recalc		= &omap2_clksel_recalc,
};

static struct clk iva1_ifck = {
	.name		= "iva1_ifck",
	.parent		= &core_ck,
	.flags		= CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
			CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
	.rate_offset= 8,
	.enable_reg	= (void __iomem *)&CM_FCLKEN_DSP,
	.enable_bit	= 10,
	.recalc		= &omap2_clksel_recalc,
};

/* IVA1 mpu/int/i/f clocks are /2 of parent */
static struct clk iva1_mpu_int_ifck = {
	.name		= "iva1_mpu_int_ifck",
	.parent		= &iva1_ifck,
	.flags		= CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
	.enable_reg	= (void __iomem *)&CM_FCLKEN_DSP,
	.enable_bit	= 8,
	.recalc		= &omap2_clksel_recalc,
};

/*
 * L3 clock domain
 * L3 clocks are used for both interface and functional clocks to
 * multiple entities. Some of these clocks are completely managed
 * by hardware, and some others allow software control. Hardware
 * managed ones general are based on directly CLK_REQ signals and
 * various auto idle settings. The functional spec sets many of these
 * as 'tie-high' for their enables.
 *
 * I-CLOCKS:
 *	L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 *	CAM, HS-USB.
 * F-CLOCK
 *	SSI.
 *
 * GPMC memories and SDRC have timing and clock sensitive registers which
 * may very well need notification when the clock changes. Currently for low
 * operating points, these are taken care of in sleep.S.
 */
static struct clk core_l3_ck = {	/* Used for ick and fck, interconnect */
	.name		= "core_l3_ck",