setup.c

linux 内核源代码

static u64 iop13xx_adma_dmamask = DMA_64BIT_MASK;
static struct iop_adma_platform_data iop13xx_adma_0_data = {
	.hw_id = 0,
	.pool_size = PAGE_SIZE,
};

static struct iop_adma_platform_data iop13xx_adma_1_data = {
	.hw_id = 1,
	.pool_size = PAGE_SIZE,
};

static struct iop_adma_platform_data iop13xx_adma_2_data = {
	.hw_id = 2,
	.pool_size = PAGE_SIZE,
};

/* The ids are fixed up later in iop13xx_platform_init */
static struct platform_device iop13xx_adma_0_channel = {
	.name = "iop-adma",
	.id = 0,
	.num_resources = 4,
	.resource = iop13xx_adma_0_resources,
	.dev = {
		.dma_mask = &iop13xx_adma_dmamask,
		.coherent_dma_mask = DMA_64BIT_MASK,
		.platform_data = (void *) &iop13xx_adma_0_data,
	},
};

static struct platform_device iop13xx_adma_1_channel = {
	.name = "iop-adma",
	.id = 0,
	.num_resources = 4,
	.resource = iop13xx_adma_1_resources,
	.dev = {
		.dma_mask = &iop13xx_adma_dmamask,
		.coherent_dma_mask = DMA_64BIT_MASK,
		.platform_data = (void *) &iop13xx_adma_1_data,
	},
};

static struct platform_device iop13xx_adma_2_channel = {
	.name = "iop-adma",
	.id = 0,
	.num_resources = 4,
	.resource = iop13xx_adma_2_resources,
	.dev = {
		.dma_mask = &iop13xx_adma_dmamask,
		.coherent_dma_mask = DMA_64BIT_MASK,
		.platform_data = (void *) &iop13xx_adma_2_data,
	},
};

void __init iop13xx_map_io(void)
{
	/* Initialize the Static Page Table maps */
	iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
}

static int init_uart;
static int init_i2c;
static int init_adma;

void __init iop13xx_platform_init(void)
{
	int i;
	u32 uart_idx, i2c_idx, adma_idx, plat_idx;
	struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];

	/* set the bases so we can read the device id */
	iop13xx_set_atu_mmr_bases();

	memset(iop13xx_devices, 0, sizeof(iop13xx_devices));

	if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
		switch (iop13xx_dev_id()) {
		/* enable both uarts on iop341 */
		case 0x3380:
		case 0x3384:
		case 0x3388:
		case 0x338c:
			init_uart |= IOP13XX_INIT_UART_0;
			init_uart |= IOP13XX_INIT_UART_1;
			break;
		/* only enable uart 1 */
		default:
			init_uart |= IOP13XX_INIT_UART_1;
		}
	}

	if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
		switch (iop13xx_dev_id()) {
		/* enable all i2c units on iop341 and iop342 */
		case 0x3380:
		case 0x3384:
		case 0x3388:
		case 0x338c:
		case 0x3382:
		case 0x3386:
		case 0x338a:
		case 0x338e:
			init_i2c |= IOP13XX_INIT_I2C_0;
			init_i2c |= IOP13XX_INIT_I2C_1;
			init_i2c |= IOP13XX_INIT_I2C_2;
			break;
		/* only enable i2c 1 and 2 */
		default:
			init_i2c |= IOP13XX_INIT_I2C_1;
			init_i2c |= IOP13XX_INIT_I2C_2;
		}
	}

	if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) {
		init_adma |= IOP13XX_INIT_ADMA_0;
		init_adma |= IOP13XX_INIT_ADMA_1;
		init_adma |= IOP13XX_INIT_ADMA_2;
	}

	plat_idx = 0;
	uart_idx = 0;
	i2c_idx = 0;

	/* uart 1 (if enabled) is ttyS0 */
	if (init_uart & IOP13XX_INIT_UART_1) {
		PRINTK("Adding uart1 to platform device list\n");
		iop13xx_uart1.id = uart_idx++;
		iop13xx_devices[plat_idx++] = &iop13xx_uart1;
	}
	if (init_uart & IOP13XX_INIT_UART_0) {
		PRINTK("Adding uart0 to platform device list\n");
		iop13xx_uart0.id = uart_idx++;
		iop13xx_devices[plat_idx++] = &iop13xx_uart0;
	}

	for(i = 0; i < IQ81340_NUM_I2C; i++) {
		if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
			printk("Adding i2c%d to platform device list\n", i);
		switch(init_i2c & (1 << i)) {
		case IOP13XX_INIT_I2C_0:
			iop13xx_i2c_0_controller.id = i2c_idx++;
			iop13xx_devices[plat_idx++] =
				&iop13xx_i2c_0_controller;
			break;
		case IOP13XX_INIT_I2C_1:
			iop13xx_i2c_1_controller.id = i2c_idx++;
			iop13xx_devices[plat_idx++] =
				&iop13xx_i2c_1_controller;
			break;
		case IOP13XX_INIT_I2C_2:
			iop13xx_i2c_2_controller.id = i2c_idx++;
			iop13xx_devices[plat_idx++] =
				&iop13xx_i2c_2_controller;
			break;
		}
	}

	/* initialize adma channel ids and capabilities */
	adma_idx = 0;
	for (i = 0; i < IQ81340_NUM_ADMA; i++) {
		struct iop_adma_platform_data *plat_data;
		if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG)
			printk(KERN_INFO
				"Adding adma%d to platform device list\n", i);
		switch (init_adma & (1 << i)) {
		case IOP13XX_INIT_ADMA_0:
			iop13xx_adma_0_channel.id = adma_idx++;
			iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel;
			plat_data = &iop13xx_adma_0_data;
			dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
			dma_cap_set(DMA_XOR, plat_data->cap_mask);
			dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask);
			dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask);
			dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
			dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask);
			dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
			break;
		case IOP13XX_INIT_ADMA_1:
			iop13xx_adma_1_channel.id = adma_idx++;
			iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel;
			plat_data = &iop13xx_adma_1_data;
			dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
			dma_cap_set(DMA_XOR, plat_data->cap_mask);
			dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask);
			dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask);
			dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
			dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask);
			dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
			break;
		case IOP13XX_INIT_ADMA_2:
			iop13xx_adma_2_channel.id = adma_idx++;
			iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel;
			plat_data = &iop13xx_adma_2_data;
			dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
			dma_cap_set(DMA_XOR, plat_data->cap_mask);
			dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask);
			dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask);
			dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
			dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask);
			dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
			dma_cap_set(DMA_PQ_XOR, plat_data->cap_mask);
			dma_cap_set(DMA_PQ_UPDATE, plat_data->cap_mask);
			dma_cap_set(DMA_PQ_ZERO_SUM, plat_data->cap_mask);
			break;
		}
	}

#ifdef CONFIG_MTD_PHYSMAP
	iq8134x_flash_resource.end = iq8134x_flash_resource.start +
				iq8134x_probe_flash_size() - 1;
	if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
		iop13xx_devices[plat_idx++] = &iq8134x_flash;
	else
		printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
#endif

	platform_add_devices(iop13xx_devices, plat_idx);
}

static int __init iop13xx_init_uart_setup(char *str)
{
	if (str) {
		while (*str != '\0') {
			switch(*str) {
			case '0':
				init_uart |= IOP13XX_INIT_UART_0;
				break;
			case '1':
				init_uart |= IOP13XX_INIT_UART_1;
				break;
			case ',':
			case '=':
				break;
			default:
				PRINTK("\"iop13xx_init_uart\" malformed"
					    " at character: \'%c\'", *str);
				*(str + 1) = '\0';
				init_uart = IOP13XX_INIT_UART_DEFAULT;
			}
			str++;
		}
	}
	return 1;
}

static int __init iop13xx_init_i2c_setup(char *str)
{
	if (str) {
		while (*str != '\0') {
			switch(*str) {
			case '0':
				init_i2c |= IOP13XX_INIT_I2C_0;
				break;
			case '1':
				init_i2c |= IOP13XX_INIT_I2C_1;
				break;
			case '2':
				init_i2c |= IOP13XX_INIT_I2C_2;
				break;
			case ',':
			case '=':
				break;
			default:
				PRINTK("\"iop13xx_init_i2c\" malformed"
					    " at character: \'%c\'", *str);
				*(str + 1) = '\0';
				init_i2c = IOP13XX_INIT_I2C_DEFAULT;
			}
			str++;
		}
	}
	return 1;
}

static int __init iop13xx_init_adma_setup(char *str)
{
	if (str)	{
		while (*str != '\0') {
			switch (*str) {
			case '0':
				init_adma |= IOP13XX_INIT_ADMA_0;
				break;
			case '1':
				init_adma |= IOP13XX_INIT_ADMA_1;
				break;
			case '2':
				init_adma |= IOP13XX_INIT_ADMA_2;
				break;
			case ',':
			case '=':
				break;
			default:
				PRINTK("\"iop13xx_init_adma\" malformed"
					    " at character: \'%c\'", *str);
				*(str + 1) = '\0';
				init_adma = IOP13XX_INIT_ADMA_DEFAULT;
			}
			str++;
		}
	}
	return 1;
}

__setup("iop13xx_init_adma", iop13xx_init_adma_setup);
__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);