clock.c

linux 内核源代码

/* linux/arch/arm/mach-s3c2443/clock.c
 *
 * Copyright (c) 2007 Simtec Electronics
 *	Ben Dooks <[e-mail]>
 *
 * S3C2443 Clock control support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/sysdev.h>
#include <linux/clk.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/serial_core.h>

#include <asm/mach/map.h>

#include <asm/hardware.h>
#include <asm/io.h>

#include <asm/arch/regs-s3c2443-clock.h>

#include <asm/plat-s3c24xx/s3c2443.h>
#include <asm/plat-s3c24xx/clock.h>
#include <asm/plat-s3c24xx/cpu.h>

/* We currently have to assume that the system is running
 * from the XTPll input, and that all ***REFCLKs are being
 * fed from it, as we cannot read the state of OM[4] from
 * software.
 *
 * It would be possible for each board initialisation to
 * set the correct muxing at initialisation
*/

static int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
{
	unsigned int clocks = clk->ctrlbit;
	unsigned long clkcon;

	clkcon = __raw_readl(S3C2443_HCLKCON);

	if (enable)
		clkcon |= clocks;
	else
		clkcon &= ~clocks;

	__raw_writel(clkcon, S3C2443_HCLKCON);

	return 0;
}

static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
{
	unsigned int clocks = clk->ctrlbit;
	unsigned long clkcon;

	clkcon = __raw_readl(S3C2443_PCLKCON);

	if (enable)
		clkcon |= clocks;
	else
		clkcon &= ~clocks;

	__raw_writel(clkcon, S3C2443_HCLKCON);

	return 0;
}

static int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
{
	unsigned int clocks = clk->ctrlbit;
	unsigned long clkcon;

	clkcon = __raw_readl(S3C2443_SCLKCON);

	if (enable)
		clkcon |= clocks;
	else
		clkcon &= ~clocks;

	__raw_writel(clkcon, S3C2443_SCLKCON);

	return 0;
}

static unsigned long s3c2443_roundrate_clksrc(struct clk *clk,
					      unsigned long rate,
					      unsigned int max)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	int div;

	if (rate > parent_rate)
		return parent_rate;

	/* note, we remove the +/- 1 calculations as they cancel out */

	div = (rate / parent_rate);

	if (div < 1)
		div = 1;
	else if (div > max)
		div = max;

	return parent_rate / div;
}

static unsigned long s3c2443_roundrate_clksrc4(struct clk *clk,
					       unsigned long rate)
{
	return s3c2443_roundrate_clksrc(clk, rate, 4);
}

static unsigned long s3c2443_roundrate_clksrc16(struct clk *clk,
						unsigned long rate)
{
	return s3c2443_roundrate_clksrc(clk, rate, 16);
}

static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk,
						 unsigned long rate)
{
	return s3c2443_roundrate_clksrc(clk, rate, 256);
}

/* clock selections */

/* CPU EXTCLK input */
static struct clk clk_ext = {
	.name		= "ext",
	.id		= -1,
};

static struct clk clk_mpllref = {
	.name		= "mpllref",
	.parent		= &clk_xtal,
	.id		= -1,
};

#if 0
static struct clk clk_mpll = {
	.name		= "mpll",
	.parent		= &clk_mpllref,
	.id		= -1,
};
#endif

static struct clk clk_epllref;

static struct clk clk_epll = {
	.name		= "epll",
	.parent		= &clk_epllref,
	.id		= -1,
};

static struct clk clk_i2s_ext = {
	.name		= "i2s-ext",
	.id		= -1,
};

static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent)
{
	unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);

	clksrc &= ~S3C2443_CLKSRC_EPLLREF_MASK;

	if (parent == &clk_xtal)
		clksrc |= S3C2443_CLKSRC_EPLLREF_XTAL;
	else if (parent == &clk_ext)
		clksrc |= S3C2443_CLKSRC_EPLLREF_EXTCLK;
	else if (parent != &clk_mpllref)
		return -EINVAL;

	__raw_writel(clksrc, S3C2443_CLKSRC);
	clk->parent = parent;

	return 0;
}

static struct clk clk_epllref = {
	.name		= "epllref",
	.id		= -1,
	.set_parent	= s3c2443_setparent_epllref,
};

static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long div = __raw_readl(S3C2443_CLKDIV0);

	div  &= S3C2443_CLKDIV0_EXTDIV_MASK;
	div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1);	/* x2 */

	return parent_rate / (div + 1);
}

static struct clk clk_mdivclk = {
	.name		= "mdivclk",
	.parent		= &clk_mpllref,
	.id		= -1,
	.get_rate	= s3c2443_getrate_mdivclk,
};


static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
{
	unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);

	clksrc &= ~(S3C2443_CLKSRC_MSYSCLK_MPLL |
		    S3C2443_CLKSRC_EXTCLK_DIV);

	if (parent == &clk_mpll)
		clksrc |= S3C2443_CLKSRC_MSYSCLK_MPLL;
	else if (parent == &clk_mdivclk)
		clksrc |= S3C2443_CLKSRC_EXTCLK_DIV;
	else if (parent != &clk_mpllref)
		return -EINVAL;

	__raw_writel(clksrc, S3C2443_CLKSRC);
	clk->parent = parent;

	return 0;
}

static struct clk clk_msysclk = {
	.name		= "msysclk",
	.parent		= &clk_xtal,
	.id		= -1,
	.set_parent	= s3c2443_setparent_msysclk,
};


/* esysclk
 *
 * this is sourced from either the EPLL or the EPLLref clock
*/

static int s3c2443_setparent_esysclk(struct clk *clk, struct clk *parent)
{
	unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);

	if (parent == &clk_epll)
		clksrc |= S3C2443_CLKSRC_ESYSCLK_EPLL;
	else if (parent == &clk_epllref)
		clksrc &= ~S3C2443_CLKSRC_ESYSCLK_EPLL;
	else
		return -EINVAL;

	__raw_writel(clksrc, S3C2443_CLKSRC);
	clk->parent = parent;

	return 0;
}

static struct clk clk_esysclk = {
	.name		= "esysclk",
	.parent		= &clk_epll,
	.id		= -1,
	.set_parent	= s3c2443_setparent_esysclk,
};

/* uartclk
 *
 * UART baud-rate clock sourced from esysclk via a divisor
*/

static unsigned long s3c2443_getrate_uart(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long div = __raw_readl(S3C2443_CLKDIV1);

	div &= S3C2443_CLKDIV1_UARTDIV_MASK;
	div >>= S3C2443_CLKDIV1_UARTDIV_SHIFT;

	return parent_rate / (div + 1);
}


static int s3c2443_setrate_uart(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);

	rate = s3c2443_roundrate_clksrc16(clk, rate);
	rate = parent_rate / rate;

	clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK;
	clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT;

	__raw_writel(clkdivn, S3C2443_CLKDIV1);
	return 0;
}

static struct clk clk_uart = {
	.name		= "uartclk",
	.id		= -1,
	.parent		= &clk_esysclk,
	.get_rate	= s3c2443_getrate_uart,
	.set_rate	= s3c2443_setrate_uart,
	.round_rate	= s3c2443_roundrate_clksrc16,
};

/* hsspi
 *
 * high-speed spi clock, sourced from esysclk
*/

static unsigned long s3c2443_getrate_hsspi(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long div = __raw_readl(S3C2443_CLKDIV1);

	div &= S3C2443_CLKDIV1_HSSPIDIV_MASK;
	div >>= S3C2443_CLKDIV1_HSSPIDIV_SHIFT;

	return parent_rate / (div + 1);
}


static int s3c2443_setrate_hsspi(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);

	rate = s3c2443_roundrate_clksrc4(clk, rate);
	rate = parent_rate / rate;

	clkdivn &= ~S3C2443_CLKDIV1_HSSPIDIV_MASK;
	clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSSPIDIV_SHIFT;

	__raw_writel(clkdivn, S3C2443_CLKDIV1);
	return 0;
}

static struct clk clk_hsspi = {
	.name		= "hsspi",
	.id		= -1,
	.parent		= &clk_esysclk,
	.ctrlbit	= S3C2443_SCLKCON_HSSPICLK,
	.enable		= s3c2443_clkcon_enable_s,
	.get_rate	= s3c2443_getrate_hsspi,
	.set_rate	= s3c2443_setrate_hsspi,
	.round_rate	= s3c2443_roundrate_clksrc4,
};

/* usbhost
 *
 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
*/

static unsigned long s3c2443_getrate_usbhost(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long div = __raw_readl(S3C2443_CLKDIV1);

	div &= S3C2443_CLKDIV1_USBHOSTDIV_MASK;
	div >>= S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;

	return parent_rate / (div + 1);
}

static int s3c2443_setrate_usbhost(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);

	rate = s3c2443_roundrate_clksrc4(clk, rate);
	rate = parent_rate / rate;

	clkdivn &= ~S3C2443_CLKDIV1_USBHOSTDIV_MASK;
	clkdivn |= (rate - 1) << S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;

	__raw_writel(clkdivn, S3C2443_CLKDIV1);
	return 0;
}

static struct clk clk_usb_bus_host = {
	.name		= "usb-bus-host-parent",
	.id		= -1,
	.parent		= &clk_esysclk,
	.ctrlbit	= S3C2443_SCLKCON_USBHOST,
	.enable		= s3c2443_clkcon_enable_s,
	.get_rate	= s3c2443_getrate_usbhost,
	.set_rate	= s3c2443_setrate_usbhost,
	.round_rate	= s3c2443_roundrate_clksrc4,
};

/* clk_hsmcc_div
 *
 * this clock is sourced from epll, and is fed through a divider,
 * to a mux controlled by sclkcon where either it or a extclk can
 * be fed to the hsmmc block
*/

static unsigned long s3c2443_getrate_hsmmc_div(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long div = __raw_readl(S3C2443_CLKDIV1);

	div &= S3C2443_CLKDIV1_HSMMCDIV_MASK;
	div >>= S3C2443_CLKDIV1_HSMMCDIV_SHIFT;

	return parent_rate / (div + 1);
}

static int s3c2443_setrate_hsmmc_div(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);

	rate = s3c2443_roundrate_clksrc4(clk, rate);
	rate = parent_rate / rate;

	clkdivn &= ~S3C2443_CLKDIV1_HSMMCDIV_MASK;
	clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSMMCDIV_SHIFT;

	__raw_writel(clkdivn, S3C2443_CLKDIV1);
	return 0;
}

static struct clk clk_hsmmc_div = {
	.name		= "hsmmc-div",
	.id		= -1,
	.parent		= &clk_esysclk,
	.get_rate	= s3c2443_getrate_hsmmc_div,
	.set_rate	= s3c2443_setrate_hsmmc_div,
	.round_rate	= s3c2443_roundrate_clksrc4,
};

static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
{
	unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);

	clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
		    S3C2443_SCLKCON_HSMMCCLK_EPLL);

	if (parent == &clk_epll)
		clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
	else if (parent == &clk_ext)
		clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
	else
		return -EINVAL;

	if (clk->usage > 0) {
		__raw_writel(clksrc, S3C2443_SCLKCON);
	}

	clk->parent = parent;
	return 0;
}

static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
{
	return s3c2443_setparent_hsmmc(clk, clk->parent);
}

static struct clk clk_hsmmc = {
	.name		= "hsmmc-if",
	.id		= -1,
	.parent		= &clk_hsmmc_div,
	.enable		= s3c2443_enable_hsmmc,
	.set_parent	= s3c2443_setparent_hsmmc,
};

/* i2s_eplldiv
 *
 * this clock is the output from the i2s divisor of esysclk
*/

static unsigned long s3c2443_getrate_i2s_eplldiv(struct clk *clk)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long div = __raw_readl(S3C2443_CLKDIV1);

	div &= S3C2443_CLKDIV1_I2SDIV_MASK;
	div >>= S3C2443_CLKDIV1_I2SDIV_SHIFT;

	return parent_rate / (div + 1);
}

static int s3c2443_setrate_i2s_eplldiv(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);

	rate = s3c2443_roundrate_clksrc16(clk, rate);
	rate = parent_rate / rate;

	clkdivn &= ~S3C2443_CLKDIV1_I2SDIV_MASK;
	clkdivn |= (rate - 1) << S3C2443_CLKDIV1_I2SDIV_SHIFT;

	__raw_writel(clkdivn, S3C2443_CLKDIV1);
	return 0;
}

static struct clk clk_i2s_eplldiv = {