📄 kconfig
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select CPU_ABRT_EV5T select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_TLB_V4WBI if MMU# XScale Core Version 3config CPU_XSC3 bool depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx default y select CPU_32v5 select CPU_ABRT_EV5T select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_TLB_V4WBI if MMU select IO_36# ARMv6config CPU_V6 bool "Support ARM V6 processor" depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 default y if ARCH_MX3 select CPU_32v6 select CPU_ABRT_EV6 select CPU_CACHE_V6 select CPU_CACHE_VIPT select CPU_CP15_MMU select CPU_HAS_ASID if MMU select CPU_COPY_V6 if MMU select CPU_TLB_V6 if MMU# ARMv6kconfig CPU_32v6K bool "Support ARM V6K processor extensions" if !SMP depends on CPU_V6 default y if SMP && !ARCH_MX3 help Say Y here if your ARMv6 processor supports the 'K' extension. This enables the kernel to use some instructions not present on previous processors, and as such a kernel build with this enabled will not boot on processors with do not support these instructions.# ARMv7config CPU_V7 bool "Support ARM V7 processor" depends on ARCH_INTEGRATOR select CPU_32v6K select CPU_32v7 select CPU_ABRT_EV7 select CPU_CACHE_V7 select CPU_CACHE_VIPT select CPU_CP15_MMU select CPU_HAS_ASID if MMU select CPU_COPY_V6 if MMU select CPU_TLB_V7 if MMU# Figure out what processor architecture version we should be using.# This defines the compiler instruction set which depends on the machine type.config CPU_32v3 bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMPconfig CPU_32v4 bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMPconfig CPU_32v4T bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMPconfig CPU_32v5 bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMPconfig CPU_32v6 bool select TLS_REG_EMUL if !CPU_32v6K && !MMUconfig CPU_32v7 bool# The abort modelconfig CPU_ABRT_NOMMU boolconfig CPU_ABRT_EV4 boolconfig CPU_ABRT_EV4T boolconfig CPU_ABRT_LV4T boolconfig CPU_ABRT_EV5T boolconfig CPU_ABRT_EV5TJ boolconfig CPU_ABRT_EV6 boolconfig CPU_ABRT_EV7 bool# The cache modelconfig CPU_CACHE_V3 boolconfig CPU_CACHE_V4 boolconfig CPU_CACHE_V4WT boolconfig CPU_CACHE_V4WB boolconfig CPU_CACHE_V6 boolconfig CPU_CACHE_V7 boolconfig CPU_CACHE_VIVT boolconfig CPU_CACHE_VIPT boolif MMU# The copy-page modelconfig CPU_COPY_V3 boolconfig CPU_COPY_V4WT boolconfig CPU_COPY_V4WB boolconfig CPU_COPY_V6 bool# This selects the TLB modelconfig CPU_TLB_V3 bool help ARM Architecture Version 3 TLB.config CPU_TLB_V4WT bool help ARM Architecture Version 4 TLB with writethrough cache.config CPU_TLB_V4WB bool help ARM Architecture Version 4 TLB with writeback cache.config CPU_TLB_V4WBI bool help ARM Architecture Version 4 TLB with writeback cache and invalidate instruction cache entry.config CPU_TLB_V6 boolconfig CPU_TLB_V7 boolendifconfig CPU_HAS_ASID bool help This indicates whether the CPU has the ASID register; used to tag TLB and possibly cache entries.config CPU_CP15 bool help Processor has the CP15 register.config CPU_CP15_MMU bool select CPU_CP15 help Processor has the CP15 register, which has MMU related registers.config CPU_CP15_MPU bool select CPU_CP15 help Processor has the CP15 register, which has MPU related registers.## CPU supports 36-bit I/O#config IO_36 boolcomment "Processor Features"config ARM_THUMB bool "Support Thumb user binaries" depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 default y help Say Y if you want to include kernel support for running user space Thumb binaries. The Thumb instruction set is a compressed form of the standard ARM instruction set resulting in smaller binaries at the expense of slightly less efficient code. If you don't know what this all is, saying Y is a safe choice.config CPU_BIG_ENDIAN bool "Build big-endian kernel" depends on ARCH_SUPPORTS_BIG_ENDIAN help Say Y if you plan on running a kernel in big-endian mode. Note that your board must be properly built and your board port must properly enable any big-endian related features of your chipset/board/processor.config CPU_HIGH_VECTOR depends on !MMU && CPU_CP15 && !CPU_ARM740T bool "Select the High exception vector" default n help Say Y here to select high exception vector(0xFFFF0000~). The exception vector can be vary depending on the platform design in nommu mode. If your platform needs to select high exception vector, say Y. Otherwise or if you are unsure, say N, and the low exception vector (0x00000000~) will be used.config CPU_ICACHE_DISABLE bool "Disable I-Cache (I-bit)" depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) help Say Y here to disable the processor instruction cache. Unless you have a reason not to or are unsure, say N.config CPU_DCACHE_DISABLE bool "Disable D-Cache (C-bit)" depends on CPU_CP15 help Say Y here to disable the processor data cache. Unless you have a reason not to or are unsure, say N.config CPU_DCACHE_SIZE hex depends on CPU_ARM740T || CPU_ARM946E default 0x00001000 if CPU_ARM740T default 0x00002000 # default size for ARM946E-S help Some cores are synthesizable to have various sized cache. For ARM946E-S case, it can vary from 0KB to 1MB. To support such cache operations, it is efficient to know the size before compile time. If your SoC is configured to have a different size, define the value here with proper conditions.config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you specifically require this or are unsure, say N.config CPU_CACHE_ROUND_ROBIN bool "Round robin I and D cache replacement algorithm" depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) help Say Y here to use the predictable round-robin cache replacement policy. Unless you specifically require this or are unsure, say N.config CPU_BPREDICT_DISABLE bool "Disable branch prediction" depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 help Say Y here to disable branch prediction. If unsure, say N.config TLS_REG_EMUL bool help An SMP system using a pre-ARMv6 processor (there are apparently a few prototypes like that in existence) and therefore access to that required register must be emulated.config HAS_TLS_REG bool depends on !TLS_REG_EMUL default y if SMP || CPU_32v7 help This selects support for the CP15 thread register. It is defined to be available on some ARMv6 processors (including all SMP capable ARMv6's) or later processors. User space may assume directly accessing that register and always obtain the expected value only on ARMv7 and above.config NEEDS_SYSCALL_FOR_CMPXCHG bool help SMP on a pre-ARMv6 processor? Well OK then. Forget about fast user space cmpxchg support. It is just not possible.config OUTER_CACHE bool default nconfig CACHE_L2X0 bool select OUTER_CACHE⌨️ 快捷键说明
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