setup.c

linux 内核源代码

	case PSR_IMPLE_FR401:
		cpu_series	= "fr400";
		cpu_core	= "fr401";
		pdm_suspend_mode = HSR0_PDM_PLL_RUN;

		switch (PSR_VERSION(psr)) {
		case PSR_VERSION_FR401_MB93401:
			cpu_silicon	= "mb93401";
			cpu_system	= __frv_mb93091_cb10;
			clock_cmodes	= clock_cmodes_fr401_fr403;
			clock_doubled	= 1;
			break;
		case PSR_VERSION_FR401_MB93401A:
			cpu_silicon	= "mb93401/A";
			cpu_system	= __frv_mb93091_cb11;
			clock_cmodes	= clock_cmodes_fr401_fr403;
			break;
		case PSR_VERSION_FR401_MB93403:
			cpu_silicon	= "mb93403";
#ifndef CONFIG_MB93093_PDK
			cpu_system	= __frv_mb93091_cb30;
#else
			cpu_system	= __frv_mb93093;
#endif
			clock_cmodes	= clock_cmodes_fr401_fr403;
			break;
		default:
			break;
		}
		break;

	case PSR_IMPLE_FR405:
		cpu_series	= "fr400";
		cpu_core	= "fr405";
		pdm_suspend_mode = HSR0_PDM_PLL_STOP;

		switch (PSR_VERSION(psr)) {
		case PSR_VERSION_FR405_MB93405:
			cpu_silicon	= "mb93405";
			cpu_system	= __frv_mb93091_cb60;
			clock_cmodes	= clock_cmodes_fr405;
#ifdef CONFIG_PM
			clock_bits_settable |= CLOCK_BIT_CMODE;
			clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
#endif

			/* the FPGA on the CB70 has extra registers
			 * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
			 *   how we tell the difference between it and a CB60
			 */
			if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
				cpu_system = __frv_mb93091_cb70;
			break;
		default:
			break;
		}
		break;

	case PSR_IMPLE_FR451:
		cpu_series	= "fr450";
		cpu_core	= "fr451";
		pdm_suspend_mode = HSR0_PDM_PLL_STOP;
#ifdef CONFIG_PM
		clock_bits_settable |= CLOCK_BIT_CMODE;
		clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
#endif
		switch (PSR_VERSION(psr)) {
		case PSR_VERSION_FR451_MB93451:
			cpu_silicon	= "mb93451";
			cpu_mmu		= "Prot, SAT, xSAT, DAT";
			cpu_system	= __frv_mb93091_cb451;
			clock_cmodes	= clock_cmodes_fr405;
			break;
		default:
			break;
		}
		break;

	case PSR_IMPLE_FR501:
		cpu_series	= "fr500";
		cpu_core	= "fr501";
		pdm_suspend_mode = HSR0_PDM_PLL_STOP;

		switch (PSR_VERSION(psr)) {
		case PSR_VERSION_FR501_MB93501:  cpu_silicon = "mb93501";   break;
		case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
		default:
			break;
		}
		break;

	case PSR_IMPLE_FR551:
		cpu_series	= "fr550";
		cpu_core	= "fr551";
		pdm_suspend_mode = HSR0_PDM_PLL_RUN;

		switch (PSR_VERSION(psr)) {
		case PSR_VERSION_FR551_MB93555:
			cpu_silicon	= "mb93555";
			cpu_mmu		= "Prot, SAT";
			cpu_system	= __frv_mb93091_cb41;
			clock_cmodes	= clock_cmodes_fr555;
			clock_doubled	= 1;
			break;
		default:
			break;
		}
		break;

	default:
		break;
	}

	printk("- Series:%s CPU:%s Silicon:%s\n",
	       cpu_series, cpu_core, cpu_silicon);

#ifdef CONFIG_MB93091_VDK
	detect_mb93091();
#endif

#if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
	cpu_board2 = __frv_mb93493;
#endif

} /* end determine_cpu() */

/*****************************************************************************/
/*
 * calculate the bus clock speed
 */
void __pminit determine_clocks(int verbose)
{
	const struct clock_cmode *mode, *tmode;
	unsigned long clkc, psr, quot;

	clkc = __get_CLKC();
	psr = __get_PSR();

	clock_p0_current = !!(clkc & CLKC_P0);
	clock_cm_current = clkc & CLKC_CM;
	clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;

	if (verbose)
		printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);

	/* the CB70 has some alternative ways of setting the clock speed through switches accessed
	 * through the FPGA.  */
	if (cpu_system == __frv_mb93091_cb70) {
		unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;

		if (clkswr & 0x1000)
			__clkin_clock_speed_HZ = 60000000UL;
		else
			__clkin_clock_speed_HZ =
				((clkswr >> 8) & 0xf) * 10000000 +
				((clkswr >> 4) & 0xf) * 1000000 +
				((clkswr     ) & 0xf) * 100000;
	}
	/* the FR451 is currently fixed at 24MHz */
	else if (cpu_system == __frv_mb93091_cb451) {
		//__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
		unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;

		if (clkswr & 0x1000)
			__clkin_clock_speed_HZ = 60000000UL;
		else
			__clkin_clock_speed_HZ =
				((clkswr >> 8) & 0xf) * 10000000 +
				((clkswr >> 4) & 0xf) * 1000000 +
				((clkswr     ) & 0xf) * 100000;
	}
	/* otherwise determine the clockspeed from VDK or other registers */
	else {
		__clkin_clock_speed_HZ = __get_CLKIN();
	}

	/* look up the appropriate clock relationships table entry */
	mode = &undef_clock_cmode;
	if (clock_cmodes) {
		tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
		if (tmode->xbus)
			mode = tmode;
	}

#define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))

	if (clock_doubled)
		__clkin_clock_speed_HZ <<= 1;

	__ext_bus_clock_speed_HZ	= CLOCK(__clkin_clock_speed_HZ, mode->xbus);
	__sdram_clock_speed_HZ		= CLOCK(__clkin_clock_speed_HZ, mode->sdram);
	__dsu_clock_speed_HZ		= CLOCK(__clkin_clock_speed_HZ, mode->dsu);

	switch (clkc & CLKC_CM) {
	case 0: /* High */
		__core_bus_clock_speed_HZ	= CLOCK(__clkin_clock_speed_HZ, mode->corebus);
		__core_clock_speed_HZ		= CLOCK(__clkin_clock_speed_HZ, mode->core);
		break;
	case 1: /* Medium */
		__core_bus_clock_speed_HZ	= CLOCK(__clkin_clock_speed_HZ, mode->sdram);
		__core_clock_speed_HZ		= CLOCK(__clkin_clock_speed_HZ, mode->sdram);
		break;
	case 2: /* Low; not supported */
	case 3: /* UNDEF */
		printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
		panic("Bye");
	}

	__res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
	if (clkc & CLKC_P0)
		__res_bus_clock_speed_HZ >>= 1;

	if (verbose) {
		printk("CLKIN: %lu.%3.3luMHz\n",
		       __clkin_clock_speed_HZ / 1000000,
		       (__clkin_clock_speed_HZ / 1000) % 1000);

		printk("CLKS:"
		       " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
		       __ext_bus_clock_speed_HZ / 1000000,
		       __res_bus_clock_speed_HZ / 1000000,
		       __sdram_clock_speed_HZ / 1000000,
		       __core_bus_clock_speed_HZ / 1000000,
		       __core_clock_speed_HZ / 1000000,
		       __dsu_clock_speed_HZ / 1000000
		       );
	}

	/* calculate the number of __delay() loop iterations per sec (2 insn loop) */
	__delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);

	/* set the serial prescaler */
	__serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
	quot = 1;
	while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
		quot += 1;

	/* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
	 * - we have to be careful - dividing too much can mean we can't get 115200 baud
	 */
	if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
		quot <<= 1;

	__serial_clock_speed_HZ /= quot;
	__frv_uart0.uartclk = __serial_clock_speed_HZ;
	__frv_uart1.uartclk = __serial_clock_speed_HZ;

	if (verbose)
		printk("      uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);

	while (!(__get_UART0_LSR() & UART_LSR_TEMT))
		continue;

	while (!(__get_UART1_LSR() & UART_LSR_TEMT))
		continue;

	__set_UCPVR(quot);
	__set_UCPSR(0);
} /* end determine_clocks() */

/*****************************************************************************/
/*
 * reserve some DMA consistent memory
 */
#ifdef CONFIG_RESERVE_DMA_COHERENT
static void __init reserve_dma_coherent(void)
{
	unsigned long ampr;

	/* find the first non-kernel memory tile and steal it */
#define __steal_AMPR(r)						\
	if (__get_DAMPR(r) & xAMPRx_V) {			\
		ampr = __get_DAMPR(r);				\
		__set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C);	\
		__set_IAMPR(r, 0);				\
		goto found;					\
	}

	__steal_AMPR(1);
	__steal_AMPR(2);
	__steal_AMPR(3);
	__steal_AMPR(4);
	__steal_AMPR(5);
	__steal_AMPR(6);

	if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
		__steal_AMPR(7);
		__steal_AMPR(8);
		__steal_AMPR(9);
		__steal_AMPR(10);
		__steal_AMPR(11);
		__steal_AMPR(12);
		__steal_AMPR(13);
		__steal_AMPR(14);
	}

	/* unable to grant any DMA consistent memory */
	printk("No DMA consistent memory reserved\n");
	return;

 found:
	dma_coherent_mem_start = ampr & xAMPRx_PPFN;
	ampr &= xAMPRx_SS;
	ampr >>= 4;
	ampr = 1 << (ampr - 3 + 20);
	dma_coherent_mem_end = dma_coherent_mem_start + ampr;

	printk("DMA consistent memory reserved %lx-%lx\n",
	       dma_coherent_mem_start, dma_coherent_mem_end);

} /* end reserve_dma_coherent() */
#endif

/*****************************************************************************/
/*
 * calibrate the delay loop
 */
void __init calibrate_delay(void)
{
	loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);

	printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
	       loops_per_jiffy / (500000 / HZ),
	       (loops_per_jiffy / (5000 / HZ)) % 100);

} /* end calibrate_delay() */

/*****************************************************************************/
/*
 * look through the command line for some things we need to know immediately
 */
static void __init parse_cmdline_early(char *cmdline)
{
	if (!cmdline)
		return;

	while (*cmdline) {
		if (*cmdline == ' ')
			cmdline++;

		/* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
		 * out from the SDRAM controller mask register
		 */
		if (!memcmp(cmdline, "mem=", 4)) {
			unsigned long long mem_size;

			mem_size = memparse(cmdline + 4, &cmdline);
			memory_end = memory_start + mem_size;
		}

		while (*cmdline && *cmdline != ' ')
			cmdline++;
	}

} /* end parse_cmdline_early() */

/*****************************************************************************/
/*
 *
 */
void __init setup_arch(char **cmdline_p)
{
#ifdef CONFIG_MMU
	printk("Linux FR-V port done by Red Hat Inc <[e-mail]>\n");
#else
	printk("uClinux FR-V port done by Red Hat Inc <[e-mail]>\n");
#endif

	memcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE);

	determine_cpu();
	determine_clocks(1);

	/* For printk-directly-beats-on-serial-hardware hack */
	console_set_baud(115200);
#ifdef CONFIG_GDBSTUB
	gdbstub_set_baud(115200);
#endif

#ifdef CONFIG_RESERVE_DMA_COHERENT
	reserve_dma_coherent();
#endif
	dump_memory_map();

#ifdef CONFIG_MB93090_MB00
	if (mb93090_mb00_detected)
		mb93090_display();
#endif

	/* register those serial ports that are available */
#ifdef CONFIG_FRV_ONCPU_SERIAL
#ifndef CONFIG_GDBSTUB_UART0
	__reg(UART0_BASE + UART_IER * 8) = 0;