irq.c

linux 内核源代码

static struct irq_chip either_edge_irq_type = {
	.name		= "Au1000 Rise or Fall Edge",
	.ack		= mask_and_ack_either_edge_irq,
	.mask		= local_disable_irq,
	.mask_ack	= mask_and_ack_either_edge_irq,
	.unmask		= local_enable_irq,
	.end		= end_irq,
};

static struct irq_chip level_irq_type = {
	.name		= "Au1000 Level",
	.ack		= mask_and_ack_level_irq,
	.mask		= local_disable_irq,
	.mask_ack	= mask_and_ack_level_irq,
	.unmask		= local_enable_irq,
	.end		= end_irq,
};

static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req)
{
	unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;

	if (irq_nr > AU1000_MAX_INTR)
		return;

	/* Config2[n], Config1[n], Config0[n] */
	if (bit >= 32) {
		switch (type) {
		case INTC_INT_RISE_EDGE: /* 0:0:1 */
			au_writel(1 << (bit - 32), IC1_CFG2CLR);
			au_writel(1 << (bit - 32), IC1_CFG1CLR);
			au_writel(1 << (bit - 32), IC1_CFG0SET);
			set_irq_chip(irq_nr, &rise_edge_irq_type);
			break;
		case INTC_INT_FALL_EDGE: /* 0:1:0 */
			au_writel(1 << (bit - 32), IC1_CFG2CLR);
			au_writel(1 << (bit - 32), IC1_CFG1SET);
			au_writel(1 << (bit - 32), IC1_CFG0CLR);
			set_irq_chip(irq_nr, &fall_edge_irq_type);
			break;
		case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
			au_writel(1 << (bit - 32), IC1_CFG2CLR);
			au_writel(1 << (bit - 32), IC1_CFG1SET);
			au_writel(1 << (bit - 32), IC1_CFG0SET);
			set_irq_chip(irq_nr, &either_edge_irq_type);
			break;
		case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
			au_writel(1 << (bit - 32), IC1_CFG2SET);
			au_writel(1 << (bit - 32), IC1_CFG1CLR);
			au_writel(1 << (bit - 32), IC1_CFG0SET);
			set_irq_chip(irq_nr, &level_irq_type);
			break;
		case INTC_INT_LOW_LEVEL: /* 1:1:0 */
			au_writel(1 << (bit - 32), IC1_CFG2SET);
			au_writel(1 << (bit - 32), IC1_CFG1SET);
			au_writel(1 << (bit - 32), IC1_CFG0CLR);
			set_irq_chip(irq_nr, &level_irq_type);
			break;
		case INTC_INT_DISABLED: /* 0:0:0 */
			au_writel(1 << (bit - 32), IC1_CFG0CLR);
			au_writel(1 << (bit - 32), IC1_CFG1CLR);
			au_writel(1 << (bit - 32), IC1_CFG2CLR);
			break;
		default: /* disable the interrupt */
			printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
			       type, irq_nr);
			au_writel(1 << (bit - 32), IC1_CFG0CLR);
			au_writel(1 << (bit - 32), IC1_CFG1CLR);
			au_writel(1 << (bit - 32), IC1_CFG2CLR);
			return;
		}
		if (int_req) /* assign to interrupt request 1 */
			au_writel(1 << (bit - 32), IC1_ASSIGNCLR);
		else	     /* assign to interrupt request 0 */
			au_writel(1 << (bit - 32), IC1_ASSIGNSET);
		au_writel(1 << (bit - 32), IC1_SRCSET);
		au_writel(1 << (bit - 32), IC1_MASKCLR);
		au_writel(1 << (bit - 32), IC1_WAKECLR);
	} else {
		switch (type) {
		case INTC_INT_RISE_EDGE: /* 0:0:1 */
			au_writel(1 << bit, IC0_CFG2CLR);
			au_writel(1 << bit, IC0_CFG1CLR);
			au_writel(1 << bit, IC0_CFG0SET);
			set_irq_chip(irq_nr, &rise_edge_irq_type);
			break;
		case INTC_INT_FALL_EDGE: /* 0:1:0 */
			au_writel(1 << bit, IC0_CFG2CLR);
			au_writel(1 << bit, IC0_CFG1SET);
			au_writel(1 << bit, IC0_CFG0CLR);
			set_irq_chip(irq_nr, &fall_edge_irq_type);
			break;
		case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
			au_writel(1 << bit, IC0_CFG2CLR);
			au_writel(1 << bit, IC0_CFG1SET);
			au_writel(1 << bit, IC0_CFG0SET);
			set_irq_chip(irq_nr, &either_edge_irq_type);
			break;
		case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
			au_writel(1 << bit, IC0_CFG2SET);
			au_writel(1 << bit, IC0_CFG1CLR);
			au_writel(1 << bit, IC0_CFG0SET);
			set_irq_chip(irq_nr, &level_irq_type);
			break;
		case INTC_INT_LOW_LEVEL: /* 1:1:0 */
			au_writel(1 << bit, IC0_CFG2SET);
			au_writel(1 << bit, IC0_CFG1SET);
			au_writel(1 << bit, IC0_CFG0CLR);
			set_irq_chip(irq_nr, &level_irq_type);
			break;
		case INTC_INT_DISABLED: /* 0:0:0 */
			au_writel(1 << bit, IC0_CFG0CLR);
			au_writel(1 << bit, IC0_CFG1CLR);
			au_writel(1 << bit, IC0_CFG2CLR);
			break;
		default: /* disable the interrupt */
			printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
			       type, irq_nr);
			au_writel(1 << bit, IC0_CFG0CLR);
			au_writel(1 << bit, IC0_CFG1CLR);
			au_writel(1 << bit, IC0_CFG2CLR);
			return;
		}
		if (int_req) /* assign to interrupt request 1 */
			au_writel(1 << bit, IC0_ASSIGNCLR);
		else	     /* assign to interrupt request 0 */
			au_writel(1 << bit, IC0_ASSIGNSET);
		au_writel(1 << bit, IC0_SRCSET);
		au_writel(1 << bit, IC0_MASKCLR);
		au_writel(1 << bit, IC0_WAKECLR);
	}
	au_sync();
}

/*
 * Interrupts are nested. Even if an interrupt handler is registered
 * as "fast", we might get another interrupt before we return from
 * intcX_reqX_irqdispatch().
 */

static void intc0_req0_irqdispatch(void)
{
	static unsigned long intc0_req0;
	unsigned int bit;

	intc0_req0 |= au_readl(IC0_REQ0INT);

	if (!intc0_req0)
		return;

#ifdef AU1000_USB_DEV_REQ_INT
	/*
	 * Because of the tight timing of SETUP token to reply
	 * transactions, the USB devices-side packet complete
	 * interrupt needs the highest priority.
	 */
	if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) {
		intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT);
		do_IRQ(AU1000_USB_DEV_REQ_INT);
		return;
	}
#endif
	bit = __ffs(intc0_req0);
	intc0_req0 &= ~(1 << bit);
	do_IRQ(AU1000_INTC0_INT_BASE + bit);
}


static void intc0_req1_irqdispatch(void)
{
	static unsigned long intc0_req1;
	unsigned int bit;

	intc0_req1 |= au_readl(IC0_REQ1INT);

	if (!intc0_req1)
		return;

	bit = __ffs(intc0_req1);
	intc0_req1 &= ~(1 << bit);
	do_IRQ(AU1000_INTC0_INT_BASE + bit);
}


/*
 * Interrupt Controller 1:
 * interrupts 32 - 63
 */
static void intc1_req0_irqdispatch(void)
{
	static unsigned long intc1_req0;
	unsigned int bit;

	intc1_req0 |= au_readl(IC1_REQ0INT);

	if (!intc1_req0)
		return;

	bit = __ffs(intc1_req0);
	intc1_req0 &= ~(1 << bit);
	do_IRQ(AU1000_INTC1_INT_BASE + bit);
}


static void intc1_req1_irqdispatch(void)
{
	static unsigned long intc1_req1;
	unsigned int bit;

	intc1_req1 |= au_readl(IC1_REQ1INT);

	if (!intc1_req1)
		return;

	bit = __ffs(intc1_req1);
	intc1_req1 &= ~(1 << bit);
	do_IRQ(AU1000_INTC1_INT_BASE + bit);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause();

	if (pending & CAUSEF_IP7)
		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
	else if (pending & CAUSEF_IP2)
		intc0_req0_irqdispatch();
	else if (pending & CAUSEF_IP3)
		intc0_req1_irqdispatch();
	else if (pending & CAUSEF_IP4)
		intc1_req0_irqdispatch();
	else if (pending  & CAUSEF_IP5)
		intc1_req1_irqdispatch();
	else
		spurious_interrupt();
}

void __init arch_init_irq(void)
{
	int i;
	struct au1xxx_irqmap *imp;
	extern struct au1xxx_irqmap au1xxx_irq_map[];
	extern struct au1xxx_irqmap au1xxx_ic0_map[];
	extern int au1xxx_nr_irqs;
	extern int au1xxx_ic0_nr_irqs;

	/*
	 * Initialize interrupt controllers to a safe state.
	 */
	au_writel(0xffffffff, IC0_CFG0CLR);
	au_writel(0xffffffff, IC0_CFG1CLR);
	au_writel(0xffffffff, IC0_CFG2CLR);
	au_writel(0xffffffff, IC0_MASKCLR);
	au_writel(0xffffffff, IC0_ASSIGNSET);
	au_writel(0xffffffff, IC0_WAKECLR);
	au_writel(0xffffffff, IC0_SRCSET);
	au_writel(0xffffffff, IC0_FALLINGCLR);
	au_writel(0xffffffff, IC0_RISINGCLR);
	au_writel(0x00000000, IC0_TESTBIT);

	au_writel(0xffffffff, IC1_CFG0CLR);
	au_writel(0xffffffff, IC1_CFG1CLR);
	au_writel(0xffffffff, IC1_CFG2CLR);
	au_writel(0xffffffff, IC1_MASKCLR);
	au_writel(0xffffffff, IC1_ASSIGNSET);
	au_writel(0xffffffff, IC1_WAKECLR);
	au_writel(0xffffffff, IC1_SRCSET);
	au_writel(0xffffffff, IC1_FALLINGCLR);
	au_writel(0xffffffff, IC1_RISINGCLR);
	au_writel(0x00000000, IC1_TESTBIT);

	mips_cpu_irq_init();

	/*
	 * Initialize IC0, which is fixed per processor.
	 */
	imp = au1xxx_ic0_map;
	for (i = 0; i < au1xxx_ic0_nr_irqs; i++) {
		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
		imp++;
	}

	/*
	 * Now set up the irq mapping for the board.
	 */
	imp = au1xxx_irq_map;
	for (i = 0; i < au1xxx_nr_irqs; i++) {
		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
		imp++;
	}

	set_c0_status(ALLINTS);

	/* Board specific IRQ initialization.
	*/
	if (board_init_irq)
		board_init_irq();
}