toshiba_rbtx4927_setup.c

linux 内核源代码

		     (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
		     (!(tx4927_ccfgptr->
			ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
		     "Internal");
		called = 1;
	}
	printk("%s PCIC --%s PCICLK:", toshiba_name,
	       (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
	if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
		int pciclk = 0;
		if (mips_machtype == MACH_TOSHIBA_RBTX4937)
			switch ((unsigned long) tx4927_ccfgptr->
				ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
			case TX4937_CCFG_PCIDIVMODE_4:
				pciclk = tx4927_cpu_clock / 4;
				break;
			case TX4937_CCFG_PCIDIVMODE_4_5:
				pciclk = tx4927_cpu_clock * 2 / 9;
				break;
			case TX4937_CCFG_PCIDIVMODE_5:
				pciclk = tx4927_cpu_clock / 5;
				break;
			case TX4937_CCFG_PCIDIVMODE_5_5:
				pciclk = tx4927_cpu_clock * 2 / 11;
				break;
			case TX4937_CCFG_PCIDIVMODE_8:
				pciclk = tx4927_cpu_clock / 8;
				break;
			case TX4937_CCFG_PCIDIVMODE_9:
				pciclk = tx4927_cpu_clock / 9;
				break;
			case TX4937_CCFG_PCIDIVMODE_10:
				pciclk = tx4927_cpu_clock / 10;
				break;
			case TX4937_CCFG_PCIDIVMODE_11:
				pciclk = tx4927_cpu_clock / 11;
				break;
			}

		else
			switch ((unsigned long) tx4927_ccfgptr->
				ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
			case TX4927_CCFG_PCIDIVMODE_2_5:
				pciclk = tx4927_cpu_clock * 2 / 5;
				break;
			case TX4927_CCFG_PCIDIVMODE_3:
				pciclk = tx4927_cpu_clock / 3;
				break;
			case TX4927_CCFG_PCIDIVMODE_5:
				pciclk = tx4927_cpu_clock / 5;
				break;
			case TX4927_CCFG_PCIDIVMODE_6:
				pciclk = tx4927_cpu_clock / 6;
				break;
			}

		printk("Internal(%dMHz)", pciclk / 1000000);
	} else {
		int pciclk = 0;
		int pciclk_setting = *tx4927_pci_clk_ptr;
		switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
		case TX4927_PCI_CLK_33:
			pciclk = 33333333;
			break;
		case TX4927_PCI_CLK_25:
			pciclk = 25000000;
			break;
		case TX4927_PCI_CLK_66:
			pciclk = 66666666;
			break;
		case TX4927_PCI_CLK_50:
			pciclk = 50000000;
			break;
		}
		printk("External(%dMHz)", pciclk / 1000000);
	}
	printk("\n");



	/* GB->PCI mappings */
	tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
	tx4927_pcicptr->g2piogbase = mips_pci_io_base |
#ifdef __BIG_ENDIAN
	    TX4927_PCIC_G2PIOGBASE_ECHG
#else
	    TX4927_PCIC_G2PIOGBASE_BSDIS
#endif
	    ;

	tx4927_pcicptr->g2piopbase = 0;

	tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
	tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
#ifdef __BIG_ENDIAN
	    TX4927_PCIC_G2PMnGBASE_ECHG
#else
	    TX4927_PCIC_G2PMnGBASE_BSDIS
#endif
	    ;
	tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;

	tx4927_pcicptr->g2pmmask[1] = 0;
	tx4927_pcicptr->g2pmgbase[1] = 0;
	tx4927_pcicptr->g2pmpbase[1] = 0;
	tx4927_pcicptr->g2pmmask[2] = 0;
	tx4927_pcicptr->g2pmgbase[2] = 0;
	tx4927_pcicptr->g2pmpbase[2] = 0;


	/* PCI->GB mappings (I/O 256B) */
	tx4927_pcicptr->p2giopbase = 0;	/* 256B */

	/* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
	tx4927_pcicptr->p2gm0plbase = 0;
	tx4927_pcicptr->p2gm0pubase = 0;
	tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
#ifdef __BIG_ENDIAN
	    TX4927_PCIC_P2GMnGBASE_TECHG
#else
	    TX4927_PCIC_P2GMnGBASE_TBSDIS
#endif
	    ;

	/* PCI->GB mappings (MEM 16MB) -not used */
	tx4927_pcicptr->p2gm1plbase = 0xffffffff;
	tx4927_pcicptr->p2gm1pubase = 0xffffffff;
	tx4927_pcicptr->p2gmgbase[1] = 0;

	/* PCI->GB mappings (MEM 1MB) -not used */
	tx4927_pcicptr->p2gm2pbase = 0xffffffff;
	tx4927_pcicptr->p2gmgbase[2] = 0;


	/* Enable Initiator Memory 0 Space, I/O Space, Config */
	tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
	tx4927_pcicptr->pciccfg |=
	    TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
	    TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;


	/* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
	tx4927_pcicptr->pcicfg1 = 0;

	if (tx4927_pcic_trdyto >= 0) {
		tx4927_pcicptr->g2ptocnt &= ~0xff;
		tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
	}

	/* Clear All Local Bus Status */
	tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
	/* Enable All Local Bus Interrupts */
	tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
	/* Clear All Initiator Status */
	tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
	/* Enable All Initiator Interrupts */
	tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
	/* Clear All PCI Status Error */
	tx4927_pcicptr->pcistatus =
	    (tx4927_pcicptr->pcistatus & 0x0000ffff) |
	    (TX4927_PCIC_PCISTATUS_ALL << 16);
	/* Enable All PCI Status Error Interrupts */
	tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;

	/* PCIC Int => IRC IRQ16 */
	tx4927_pcicptr->pcicfg2 =
	    (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;

	if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
		/* XXX */
	} else {
		/* Reset Bus Arbiter */
		tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
		/* Enable Bus Arbiter */
		tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
	}

	tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
	    PCI_COMMAND_MEMORY |
	    PCI_COMMAND_PARITY | PCI_COMMAND_SERR;

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       ":pci setup complete:\n");
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
}

#endif /* CONFIG_PCI */

static void __noreturn wait_forever(void)
{
	while (1)
		if (cpu_wait)
			(*cpu_wait)();
}

void toshiba_rbtx4927_restart(char *command)
{
	printk(KERN_NOTICE "System Rebooting...\n");

	/* enable the s/w reset register */
	writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);

	/* wait for enable to be seen */
	while ((readb(RBTX4927_SW_RESET_ENABLE) &
		RBTX4927_SW_RESET_ENABLE_SET) == 0x00);

	/* do a s/w reset */
	writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);

	/* do something passive while waiting for reset */
	local_irq_disable();
	wait_forever();
	/* no return */
}


void toshiba_rbtx4927_halt(void)
{
	printk(KERN_NOTICE "System Halted\n");
	local_irq_disable();
	wait_forever();
	/* no return */
}

void toshiba_rbtx4927_power_off(void)
{
	toshiba_rbtx4927_halt();
	/* no return */
}

void __init toshiba_rbtx4927_setup(void)
{
	int i;
	u32 cp0_config;
	char *argptr;

	printk("CPU is %s\n", toshiba_name);

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       "-\n");

	/* f/w leaves this on at startup */
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":Clearing STO_ERL.\n");
	clear_c0_status(ST0_ERL);

	/* enable caches -- HCP5 does this, pmon does not */
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
	cp0_config = read_c0_config();
	cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
	write_c0_config(cp0_config);

#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
	{
		extern void dump_cp0(char *);
		dump_cp0("toshiba_rbtx4927_early_fw_fixup");
	}
#endif

	set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":mips_io_port_base=0x%08lx\n",
				       mips_io_port_base);

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":Resource\n");
	ioport_resource.end = 0xffffffff;
	iomem_resource.end = 0xffffffff;

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
				       ":ResetRoutines\n");
	_machine_restart = toshiba_rbtx4927_restart;
	_machine_halt = toshiba_rbtx4927_halt;
	pm_power_off = toshiba_rbtx4927_power_off;

	for (i = 0; i < TX4927_NR_TMR; i++)
		txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);

#ifdef CONFIG_PCI

	/* PCIC */
	/*
	   * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
	   *
	   * For TX4927:
	   * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
	   * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
	   * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
	   * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
	   * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
	   * i.e. S9[3]: ON (83MHz), OFF (100MHz)
	   *
	   * For TX4937:
	   * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
	   * PCIDIVMODE[10] is 0.
	   * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
	   * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
	   * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
	   * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
	   * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
	   * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
	   *
	 */
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
				       "ccfg is %lx, PCIDIVMODE is %x\n",
				       (unsigned long) tx4927_ccfgptr->ccfg,
				       (unsigned long) tx4927_ccfgptr->ccfg &
				       (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
					TX4937_CCFG_PCIDIVMODE_MASK :
					TX4927_CCFG_PCIDIVMODE_MASK));

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
				       "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
				       (unsigned long) tx4927_ccfgptr->
				       ccfg & TX4927_CCFG_PCI66,
				       (unsigned long) tx4927_ccfgptr->
				       ccfg & TX4927_CCFG_PCIMIDE,
				       (unsigned long) tx4927_ccfgptr->
				       ccfg & TX4927_CCFG_PCIXARB);

	if (mips_machtype == MACH_TOSHIBA_RBTX4937)
		switch ((unsigned long)tx4927_ccfgptr->
			ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
		case TX4937_CCFG_PCIDIVMODE_8:
		case TX4937_CCFG_PCIDIVMODE_4:
			tx4927_cpu_clock = 266666666;	/* 266MHz */
			break;
		case TX4937_CCFG_PCIDIVMODE_9:
		case TX4937_CCFG_PCIDIVMODE_4_5:
			tx4927_cpu_clock = 300000000;	/* 300MHz */
			break;
		default:
			tx4927_cpu_clock = 333333333;	/* 333MHz */
		}
	else
		switch ((unsigned long)tx4927_ccfgptr->
			ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
		case TX4927_CCFG_PCIDIVMODE_2_5:
		case TX4927_CCFG_PCIDIVMODE_5:
			tx4927_cpu_clock = 166666666;	/* 166MHz */
			break;
		default:
			tx4927_cpu_clock = 200000000;	/* 200MHz */
		}

	/* CCFG */
	/* enable Timeout BusError */
	if (tx4927_ccfg_toeon)
		tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;

	tx4927_pci_setup();
	if (tx4927_using_backplane == 1)
		printk("backplane board IS installed\n");
	else
		printk("No Backplane \n");

	/* this is on ISA bus behind PCI bus, so need PCI up first */
#ifdef CONFIG_TOSHIBA_FPCIB0
	{
		if (tx4927_using_backplane) {
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":fpcibo=yes\n");

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":smsc_fdc37m81x_init()\n");
			smsc_fdc37m81x_init(0x3f0);

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":smsc_fdc37m81x_config_beg()\n");
			smsc_fdc37m81x_config_beg();

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":smsc_fdc37m81x_config_set(KBD)\n");
			smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
						  SMSC_FDC37M81X_KBD);
			smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
			smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
			smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
						  1);

			smsc_fdc37m81x_config_end();
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":smsc_fdc37m81x_config_end()\n");
		} else {
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_SETUP,
			     ":fpcibo=not_found\n");
		}
	}
#else
	{
		TOSHIBA_RBTX4927_SETUP_DPRINTK
		    (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
	}
#endif

#endif /* CONFIG_PCI */

#ifdef CONFIG_SERIAL_TXX9
	{
		extern int early_serial_txx9_setup(struct uart_port *port);
		struct uart_port req;
		for(i = 0; i < 2; i++) {
			memset(&req, 0, sizeof(req));
			req.line = i;
			req.iotype = UPIO_MEM;
			req.membase = (char *)(0xff1ff300 + i * 0x100);
			req.mapbase = 0xff1ff300 + i * 0x100;
			req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
			req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
			req.uartclk = 50000000;
			early_serial_txx9_setup(&req);
		}
	}
#ifdef CONFIG_SERIAL_TXX9_CONSOLE
        argptr = prom_getcmdline();
        if (strstr(argptr, "console=") == NULL) {
                strcat(argptr, " console=ttyS0,38400");
        }
#endif
#endif

#ifdef CONFIG_ROOT_NFS
        argptr = prom_getcmdline();
        if (strstr(argptr, "root=") == NULL) {
                strcat(argptr, " root=/dev/nfs rw");
        }
#endif


#ifdef CONFIG_IP_PNP
        argptr = prom_getcmdline();
        if (strstr(argptr, "ip=") == NULL) {
                strcat(argptr, " ip=any");
        }
#endif


	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
			       "+\n");
}

void __init
toshiba_rbtx4927_time_init(void)
{
	mips_hpt_frequency = tx4927_cpu_clock / 2;
	if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
		txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
				     TXX9_IRQ_BASE + 17,
				     50000000);
}

static int __init toshiba_rbtx4927_rtc_init(void)
{
	static struct resource __initdata res = {
		.start	= 0x1c010000,
		.end	= 0x1c010000 + 0x800 - 1,
		.flags	= IORESOURCE_MEM,
	};
	struct platform_device *dev =
		platform_device_register_simple("rtc-ds1742", -1, &res, 1);
	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
}
device_initcall(toshiba_rbtx4927_rtc_init);

static int __init rbtx4927_ne_init(void)
{
	static struct resource __initdata res[] = {
		{
			.start	= RBTX4927_RTL_8019_BASE,
			.end	= RBTX4927_RTL_8019_BASE + 0x20 - 1,
			.flags	= IORESOURCE_IO,
		}, {
			.start	= RBTX4927_RTL_8019_IRQ,
			.flags	= IORESOURCE_IRQ,
		}
	};
	struct platform_device *dev =
		platform_device_register_simple("ne", -1,
						res, ARRAY_SIZE(res));
	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
}
device_initcall(rbtx4927_ne_init);